ML410 BSB Design Creation Using 8.2i SP1 EDK Base System Builder (BSB)

April 2007

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Overview• Hardware Setup• Software Requirements• Create a BSB System Build (BSB) in EDK• Generate a Bitstream • Transfer the Bitstream onto the FPGA• Loading a Bootloop into the Block RAM

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ML410 BSB Hardware• The ML410 BSB design

hardware includes:– 64 KB BRAM– DDR1 Interface (64 MB)– UART– Interrupt Controller– System ACE Interface– IIC – GPIO (LEDs and LCD)– PLB2OPB Bridge– PLB and OPB Arbiters– Networking– OPB2PLB Bridge– OPB2PCI Bridge– PCI Arbiter

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Additional Setup Details• Refer to ml410_overview_setup.ppt for details on:

– Software Requirements– ML410 Board Setup

• Equipment and Cables• Software• Network

– Terminal Programs• This presentation requires the

9600-8-N-1 Baud terminal setup

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Hardware Setup• Connect the Xilinx Parallel

Cable IV (PC4) to the ML410 board

• Connect the RS232 nullmodem cable to the ML410 board

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ISE Software Requirement• Xilinx ISE 8.2i SP2 software

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EDK Software Requirement• Xilinx EDK 8.2i SP1 software

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Software Setup• Start the Terminal Program:

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Run Xilinx Platform Studio• Open Xilinx Platform

Studio• Select File →

New Project… (1)

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Run Xilinx Platform Studio• Select Base System Builder wizard (1)

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Create Base System Build• Enter the path and file name:

C:\ml410_bsb_design\ml410_bsb_system.xmp (1)• Click OK (2)

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Create BaseSystem Build

• Create a new design (1) • Click Next (2)1

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Create BaseSystem Build

• Select (1):– Board Vendor: Xilinx– Board Name: ML410– Board Revision: B

• Click Next (2)

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Note: This is also the correct setting for RevC and RevD boards

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Create BaseSystem Build

• Select the PowerPCprocessor (1)

• Click Next (2)1

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• Change the Processor Clock Frequency to 300 MHz (1)

• Click Next (2)

Create BaseSystem Build

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• RS232_Uart_1 – Select OPB UART16550

Peripheral (1)– Select Use Interrupt (2)

• De-select RS232_Uart_2 (3)• Click Next (4)

Create BaseSystem Build

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• SPI_EEPROM– Select Use Interrupt (1)

• Click Next (2)

Create BaseSystem Build

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• PCI32_BRIDGE– Select Use Interrupt (1)

• SysACE_CompactFlash – Select Use Interrupt (2)

• IIC_BUS– Select Use Interrupt (3)

• Click Next (4)

Create BaseSystem Build

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• De-selectEthernet_MAC (1)

• TriMode_MAC_GMII (2)– Select Use Interrupt (3)

• Click Next (4)

Create BaseSystem Build

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• Click Next (1)

Create BaseSystem Build

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• PLB BRAM IF CNTLR– Change the memory

size from 16 KBto 64 KB (1)

• Click Next (2)

Create BaseSystem Build

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• Leave this window as is• Click Next (1)

Create BaseSystem Build

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• Leave this window as is• Click Next (1)

Create BaseSystem Build

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• Leave this window as is• Click Next (1)

Create BaseSystem Build

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• Create the Base System Build– Click Generate (1)

Create BaseSystem Build

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• Finalize the creation of the Base System Build– Click Finish (1)

Create BaseSystem Build

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Create Base System Build• Before generating

a bitstream the MHS and UCF files (1) must be updated

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Create Base System Build• Open the

ml410_bsb_system.mhs (1)

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Update MHS• Add this parameter to the plb_v34 (1):

– PARAMETER C_NUM_OPBCLK_PLB2OPB_REARB = 100

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Create Base System Build• Open the

ml410_bsb_system.ucf (1)

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Update UCF• Edit this timespec (1):

– From: TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps;– To: TIMESPEC "TS_PCI_BUS" = FROM "PCI_CLK" TO "SYS_CLK" 9.9ns datapathonly;

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See Answer Record 22677 for detailswww.BDTIC.com/XILINX

Update ucf• Add these lines to the ml410_bsb_system.ucf and

save:#### AR 22677

AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139;

INST "opb2plb" AREA_GROUP = "opb2plb";AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111;INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom";AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191;INST "plb2opb" AREA_GROUP = "pblock_plb2opb";INST "plb/plb/*?/_n*" AREA_GROUP = "pblock_plb2opb";INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb";

See Answer Record 22677 for detailswww.BDTIC.com/XILINX

Update TestApp• Open TestApp_Peripheral/src/xtemac_example.h• Change the PHY Address from 0 to 7

– #define TEMAC_PHY_ID 7

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See Answer Record 24004 for detailswww.BDTIC.com/XILINX

Update TestApp• Open TestApp_Peripheral/src/xtemac_example_util.c• Add this line twice as shown here (1):

– usleep(1000000);

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See Answer Record 24004 for detailswww.BDTIC.com/XILINX

Generate Bitstream• Generate the libraries

needed to create the bitstream– Select Software →

Generate Librariesand BSPs (1)

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Generate Bitstream• Compile the TestApp

project and create an executable (executable.elf)– Select Software →

Build All User Applications (1)

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Generate Bitstream• Create the

hardware design, ml410_bsb_system.bit that is located in<project directory>/implementation– Select Hardware →

Generate Bitstream(1) (Takes roughly 40 minutes)

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Download the Bitstream• Initialize the compiled

TestApp project in the block RAM and download the new bitstream (download.bit)– Select Device

Configuration →Download Bitstream (1)

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Download the Bitstream • View the output of a successful bitstream download

in the terminal window

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Loading Bootloop into BRAM• A concatenated software/hardware file, known as

an ACE file, is useful for loading large programs, such as a Linux, VxWorks, or U-Boot into the external memory

• A bootloop program must be used to occupy the processor until the software is loaded into memory

• The following pages show how to initialize a bootloopprogram into block RAM and to test its existence

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Loading Bootloop into BRAM• Right-click the

TestApp_Memoryproject and de-select Mark to Initialize BRAMs (1)

• This will prevent the TestApp program from being inserted into the block RAM when the new bitstream is created

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Loading Bootloop into BRAM• Right-click the

ppc405_0_bootloop project and select Mark to InitializeBRAMs (1)

• Now the bootloop will be instantiated into block RAM rather than the TestApp_Memory project

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Loading Bootloop into BRAM• Update the bitstream

(download.bit) with a bootloop ELF file (ppc405_0.elf)– Select Device

Configuration →Update Bitstream (1)

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Loading Bootloop into BRAM• Load the new design

onto the FPGA and load the bootloopprogram into the blockRAM– Select Device

Configuration →Download Bitstream (1)

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Loading Bootloop into BRAM• A memory read can

be executed to test if bootloop was successfully loaded– Select Debug →

Launch XMD (1)– Select ppc405_0 (2)

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XMD Setup• The first time XMD runs

on a project, the options must be set– Click OK (1)– Click Save (2)

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Loading Bootloop into BRAM• XMD opens and connects to the processor, using the default

options

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Loading Bootloop into BRAM• To execute a memory read, type mrd 0xfffffffc• This will read the memory address at the reset vector; the

value should be 0x48000000 as shown below

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Loading Bootloop into BRAM• Make a copy of the updated bitstream (download.bit) and

rename it ml410_bsb_bootloop.bit• This bootloop bitstream will be used in future designs

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AppendixAdding the Null Tiles

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Null Tiles• AR 23410 – Needed to preserve unused MGTs for future

designs• Step 1 – Download the null tile pcore

– Unzip this to the <design dir>/pcores

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Null Tiles• Step 2 – Update the UCF file

– AR 23410 has the UCF File changes for the Virtex-4 FX60-FF1152– Paste these constraints into your <Design

dir>/data/ml410_bsb_system.ucf file:

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Null Tiles• Step 3 – Update the MHS file

– AR 23410 has the MHS file changes for the Virtex-4 FX60-FF1152– Paste these lines (ports and pcore instantiations) into your <Design

dir>/ml410_bsb_system.mhs file:

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Null Tiles• Step 4 –

Recompile the bitstream

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Available Documentation• Platform Studio Documentation

– Embedded Development Kit (EDK) Resourceshttp://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm

• ML410– ML410 User's Guide

http://www.xilinx.com/bvdocs/userguides/ug085.pdf– ML410 Overview

http://www.xilinx.com/ml410– ML410 Schematics

http://www.xilinx.com/products/boards/ml410/docs/ml410_revE.pdf

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