timing closure today - university of california, los...

The Quest for Synthesis and Layout Timing Closure

8 June 2000

DAC 2000 - A.D. Drumm 1

9 June 2000 DAC 2000 - The Quest - A.D. Drumm 1

Timing Closure Today

Tony DrummTony DrummIBM CorporationIBM CorporationRochester, MNRochester, MN

[email protected]@us.ibm.com


Agenda

nn Traditional design flowsTraditional design flowsnn Timing analysisTiming analysisnn Transformations for timing correctionTransformations for timing correctionnn Some of the current problemsSome of the current problemsnn PostPost--placement optimizationplacement optimizationnn SummarySummary


8 June 2000



Agenda



Traditional Design FlowsDesign Entry

Synthesis

Timing

Place

Timing

Route

Timing

1. Tech independent optimization

2. Tech mapping

3. Rudimentary timing correction


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Logic Synthesis Flow

nn Technology independent optimizationTechnology independent optimizationuu General goal: reduce connections, literals, General goal: reduce connections, literals,

redundancies, arearedundancies, area

nn Technology mappingTechnology mappinguu Map logic into technology library Map logic into technology library

nn Timing correctionTiming correctionuu Find and fix critical timing pathsFind and fix critical timing pathsuu Fix electrical violations (load, slew)Fix electrical violations (load, slew)


Traditional Design FlowsDesign Entry

Synthesis w/Timing

Place w/Timing

Route

Timing

Integrate timing with synthesis and placement

1. Tech independent optimization

2. Tech mapping

3. Timing correction


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Tools of Timing Correction

Transformations Drivers

Analysis Checking




Analysis Checking


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Timing Correction Method

nn What to apply ?What to apply ?uu Transformations (or Transformations (or transformstransforms))

FF Change the structure of the design without changing Change the structure of the design without changing the function of the designthe function of the design




Analysis Checking


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nn Where to apply it ?Where to apply it ?uu DriversDrivers

FF Traverse the design to find the best place to apply Traverse the design to find the best place to apply transformstransforms




Analysis Checking


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nn Is it beneficial?Is it beneficial?uu AnalysisAnalysis

FF Timing: Static Timing AnalysisTiming: Static Timing AnalysisFF Others: Noise analysis, power analysis, etcOthers: Noise analysis, power analysis, etc




Analysis Checking


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nn Is it legal ?Is it legal ?uu CheckingChecking

FF Logical correctnessLogical correctnessFF Electrical correctness Electrical correctness


Agenda



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Timing Analysis

nn Give accurate time values on each pin/port Give accurate time values on each pin/port of the networkof the network

nn Has to deal with design changes in Has to deal with design changes in optimization toolboxoptimization toolbox

nn StaticStatic Timing AnalysisTiming Analysisuu Simulation far too slow in optimization Simulation far too slow in optimization

environmentenvironmentuu Accuracy is more than enoughAccuracy is more than enough


Timing Analysis Requirements

nn Choose combination of timing analyzer and delay Choose combination of timing analyzer and delay calculator which are appropriate for level of calculator which are appropriate for level of designdesignuu give the best accuracygive the best accuracyuu for performance that can be toleratedfor performance that can be tolerated

nn Timing Analysis / Delay calculation must be able Timing Analysis / Delay calculation must be able to cope with logic design changesto cope with logic design changesuu IncrementalIncrementaluu Highest performance possibleHighest performance possibleuu NonNon--linear delay equationslinear delay equations


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Timing Analysis Requirements

nn Must handle…Must handle…uu Difference between rising and falling delaysDifference between rising and falling delaysuu Delay dependent on slew rateDelay dependent on slew rateuu Slew and delay dependent on output loadSlew and delay dependent on output loaduu NonNon--linear delay equationslinear delay equations


Late Mode Analysis Definitions

nn Constraints: assertions at the boundariesConstraints: assertions at the boundaries–– Arrival times: Arrival times: ATATaa, , ATATbb

–– Required arrival time: Required arrival time: RATRATxx

nn Delay from Delay from aa to to xx is the longest time it takes to is the longest time it takes to propagate a signal from propagate a signal from aa to to xx

nn Slack is required arrival time Slack is required arrival time -- arrival time.arrival time.

a

b xc

yaAT

bATxRAT

axd


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Example

a

b xc

y0=aAT

1=bAT2=xRAT

3=xAT

132 −=−=xSL110 −=−=bSL

000 =−=aSL2=yAT

0=cAT

121 −=−=ySL

11

101 =−=cSL


Early mode analysis

0=aAT

1=bAT

2=xRAT

1=xAT

121 −=−=xSL101 =−=bSL

000 =−=aSL1=yAT

0=cAT

011 =−=ySL

a

b xc

y

nn Definitions change as followsDefinitions change as follows–– longestlongest becomes becomes shortestshortest–– slack = arrival slack = arrival -- requiredrequired

11

110 −=−=cSL


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Delay modeling

axda

bx

bxd

Propagation Arcs cl

d odclt _

ocld _

Test ArcTiming Model


Agenda



8 June 2000



Timing Correction

nn Fix electrical violationsFix electrical violationsuu Resize cellsResize cellsuu Buffer netsBuffer netsuu Copy (clone) cellsCopy (clone) cells

nn Fix timing problemsFix timing problemsuu Local transforms (bag of tricks)Local transforms (bag of tricks)uu PathPath--based transformsbased transforms


Local Transforms

nn Resize cellsResize cellsnn Buffer or clone to reduce load on critical netsBuffer or clone to reduce load on critical netsnn Decompose large cellsDecompose large cellsnn Swap connections on commutative pins or among Swap connections on commutative pins or among

equivalent netsequivalent netsnn Move critical signals forwardMove critical signals forwardnn Pad early pathsPad early pathsnn Area recoveryArea recovery


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Transform Example

Delay = 4

…..

Double Inverter

Removal

…..

…..

Delay = 2


Resizing

00.010.020.030.040.05

0 0.2 0.4 0.6 0.8 1load

d

A B C

b

ad

e

f

0.2

0.2

0.3

?

b

aA

0.035

b

aC

0.026


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Cloning

00.010.020.030.040.05

0 0.2 0.4 0.6 0.8 1load

d

A B C

b

a

d

e

f

g

h

0.2

0.2

0.2

0.20.2

?

b

a

d

ef

gh

A

B


Buffering

00.010.020.030.040.05

0 0.2 0.4 0.6 0.8 1load

d

A B C

b

a

d

e

f

g

h

0.2

0.2

0.2

0.20.2

? b

a

d

e

f

g

h0.1

0.2

0.2

0.20.2

BB

0.2


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Redesign Fan-in Treea

cd

b eArr(b)=3

Arr(c)=1

Arr(d)=0

Arr(a)=4

Arr(e)=61

1

1

cd

e

Arr(e)=51

1b1

a


Redesign Fan-out Tree

1

1

1

3

1

1

1

Longest Path = 5

1

1

1

3

1

2

Longest Path = 4Slowdown of buffer due to load


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Decomposition


Swap Commutative Pins

2

c

ab

2

1

0 1

1

1

3

a

cb

2

1

0

1

1

2

1 5

Simple Sorting on arrival times and delay works


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Move Critical Signals Forward

nn Based on ATPGBased on ATPG–– linear in circuit sizelinear in circuit size–– Detects redundancies Detects redundancies

efficientlyefficientlynn Efficiently find wires to Efficiently find wires to

be added and remove.be added and remove.–– Based on mandatory Based on mandatory

assignments.assignments.

ab

cd e

ab

edc


Path-based Transforms

nn PathPath--based resizingbased resizingnn Unmap Unmap / / remap remap a path or conea path or conenn Slack stealingSlack stealingnn RetimingRetiming


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Slack Stealingnn Take advantage of timing behavior of level sensitive registers Take advantage of timing behavior of level sensitive registers

(latches)(latches)

C1

C2Slack = 0

C1 C2

Slack = +1Slack = -1

C1

C20 1 2


Retiming

Delay=3

Delay=2

Forward

Backward


8 June 2000



Agenda



The Wall

nn Logic designers concentrate on logic and Logic designers concentrate on logic and timingtiming

nn Design work done in abstract world of gates Design work done in abstract world of gates and wire load modelsand wire load models

nn Throw design Throw design over the wallover the wall when completewhen completenn Physical designers concentrate on layout Physical designers concentrate on layout

and ability to routeand ability to routenn Effective method for many yearsEffective method for many years


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General CMOS Problems

nn Small voltagesSmall voltagesnn Low drive strengths / low powerLow drive strengths / low powernn Capacitance plays a large role in Capacitance plays a large role in

performanceperformancenn NoiseNoisenn Variability Variability –– range between slowest range between slowest

possible and fastest possiblepossible and fastest possible


Additional DSM Problems

nn High density / huge designsHigh density / huge designsnn Very thin and resistive wiresVery thin and resistive wiresnn Very high frequenciesVery high frequenciesnn Smaller voltages Smaller voltages nn Clock skew and latencyClock skew and latencynn Electromigration and noiseElectromigration and noise


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Clock Distribution Problems

nn Most common design approach requires Most common design approach requires close to zero skewclose to zero skew

nn CMOS / DSM problems all affect clocksCMOS / DSM problems all affect clocksnn Distribution problem increasingDistribution problem increasing

uu Number of latches/flipNumber of latches/flip--flops growing flops growing significantlysignificantly

nn Power consumed in clock tree significantPower consumed in clock tree significantuu ∆∆II and noise also of concernand noise also of concern


Problem Mitigation

nn Carry hierarchical logic design into physicalCarry hierarchical logic design into physicalnn Many metal layersMany metal layersnn Copper wires, thick wires to lower RCopper wires, thick wires to lower Rnn Other technology improvementsOther technology improvements

uu SOI, low kSOI, low knn More sophisticated clock designsMore sophisticated clock designsnn Improved analysisImproved analysisnn Custom designCustom design


8 June 2000



Hierarchy and Physical Design

nn Logical hierarchy can be carried over into Logical hierarchy can be carried over into physical designphysical design

nn Seems natural topSeems natural top--down approach, using down approach, using floorplanning floorplanning as a firm guide to physical as a firm guide to physical designdesign


Hierarchy and Physical DesignPros…nn Run time of P&R toolsRun time of P&R toolsnn Early (Early (and valuableand valuable) knowledge of global ) knowledge of global

wireswiresnn Wire delay within macro may be tolerableWire delay within macro may be tolerablenn Generally, contain the problem sizeGenerally, contain the problem sizenn May be the only real method availableMay be the only real method available


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Hierarchy and Physical DesignCons…nn Placement solution boundedPlacement solution boundednn Ability to find a routable solution hinderedAbility to find a routable solution hinderednn Hierarchy usually logicallyHierarchy usually logically--based, not based, not

physicallyphysically--basedbasednn Boundary conditions explode and must be Boundary conditions explode and must be

managed carefully to avoid surprisesmanaged carefully to avoid surprisesnn Pin assignment problem for all macrosPin assignment problem for all macros


Hierarchy Example Plots


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8 June 2000



Correlation Pre/Post-P&R

nn Many of the problems reduce to this:Many of the problems reduce to this:nn How good is the correlation between PreHow good is the correlation between Pre--

P&R estimates and PostP&R estimates and Post--P&R extraction?P&R extraction?nn If correlation is good…If correlation is good…

uu Problems detected and potentially fixed Problems detected and potentially fixed earlyearly

nn If correlation is bad…If correlation is bad…uu Problems detected Problems detected latelateuu Not a good situation!Not a good situation!


Correlation Pre/Post-P&RThe problemnn Can’t complete layout until logic design is Can’t complete layout until logic design is

completecompletenn Can’t complete logic design without timingCan’t complete logic design without timingnn Can’t time without load and net delay dataCan’t time without load and net delay datann Can’t extract load and net delay data until Can’t extract load and net delay data until

layout is completelayout is completenn Can’t complete layout …Can’t complete layout …


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Correlation Pre/Post-P&RCommon solutionnn Don’t know specific layout dataDon’t know specific layout datann But we know something about statistical But we know something about statistical

propertiespropertiesnn Average net load, average net delayAverage net load, average net delaynn Further refine using other characteristicsFurther refine using other characteristics

uu Number of sinksNumber of sinksuu Size of design (number of circuits)Size of design (number of circuits)uu Physical sizePhysical size


Correlation Pre/Post-P&RUsing averagesnn Wire load modelsWire load models give synthesis an give synthesis an estimateestimate

of physical designof physical designnn We can correlate averages preWe can correlate averages pre-- and postand post--

P&R as accurately as neededP&R as accurately as needednn If specific design has average behavior, its If specific design has average behavior, its

timing, timing, on averageon average, can be predicted, can be predictednn Otherwise, a pass through placement can Otherwise, a pass through placement can

provide data needed to adjust modelprovide data needed to adjust model


8 June 2000



Correlation Pre/Post-P&RTiming and averagesnn Statistics are important to timing analysisStatistics are important to timing analysisnn However, cycle time dictated by the worst However, cycle time dictated by the worst

specificspecific pathpathnn That path is built of That path is built of individualindividual netsnetsnn One net can determine the speed of an One net can determine the speed of an

entire designentire designnn Reality: poor correlation for relatively few Reality: poor correlation for relatively few

nets can cause major headachesnets can cause major headaches


Correlation Pre/Post-P&RAverages and Wire Loads

Distribution of C / fan-out

05000

1000015000200002500030000

0 10 20 30 40 50 60 70 80 90 100 110

pF per fan-out

Num

ber

of n

ets medianmedian meanmean


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Correlation Pre/Post-P&RCwire Data by Logic Design

Cwire

Number of fan-outs


Correlation Pre/Post-P&RBack annotationnn How can we use information from one pass How can we use information from one pass

through physical design?through physical design?nn Adjust wire load model coefficientsAdjust wire load model coefficientsnn Back annotateBack annotate specific net load and delay specific net load and delay

data to the logic designdata to the logic designnn New problem: correlation of logic preNew problem: correlation of logic pre-- and and

postpost--synthesissynthesisnn This correlation may be impossibleThis correlation may be impossible


8 June 2000



Transform Example

Delay = 4

…..

Double Inverter

Removal

…..

…..

Delay = 2


Agenda



8 June 2000



Post-Placement OptimizationDesign Entry

Synthesis w/Timing

Place

Route

Timing

Synthesis w/Timing

1. In-place optimizations

2. Minimally disturb placement optimizations


Post-Placement Optimization

nn InIn--placeplaceuu Resizing (carefully)Resizing (carefully)uu Pin swapping, some tree rebuildingPin swapping, some tree rebuildinguu Wire sizing / typingWire sizing / typing

nn Minimally disruptiveMinimally disruptiveuu ResizingResizinguu BufferingBufferinguu CloningCloninguu Tree rebuildingTree rebuildinguu Cell removalCell removal


8 June 2000



In-place Optimization

nn Not Not tootoo difficultdifficultnn Can use extracted electrical data (C, RC) Can use extracted electrical data (C, RC)

from placement toolfrom placement tooluu Some changes affect pin locations, but may be Some changes affect pin locations, but may be

ignoredignoreduu Tree rebuilding needs incremental extractionTree rebuilding needs incremental extraction

nn Can use timing reports for timing dataCan use timing reports for timing datauu But, accuracy suffers as changes are madeBut, accuracy suffers as changes are made


In-place Optimization

Placement & extraction

Placed netlist

C/RC data

Optimization

Opt’d netlist

Resize swap pins

rebuild trees


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Place-disruptive Optimization

nn Nets changing implies…Nets changing implies…uu Must be able to recompute C and RCMust be able to recompute C and RCuu May need to incrementally place new cellsMay need to incrementally place new cellsuu Need incremental timing capabilityNeed incremental timing capability


Place-disruptive Optimization

Placement & extraction

Placed netlist

C/RC data

Optimization with placer,

timer, extractor

Opt’d netlist

Resize buffer clone

cell removal rebuild trees


8 June 2000



Post-Placement Example -Buffering long wires


Sample Optimization Results

.18 .18 µµmm7.5 ns7.5 ns--4 / 10004 / 1000--11 / 200011 / 2000--0.5 / 5000.5 / 500V2V2

placedplaced optoptpreplacepreplace

.25 .25 µµmm8 ns8 ns--13 / 20k13 / 20k--97 / 43k97 / 43k--0.4 / 1000.4 / 100P1P1

.18 .18 µµmm2.52.5--10 ns10 ns--6 / 62k6 / 62k--48 / 164k48 / 164k--0.5 / 20000.5 / 2000T1T1

.18 .18 µµmm7.5 ns7.5 ns--0.3 / 1000.3 / 100--12 / 15k12 / 15k0 / 00 / 0V1V1

.25 .25 µµmm7.5 ns7.5 ns--2 / 14002 / 1400--12 / 38k12 / 38k--1 / 20001 / 2000C1C1

TechTechCycle Cycle timetime

Worst slack / # missesWorst slack / # missesDesignDesign


8 June 2000



Fix My Clocks… Please!

nn Zero skew is not necessaryZero skew is not necessarynn CMOS uncertainties are worrisome, but…CMOS uncertainties are worrisome, but…nn Freedom to adjust clocks arrival times at Freedom to adjust clocks arrival times at

memory elements provides another memory elements provides another powerful timing closure toolpowerful timing closure tool

nn Similar to retiming but less disruptiveSimilar to retiming but less disruptive


Post-Placement Challenges

nn Getting the timing rightGetting the timing rightuu Different timers used at different stagesDifferent timers used at different stagesuu Does the optimizer see the same worst paths as Does the optimizer see the same worst paths as

the signthe sign--off timer?off timer?uu Timing analysis is an act of faithTiming analysis is an act of faith –– Drumm’s Drumm’s

third lawthird law

nn Design size / tool capacityDesign size / tool capacityuu Using synthesis technology on flat designsUsing synthesis technology on flat designs


8 June 2000




nn Incompatible tools, formatsIncompatible tools, formatsuu Placer, synthesizer, timer may all use different Placer, synthesizer, timer may all use different

file format, may all be different vendorsfile format, may all be different vendorsuu Basic interoperability issuesBasic interoperability issues

nn Incremental placer needed for new cellsIncremental placer needed for new cellsuu Doesn’t have to be smartDoesn’t have to be smartuu But might produce some infeasible solutionsBut might produce some infeasible solutionsuu Must be integrated with optimizerMust be integrated with optimizer



nn Extraction of net dataExtraction of net datauu Steiner tree estimationSteiner tree estimationuu Net C and delay (RC) calculatorNet C and delay (RC) calculatoruu Do results match other extraction tools?Do results match other extraction tools?uu Any optimization which significantly alters net Any optimization which significantly alters net

topology needs this abilitytopology needs this abilityFF Insert cellsInsert cellsFF Remove cellsRemove cellsFF Move connections except locallyMove connections except locally


8 June 2000



Good News

nn The biggest improvements come from the The biggest improvements come from the simplest transformationssimplest transformationsuu Resizing easiest Resizing easiest –– most importantmost importantuu Buffering Buffering –– fixes many placementfixes many placement--induced induced

missesmissesuu Pin swapping and tree rebuilding Pin swapping and tree rebuilding –– don’t don’t

require a placer, don’t affect placement at allrequire a placer, don’t affect placement at all


Bad News

nn Cycle time and technology advances Cycle time and technology advances demand more and more sophisticated demand more and more sophisticated optimization techniquesoptimization techniques

nn Disconnect among various tools involved Disconnect among various tools involved increases turnincreases turn--aroundaround--time and limits time and limits optimization optimization


8 June 2000



Good News

nn The Bad News is commonly recognizedThe Bad News is commonly recognizednn Many tool vendors, academics, inMany tool vendors, academics, in--house house

EDA researchers are working to solve these EDA researchers are working to solve these problemsproblems

nn The problems will be solvedThe problems will be solved


Bad News

nn These problems won’t be the last!These problems won’t be the last!nn Like frequencies, density, complexity Like frequencies, density, complexity –– new new

problems will be discovered at an ever problems will be discovered at an ever increasing rateincreasing rate


8 June 2000



Agenda



Summary

nn Timing correction methods fairly matureTiming correction methods fairly maturenn Technology and frequency present new Technology and frequency present new

problemsproblemsnn Synthesis techniques can be used Synthesis techniques can be used

successfully postsuccessfully post--placementplacementnn Better integration and interoperability are Better integration and interoperability are

needed to solve newest problems and take needed to solve newest problems and take us into the futureus into the future


8 June 2000



Acknowledgements

nn Leon Leon StokStoknn Alex Alex SuessSuessnn JosJoséé NevesNevesnn Bill JoynerBill Joynernn IBM Rochester EDA folksIBM Rochester EDA folks


timing closure today - university of california, los...

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