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© Copyright 2018 Xilinx Presented By Ron Plyler Product Marketing, Vivado Implementation Tools December 10, 2018 Timing Closure Tips and Tricks

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Page 1: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Presented By

Ron Plyler

Product Marketing, Vivado Implementation Tools

December 10, 2018

Timing Closure Tips and Tricks

Page 2: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Topics for Today

˃ Implementation Flow: Built for Timing Closure

˃ SSI Design: Tips for Maximizing Performance

˃ Timing Closure: Automating Solutions

Page 3: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Implementation Flow

Built for Timing Closure

Page 4: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Start New Projects with Latest Vivado Versions

2012-2013 2013-2014 2015-2016 2017-2018+

opt_design opt_design+HFN global buffering

opt_design+Hierarchy-based replication

driver merging

opt_design

power_opt_design power_opt_design power_opt_design power_opt_design

place_design place_design place_design place_design+PSIP (phys_opt_design replication,

MAX_FANOUT support)

+HFN global buffering

+phys_opt_design+replication, retiming, and re-placement

phys_opt_design phys_opt_design+SLR crossing optimization

route_design route_design route_design route_design+PSIR (phys_opt_design replication and re-routing)

+phys_opt_design (post-route)+critical path replication and re-routing

phys_opt_design+SLR crossing optimization

More and more Timing Closure features built into Implementation

Bold indicates required flow step

Page 5: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

-directive AggressiveExplore (2018.3)

+More exhaustive thresholds and effort levels

Core Placement and Routing Improvements

˃ Replication provides better default QoR

PSIP (Physical Synthesis In Placer) enabled by default starting 2018.2

New MAX_FANOUT recommendations

‒ Synthesis: use MAX_FANOUT only on local, low-fanout replication, not design-wide signals

‒ PSIP: use MAX_FANOUT to suggest replication candidate nets during placement phase

PSIR (Physical Synthesis In Router) introduced 2018.1 for UltraScale+

˃ Router directives for higher design performance

New directives built on top of Explore

More runtime tradeoffs-directive NoTimingRelaxation

+Maintain original timing targets (don’t relax)

-directive ExplorePost-route critical path optimization

US+ clock skew optimization

Page 6: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

The New Incremental Compile Flow

Incremental ImplementationIncremental Synthesis

Reference

RTL synth Reference

Synth DCPimpl Reference

Impl DCP

Revised

RTL synth impl Incremental

Impl DCP

Incremental

Synth DCP

read_checkpoint

-incremental

read_checkpoint

-incremental

write_checkpoint

-incremental_synthwrite_checkpoint

˃ Incremental Synthesis and Implementation bolt together to reduce compile time and preserve timing-closed results

˃ Incremental Synthesis minimizes netlist changesRequires write_checkpoint -incremental_synth option to save incr data

Page 7: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Automatic Incremental Implementation for Projects

˃ Pushbutton mode where Vivado manages Incremental DCP for each run

launch_runs

implIncremental

Impl DCP

Revised

Synth DCP

Reference

Impl DCP

New in 2018.3Recirculates latest routed DCP as the reference DCP

‒ if it is a good fit

Reference DCP added to sources in utility_1 fileset

‒ Captured in project archives

Page 8: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

SSI Design

Tips for Maximizing

Performance

Page 9: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Proliferating SSI as the Platform of Choice

˃ Vivado placement and routing are continuously improving in

basic key areas

Delay Estimation - more accurate pre-route modeling of SLR crossings

Congestion - better spreading near SLR crossings

SLR Crossing Speed - more opportunistic use of SLL registers

˃ New features improve quality of Partitioning and Placement

USER_SLR_ASSIGNMENT: Control partitioning of cells

USER_CROSSING_SLR (EA): Control partitioning based on nets/pins

Laguna TX_REG -> RX_REG direct connection (UltraScale+ only)

USER_SLL_REG (EA): SLL (Laguna) register preference to improve speed, predictability

SLLs

SLR2

SLR1

SLR0

VU9P: 3 SLRs

Page 10: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Partitioning with USER_SLR_ASSIGNMENT

˃ Hierarchical cell property (not for leaf cells)

Assigns cells to SLR when SLR name is used: SLR0, SLR1, SLR2, ...

Keeps cells in same SLR when value is a string

Tries to prevent cells from crossing SLR boundaries

˃ More flexible than Pblocks

Soft constraint, ignored if prevents successful partition

Placer, PhysOpt not restricted by Pblock bounds

˃ Add pipeline registers on cell boundaries

Helps maintain clock speed

Allows even greater placement flexibility

SLR1

SLR0

Add pipeline

registers for

placement

flexibility

IP2

IP3

IP1

IP4 IP5

set_property USER_SLR_ASSIGNMENT SLR1 {IP1 IP2}

set_property USER_SLR_ASSIGNMENT SLR0 IP3

set_property USER_SLR_ASSIGNMENT group0 {IP4 IP5}

Page 11: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

USER_CROSSING_SLR (Early Access Until 2018.3)

˃ Soft constraint: pin/net property for fine-tuning SLR partitioning

˃ Specifies a preference that connections should cross an SLR boundary

True applies only to single-fanout pipeline register connections

False applies to any net or input pin except internal library macros: PRIMITIVE_LEVEL == INTERNAL (restriction removed in 2018.3)

SLR

Boundary

Apply FALSE

Apply TRUE

Register pipeline

for traversing SLRs

Page 12: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Using UltraScale+ SLL Registers

˃ TX_REG can drive RX_REG directly (2018.1)

Router adjusts leaf clock skews to fix hold

Fits most intra-clock topologies

Not for use with Clock Domain Crossings

˃ Use USER_SLL_REG register property (2018.3)

Easier method to move register from fabric to nearby Laguna register

Similar behavior as IOB property

˃ Use BEL and LOC to constrain and lock SLR

crossing interfaces

Register pipelines

for traversing SLRs

Consistent crossing performance

Laguna

Column

Reduced vertical

congestion for

wide bus crossings

Page 13: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Timing Closure

Automating Solutions

Page 14: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

report_qor_suggestions (RQS)

˃ Reduce timing closure time and effort (Introduced in 2017.1)

˃ Run report and follow suggestions

˃ Example: RQS analysis generated suggestions to:

Improve congestion

Improve critical paths ending at control pins

RQSPreSynth.xdc output file

Page 15: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Applying Suggestions

synth_1 impl_1 RQS Suggestions

RQSPreSynth

RQSImplCommon

RQSPreImpl

RQSImplCommon

Relaunch

current run

synth_2 impl_2

RQSPreSynth

RQSImplCommon

RQSPreImpl

RQSImplCommon

Or copy run

and launch

Launch

Runs

˃ RQS Automation Roadmap

2018.3: Interactively create & launch runs

2019.X: Integrate Incremental Compile

2019.X: Dynamically update suggestions

throughout the flow

> Design sources frozen?

Start with Implementation

> Design sources in development?

Start with Synthesis

> Add RQS XDC and Tcl.pre files

Page 16: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Introducing report_qor_assessment (RQA) in 2018.3

˃ How likely will design goals be met? Evaluates an entire design and generates a

simple score

Implementation will fail, stop flow

Timing will fail, review RQS

Timing difficult, add many strategies

Timing fair, add a few strategies

Timing easy to meet

1

2

3

4

5

Assessment Scores

Page 17: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Assessment and RQS Suggestion Integration

report_qor_suggestions

Suggester

report_qor_assessment

Assessor Timing

Utilization

Congestion

Clocking

Constraints

Prioritized

Scoring

Overall design

assessment: 1-5

Timing

Assessment is used to generate RQS suggestions

Suggestion

Database

Congestion

Utilization

Clocking

Constraints

RQS

Presynth

RQS

PreImpl

RQS

ImplCommon

Suggestions:

Tcl/XDC

ML Custom

Strategies

(Roadmap)

Page 18: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx

Summary

˃ Begin new projects with the latest Vivado version

2018.3 planned for mid-December

˃ Use Incremental Compile to reduce compile times and preserve timing closure

˃ Apply new SSI constraints to improve UltraScale and UltraScale+ performance

˃ Benefit from automated analysis and solutions: report_qor_assessment (2018.3)

and report_qor_suggestions (Now)

˃ Please share feedback on problems and improvements

Page 19: Timing Closure Tips and Tricks - Xilinx · 2018-12-20 · Title: Timing Closure Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:41:48 PM

© Copyright 2018 Xilinx


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