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STUDY PACKAGE 1e

GATEINSTRUMENTATION ENGINEERING

Vol 4 of 5

► BASICS OF CIrCUITS

► AnAlOG ElECTrOnICS

► DIGITAl ElECTrOnICS

R. K. Kanodia Ashish Murolia

nODIA & COMPAnY

GATE Instrumentation Engineering Vol 4 of 5RK Kanodia and Ashish Murolia

Copyright © By NODIA & COMPANY

Information contained in this book has been obtained by author, from sources believes to be reliable. However, neither NODIA & COMPANY nor its author guarantee the accuracy or completeness of any information herein, and NODIA & COMPANY nor its author shall be responsible for any error, omissions, or damages arising out of use of this information. This book is published with the understanding that NODIA & COMPANY and its author are supplying information but are not attempting to render engineering or other professional services.

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To Our Parents

PrEFACE

The objective of this study package is to develop in the GATE aspirants the ability to solve GATE level problems of Instrumentation Engineering Paper. The highly increased competition in GATE exam from last few years necessitate an in-depth knowledge of the concepts for the GATE aspirants. There are lots of study packages available for GATE Instrumentation Engineering, which includes the theory and problem sets. But through this package our notion is to develop the problem solving approach rather than just introducing the theory and problem set. This study package fulfills all the requirements of a GATE aspirant to prepare for the exam.

There is no special pre-requisite before starting this study package. Although it is always recommended to refer other standard text books to clear doubts in a typical problem. The study package is published in 5 different volumes that cover the different subjects of GATE Instrumentation Engineering Paper. As the weightage of General Aptitude and Engineering Mathematics in the Instrumentation Engineering paper are 15 % each, and the subjects are very much wide in the syllabus; these subjects are published in separate volumes to provide practice problem set on all the important topics of the subjects. Rest three volumes cover the core subjects of GATE Instrumentation Engineering.

In the very first volume of this study package, General Aptitude is introduced. General aptitude is divided into two sections: verbal ability and numerical ability. Some important rules of grammar is introduced at the starting of verbal ability section, and then different types of verbal ability problems are given in separate chapters. At the end of each chapter answers of the problems are described with detailed theory and grammatical rule. The numerical ability part does not include theory as it is expected from an engineering students that they are very well known to the basic mathematical formulas of under 10th class. In numerical ability section, the chapters are organized such as to cover all types of problems asked in previous GATE papers. There is the detailed solutions available for each of the numerical ability problems such that even an average student can clear his/her doubts easily.

In volume 2 of the study package, Engineering Mathematics is introduced. Each chapter of Engineering Mathematics introduces a brief theory with problem solving methodology and important formulas at the starting and then the problems are given in a graded manner from basic to advance level. At last, the solutions are given with a detailed description of formulas and concepts used to solve it.

Volumes 3, 4 and 5 include the core subjects of instrumentation. The subjects with interrelated topics are taken in the same volume. Volume 3 includes the subjects:

Basics of Measurement Systems; Electrical & Electronic Measurement; Transducers, Mechanical Measurement and Industrial Instrumentation; Analytical, Optical & Biomedical Instrumentation. Volume 4 includes the subjects: Basics of Circuits, Analog Electronics, Digital Electronics. Volume 5 includes the subjects: Signals & Systems; Communication Systems; Control Systems and Process Control. For each of the subjects, the chapters are organized in a manner to cover the complete syllabus with a balanced number of problems on each topic. In starting of each chapter, a brief theory is given that includes formula, problem solving methodology and some important points to remember. There are enough number of problems to cover all the varieties, and the problems are graded from basic to advance level such that a GATE aspirant can easily understand concepts while solving problems. Each and every problems are solved with a good description to avoid any confusion or doubt.

There are two types of problems being asked in GATE exam: MCQ (Multiple Choice Questions) and NAT (Numerical Answer Type questions). Both type of problems are given in this study package. Solutions are presented in a descriptive and step-by-step manner. The diagrams in the book are clearly illustrated. Overall, a very simple language is used throughout this study package to facilitate easy understanding of the concepts.

We believe that each volume of GATE Study Package helps a student to learn fundamental concepts and develop problem solving skills for a subject, which are key essentials to crack GATE. Although we have put a vigorous effort in preparing this book, some errors may have crept in. We shall appreciate and greatly acknowledge all constructive comments, criticisms, and suggestions from the users of this book at [email protected]

We wish you good luck !

Authors

Acknowledgements

We would like to express our sincere thanks to all the co-authors, editors, and reviewers for their efforts in making this project successful. We would also like to thank Team NODIA for providing professional support for this project through all phases of its development. At last, we express our gratitude to God and our Family for providing moral support and motivation.

Authors

SYllABUS

General Aptitude (GA):Verbal Ability : English grammar, sentence completion, verbal analogies, word groups, instructions, critical reasoning and verbal deduction.

Numerical Ability : Numerical computation, numerical estimation, numerical reasoning and data interpretation.

Section 1 : Engineering MathematicsLinear Algebra: Matrix algebra, systems of linear equations, Eigen values and Eigen vectors.

Calculus: Mean value theorems, theorems of integral calculus, partial derivatives, maxima and minima, multiple integrals, Fourier series, vector identities, line, surface and volume integrals, Stokes, Gauss and Green’s theorems.

Differential equations: First order equation (linear and nonlinear), higher order linear differential equations with constant coefficients, method of variation of parameters, Cauchy’s and Euler’s equations, initial and boundary value problems, solution of partial differential equations: variable separable method.

Analysis of complex variables: Analytic functions, Cauchy’s integral theorem and integral formula, Taylor’s and Laurent’s series, residue theorem, solution of integrals.

Probability and Statistics: Sampling theorems, conditional probability, mean, median, mode and standard deviation, random variables, discrete and continuous distributions: normal, Poisson and binomial distributions.

Numerical Methods: Matrix inversion, solutions of non-linear algebraic equations, iterative methods forsolving differential equations, numerical integration, regression and correlation analysis.Instrumentation Engineering

Section 2: Electrical Circuits: Voltage and current sources: independent, dependent, ideal and practical; v - i relationships of resistor, inductor, mutual inductor and capacitor; transient analysis of RLC circuits with dc excitation.

Kirchoff’s laws, mesh and nodal analysis, superposition, Thevenin, Norton, maximum power transfer and reciprocity theorems.

Peak-, average- and rms values of ac quantities; apparent- active- nd reactive powers; phasor analysis, impedance and admittance; series and parallel resonance, locus diagrams, realization of basic filters with R, L and C elements.

One-port and two-port networks, driving point impedance and admittance, open-, and short circuit parameters.

Section 3: Signals and Systems Periodic, aperiodic and impulse signals; Laplace, Fourier and z-transforms; transfer function, frequency response of first and second order linear time invariant systems, impulse response of systems; convolution, correlation. Discrete time system: impulse response, frequency response, pulse transfer function; DFT and FFT; basics of IIR and FIR filters.

Section 4: Control SystemsFeedback principles, signal flowgraphs, transient response, steady-state-errors, Bode plot, phase and gain margins, Routh and Nyquist criteria, root loci, design of lead, lag and lead-lag compensators, state-space representation of systems; time-delay systems; mechanical, hydraulic and pneumatic system components, synchro pair, servo and stepper motors, servo valves; on-off, P, P-I, P-I-D, cascade, feedforward, and ratio controllers.

Section 5: Analog Electronics Characteristics and applications of diode, Zener diode, BJT and MOSFET; small signal analysis of transistor circuits, feedback amplifiers. Characteristics of operational amplifiers; applications of opamps: difference amplifier, adder, subtractor, integrator, differentiator, instrumentation amplifier, precision rectifier, active filters and other circuits. Oscillators, signal generators, voltage controlled oscillators and phase locked loop.

Section 6: Digital Electronics Combinational logic circuits, minimization of Boolean functions. IC families: TTL and CMOS. Arithmetic circuits, comparators, Schmitt trigger, multi-vibrators, sequential circuits, flip-flops, shift registers, timers and counters; sample-and-hold circuit, multiplexer, analog-to-digital (successive approximation, integrating, flash and sigma- delta) and digital-to-analog converters (weighted R, R-2R ladder and current steering logic). Characteristics of ADC and DAC (resolution, quantization, significant bits, conversion/settling time); basics of number systems, 8-bit microprocessor and microcontroller: applications, memory and input-output interfacing; basics of data acquisition systems.

Section 7: Measurements SI units, systematic and random errors in measurement, expression of uncertainty -accuracy and precision index, propagation of errors. PMMC, MI and dynamometer type instruments; dc potentiometer; bridges for measurement of R, L and C, Q-meter. Measurement of voltage, current and power in single and three phase circuits; ac and dc current probes; true rms meters, voltage and current scaling, instrument transformers, timer/counter, time, phase and frequency measurements, digital voltmeter, digital multimeter; oscilloscope, shielding and grounding.

Section 8: Sensors and Industrial Instrumentation Resistive-, capacitive-, inductive-, piezoelectric-, Hall effect sensors and associated signal conditioning circuits; transducers for industrial instrumentation: displacement (linear and angular), velocity, acceleration, force, torque, vibration, shock, pressure (including low pressure), flow (differential pressure, variable area, electromagnetic, ultrasonic, turbine and open channel flow meters) temperature (thermocouple, bolometer, RTD (3/4 wire), thermistor, pyrometer and semiconductor); liquid level, pH, conductivity and viscosity measurement.

Section 9: Communication and Optical Instrumentation Amplitude-and frequency modulation and demodulation; Shannon’s sampling theorem, pulse code modulation; frequency and time division multiplexing, amplitude- , phase-, frequency-, pulse shift keying for digital modulation; optical sources and detectors: LED, laser, photo-diode, light dependent resistor and their characteristics; interferometer: applications in metrology; basics of fiber optic sensing.

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COnTEnTS

BASICS OF CIrCUITS

1 BASIc cONcEpTS1.1 IntroductIon 3

1.2 BasIc ElEctrIc QuantItIEs or nEtwork VarIaBlEs 3

1.2.1 Charge 31.2.2 Current 31.2.3 Voltage 41.2.4 Power 41.2.5 Energy 5

1.3 cIrcuIt ElEmEnts 51.3.1 Active and Passive Elements 51.3.2 Bilateral and Unilateral Elements 51.3.3 Linear and Non-linear Elements 61.3.4 Lumped and Distributed Elements 6

1.4 sourcEs 61.4.1 Independent Sources 61.4.2 Dependent Sources 7

2 BASIc LAwS2.1 IntroductIon 23

2.2 ohm’s law 232.2.1 Sign Convention 242.2.2 Concept of Short Circuit and Open

Circuit 24

2.3 BranchEs, nodEs and loops 25

2.4 kIrchhoff’s law 262.4.1 Kirchhoff’s Current Law 262.4.2 Kirchoff’s Voltage Law 26

2.5 rEsIstancE connEctEd In sErIEs and parallEl 26

2.5.1 Series Resistances and Voltage Division 26

2.5.2 Parallel Resistances and Current Division 27

2.6 sourcEs In sErIEs or parallEl 272.6.1 Series Connection of Voltage

Sources 272.6.2 Parallel Connection of Identical

Voltage Sources 282.6.3 Parallel Connection of Current

Sources 282.6.4 Series Connection of Identical

Current Sources 282.6.5 Series - Parallel Connection of

Voltage and Current Sources 29

2.7 dElta- to- wyE transformatIon 29

3 NOdAL ANd LOOp ANALySIS3.1 IntroductIon 49

3.2 nodal analysIs 49

3.3 mEsh analysIs 50

3.4 comparIson BEtwEEn nodal analysIs and mEsh analysIs 51

4 cIRcUIT ThEOREMS4.1 IntroductIon 73

4.2 supErposItIon 73

4.3 sourcE transformatIon 73

4.4 thEVEnIn’s thEorEm 744.4.1 Thevenin’s Voltage 754.4.2 Thevenin’s Resistance 75

4.5 norton’s thEorEm 764.5.1 Norton’s Current 764.5.2 Norton’s Resistance 77

4.6 maxImum powEr transfEr thEorEm 78

4.7 rEcIprocIty thEorEm 78

4.8 suBstItutIon thEorEm 78

4.9 mIllman’s thEorEm 78

4.10 tEllEgEn’s thEorEm 79

5 INdUcTOR ANd cApAcITOR5.1 IntroductIon 105

5.2 capacItor 105

5.3 sErIEs and parallEl capacItors 1075.3.1 Capacitors in Series 1075.3.2 Capacitors in Parallel 108

5.4 Inductor 108

5.5 sErIEs and parallEl Inductors 1095.5.1 Inductors in Series 1095.5.2 Inductors in Parallel 110

5.6 dualIty 110

6 FIRST ORdER RL ANd Rc cIRcUITS6.1 IntroductIon 129

6.2 sourcE frEE or ZEro-Input rEsponsE 129

6.2.1 Source-Free RC Circuit 1296.2.2 Source-Free RL circuit 130

6.3 dc or stEp rEsponsE of fIrst ordEr cIrcuIt 131

6.3.1 Step Response of an RC Circuit 1316.3.2 Step Response of an RL Circuit 132

6.4 staBIlIty of fIrst ordEr cIrcuIts 133

7 SEcONd ORdER cIRcUITS7.1 IntroductIon 167

7.2 sourcE-frEE sErIEs RLC cIrcuIt 167

7.3 sourcE-frEE parallEl RLC cIrcuIt 169

7.4 stEp rEsponsE of sErIEs rlc cIrcuIt 170

7.5 stEp rEsponsE of parallEl RLC cIrcuIt 171

7.6 thE losslEss LC cIrcuIt 171

8 SINUSOIdAL STEAdy STATE ANALySIS8.1 IntroductIon 193

8.2 charactErIstIcs of sInusoId 193

8.3 phasors 194

8.4 ImpEdancE 1958.4.1 Impedance of Element R, L and C

1968.4.2 Impedance Combinations 196

8.5 phasor dIagrams 197

9 Ac pOwER ANALySIS9.1 IntroductIon 217

9.2 InstantanEous and aVEragE powEr 217

9.3 EffEctIVE or rms ValuE of a pErIodIc waVEform 218

9.4 complEx powEr 2199.4.1 Complex Power in Terms of Load

Impedance 2209.4.2 Power Factor 2209.4.3 Power Triangle 220

9.5 maxImum aVEragE powEr transfEr thEorEm 221

10 MAGNETIcALLy cOUpLEd cIRcUITS10.1 IntroductIon 245

10.2 mutual InductancE 245

10.3 sErIEs connEctIon of couplEd coIls 246

10.3.1 Series Adding Connection 24610.3.2 Series Opposing Connection 247

10.4 parallEl connEctIon of couplEd coIls 247

10.5 EnErgy storEd In a couplEd

cIrcuIt 247

10.6 lInEar transformEr 24810.6.1 T-equivalent of a Linear Transformer

24810.6.2 p-equivalent of a Linear Transformer

24910.6.3 Ideal Transformer 250

11 FREqUENcy RESpONSE11.1 IntroductIon 273

11.2 transfEr functIons 273

11.3 rEsonant cIrcuIt 27411.3.1 Series Resonance 27411.3.2 Parallel Resonance 276

11.4 passIVE fIltErs 27711.4.1 Low Pass Filter 27711.4.2 High Pass Filter 27811.4.3 Band Pass Filter 27911.4.4 Band Stop Filter 279

12 cIRcUIT ANALySIS USING LApLAcE TRANSFORM

12.1 IntroductIon 299

12.2 cIrcuIt ElEmEnts In thE s -domaIn 299

12.2.1 Resistor in the s -domain 29912.2.2 Inductor in the s -domain 30012.2.3 Capacitor in the s -domain 300

12.3 transfEr functIon 301

12.4 stEady statE rEsponsE 301

13 TwO pORT NETwORk13.1 IntroductIon 327

13.2 dIffErEnt typEs of two port paramEtErs 327

13.2.1 Impedance Parameters 32713.2.2 Admittance Parameters 32813.2.3 Hybrid Parameters 32813.2.4 Transmission Parameters 328

13.3 symmEtrIcal and rEcIprocal nEtwork 329

13.4 IntErconnEctIon of two-port nEtworks 330

13.4.1 Series Connection 33013.4.2 Parallel Connection 33113.4.3 Cascade Connection 331

AnAlOG ElECTrOnICS

1 dIOdE cIRcUITS1.1 IntroductIon 3

1.2 dIodE 31.2.1 Operating Modes of Diode 31.2.2 Current-Voltage Characteristics of a

Diode 4

1.3 load lInE analysIs 4

1.4 pIEcEwIsE lInEar modEl 5

1.5 small sIgnal modEl 51.5.1 AC and DC Equivalent Model 6

1.6 clIppEr and clampEr cIrcuIts 61.6.1 Clippers 61.6.2 Clampers 6

1.7 VoltagE multIplIEr cIrcuIt 71.7.1 Voltage Doubler 71.7.2 Voltage Tripler and Quadrupler 7

1.8 rEctIfIEr cIrcuIt 71.8.1 Half Wave Rectifiers 81.8.2 Full wave Rectifiers 9

1.9 ZEnEr dIodE 10

2 BJT BIASING2.1 IntroductIon 37

2.2 BasIc BIpolar junctIon transIstor 37

2.2.1 Operating Modes of BJT 382.2.2 Circuit Symbol and Conventions

for a BJT 38

2.3 Bjt confIguratIon 392.3.1 Common Base Configuration 392.3.2 Common Emitter configuration 412.3.3 Common-Collector Configuration

43

2.4 currEnt rElatIonshIps In Bjt 432.4.1 Relation between Current Gain 432.4.2 Relation between Leakage

Currents 44

2.5 load lInE analysIs 44

2.6 BIasIng 452.6.1 Fixed Bias Circuit 452.6.2 Emitter Stabilized Bias Circuit 462.6.3 Voltage Divider Bias 46

3 BJT AMpLIFIERS3.1 IntroductIon 73

3.2 ac load lInE analysIs 73

3.3 hyBrId EQuIValEnt modEl 74

3.4 small sIgnal paramEtEr 75

3.5 hyBrId-p modEl 77

3.6 analysIs of standard modEls 783.6.1 Common Emitter Fixed Bias

Configuration 783.6.2 Voltage Divider Bias 803.6.3 Common-Emitter Bias Configuration

81

4 FET BIASING4.1 IntroductIon 107

4.2 junctIon fIEld EffEct transIstor 107

4.3 mEtal-oxIdE sEmIconductor fIEld EffEct transIstor (mosfEt) 109

4.3.1 n-channel Enhancement Type MOSFET 109

4.3.2 p-channel Enhancement Type MOSFET 110

4.3.3 n-channel Depletion Type MOSFET 112

4.3.4 p-channel Depletion Type MOSFET 113

4.4 BIasIng confIguratIons for jfEt 113

4.4.1 Fixed Bias Configuration 1144.4.2 Self Bias Configuration 1144.4.3 Voltage Divider Biasing 114

4.5 BIasIng confIguratIons for EnhancEmEnt typE mosfEt cIrcuIts 115

4.5.1 Feedback Biasing Configuration 115

4.5.2 Voltage Divider Biasing Configuration 116

4.5.3 Enhancement Mode NMOS device with the Gate Connected to the Drain 116

5 FET AMpLIFIERS5.1 IntroductIon 139

5.2 small sIgnal analysIs of jfEt cIrcuIt 139

5.2.1 Transconductance 1395.2.2 Output Resistance 140

5.3 somE standard confIguratIons 140

5.3.1 JFET Fixed Bias Configuration 1405.3.2 JFET Self Bias Configuration with

bypassed Capacitor 1415.3.3 JFET Self Bias Configuration with

Unbypassed RS 1425.3.4 JFET Voltage Divider Configuration

1445.3.5 JFET Source Follower (Common

Drain) Configuration 1455.3.6 JFET Common Gate Configuration

146

5.4 small sIgnal analysIs of dEplEtIon typE mosfEt 147

5.5 small sIgnal analysIs of EnhancEmEnt typE mosfEt 147

6 OUTpUT STAGES ANd pOwER AMpLIFIERS


6.2 EmIttEr followEr as powEr amplIfIEr 167

6.3 push-pull stagE 168

6.4 classEs of amplIfIErs 1696.4.1 Class-A Operation 1716.4.2 Class-B Operation 1726.4.3 Class-AB Output Stage 173

6.5 amplIfIEr dIstortIon 174

7 Op AMp chARAcTERISTIcS ANd BASIc cIRcUITS


7.2 opEratIonal amplIfIEr 195

7.3 IdEal op-amp cIrcuIt 196

7.4 practIcal op-amp cIrcuIts 1977.4.1 Inverting Amplifier 1977.4.2 Non-inverting Amplifier 1977.4.3 Unity Follower 1987.4.4 Summing Amplifier 1987.4.5 Amplifier with a T-network 198

7.5 practIcal op-amp cIrcuIts wIth fInItE gaIn 199

7.5.1 Unity Follower 1997.5.2 Inverting Amplifier 1997.5.3 Non-inverting Amplifier 199

7.6 slEw ratE 200

7.7 dIffErEntIal and common-modE opEratIon 200

7.7.1 Differential Inputs 2007.7.2 Common Inputs 2007.7.3 Output voltage 2017.7.4 Common Mode Rejection Ratio 201

7.8 dc offsEt paramEtEr 2017.8.1 Output Offset Voltage due to

Input Offset Voltage 2017.8.2 Output Offset Voltage due to

Input Offset Current 202

8 Op AMp AppLIcATIONS8.1 IntroductIon 223

8.2 InVErtIng amplIfIEr 223

8.3 non-InVErtIng amplIfIEr 224

8.4 multIplE-stagE gaIns 224

8.5 VoltagE suBtractIon 225

8.6 currEnt to VoltagE conVErtEr 225

8.7 VoltagE to currEnt conVErtEr 226

8.8 dIffErEncE amplIfIEr 227

8.9 InstrumEntatIon amplIfIEr 228

8.10 IntEgrator 229

8.11 dIffErEntIator 230

8.12 logarIthmIc amplIfIEr 230

8.13 ExponEntIal amplIfIEr 231

8.14 sQuarE-root amplIfIEr 231

8.15 comparator 232

8.16 schmItt trIggEr 233

8.17 non InVErtIng schmItt trIggEr cIrcuIt 234

8.18 prEcIsIon rEctIfIEr 235

8.19 functIon gEnErator 236

9 AcTIvE FILTERS9.1 IntroductIon 263

9.2 actIVE fIltEr 2639.2.1 Low Pass Filter 2639.2.2 High Pass Filter 2659.2.3 Band pass filter 266

9.3 thE fIltEr transfEr functIon 266

9.4 ButtErworth fIltErs 270

9.5 thE chEByshEV fIltEr 270

10 FEEdBAck AMpLIFIER ANd OScILLATOR


10.2 fEEdBack 29310.2.1 Negative Feedback 29310.2.2 Positive Feedback 294

10.3 thE four BasIc fEEdBack topologIEs 294

10.3.1 Voltage Amplifier 29410.3.2 Current Amplifier 29410.3.3 Transconductance Amplifier 29510.3.4 Transresistance Amplifier 296

10.4 analysIs of fEEdBack amplIfIEr 296

10.5 oscIllators 298

10.6 op-amp rc oscIllator cIrcuIts 29910.6.1 Wein Bridge Oscillator 29910.6.2 Phase Shift Oscillator 299

10.7 lc oscIllator cIrcuIt 30010.7.1 Colpitts Oscillator 30010.7.2 Hartley oscillator 301

10.8 thE 555 cIrcuIt 30110.8.1 Monostable Multivibrator 30110.8.2 Astable Multivibrator 302

DIGITAl ElECTrOnICS

1 NUMBER SySTEM ANd cOdES1.1 IntroductIon 3

1.2 numBEr systEms 31.2.1 Decimal Number System 41.2.2 Binary Number System 41.2.3 Octal Number System 41.2.4 Hexadecimal Number System

5

1.3 numBEr systEm conVErsIon 51.3.1 Decimal-to-Binary Conversion 61.3.2 Decimal-to-Octal Conversion 61.3.3 Decimal-to-Hexadecimal

Conversion 71.3.4 Octal-to-Binary conversion 71.3.5 Binary-to-Octal Conversion 8

1.3.6 Hexadecimal-to-Binary Conversion 81.3.7 Binary-to-Hexadecimal Conversion 81.3.8 Hexadecimal-to-Octal and Octal-

to-Hexadecimal Conversion 9

1.4 BasIc BInary arIthmEtIc 9

1.5 complEmEnts of numBErs 10

1.6 numBEr rEprEsEntatIon In BInary 111.6.1 Sign-Magnitude Representation 111.6.2 1’s Complement Representation 111.6.3 2’s Complement Representation 11

1.7 complEmEnt BInary arIthmEtIc 121.7.1 Addition Using 1’s Complement 121.7.2 Subtraction Using 1’s Complement

131.7.3 Addition Using 2’s Complement 131.7.4 Subtraction using 2’s Complement

14

1.8 BInary codEs 141.8.1 Weighted and Non-Weighted

Codes 141.8.2 Numeric and Alphanumeric Codes 151.8.3 Error Detecting and Correcting

Codes 151.8.4 Self-complementary Codes 151.8.5 Unit Distance Codes (Cyclic Codes)

151.8.6 Sequential Codes 151.8.7 Reflective Code s 16

1.9 BInary codEd dEcImal ( 8421 ) codE 16

1.10 thE ExcEss-3 codE 16

1.11 gray codE 17

2 BOOLEAN ALGEBRA ANd LOGIc SIMpLIFIcATION

2.1 IntroductIon 33

2.2 BasIc BoolEan opEratIons 33

2.3 thEorEms of BoolEan algEBra 34

2.4 logIc gatEs 362.4.1 Logic Levels 362.4.2 Types of Logic Gates 37

3 ThE k-MAp3.1 IntroductIon 59

3.2 rEprEsEntatIon for BoolEan functIons 59

3.2.1 Standard or Canonical Sum-of-Products (SOP) Form 59

3.2.2 Standard or Canonical Product-of-Sums (POS) Form 61

3.3 karnaugh map (k-map) 63

3.4 groupIng of cElls for sImplIfIcatIon 64

3.4.1 Grouping of Two adjacent Cells (Pair) 64

3.4.2 Grouping of Four Adjacent Cells (Quad) 65

3.4.3 Grouping of Eight Adjacent Cells (Octet) 65

3.4.4 Redundant Group 66

3.5 don’t carE condItIons 673.5.1 K-map Simplification with Don’t

Care Conditions 683.5.2 Conversion of Standard SOP to

Standard POS with Don’t Care Conditions 68

4 cOMBINATIONAL cIRcUITS4.1 IntroductIon 83

4.2 addErs and suBtractors 834.2.1 Half-Adder 834.2.2 Full-Adder 844.2.3 Half-Subtractor 854.2.4 Full-Subtractor 85

4.3 comparator 864.3.1 1-bit Magnitude Comparator 864.3.2 2-bit Magnitude Comparator 87

4.4 multIplExEr 884.4.1 2-to-1 Multiplexer 884.4.2 4-to-1 Multiplexer 89

4.5 dEmultIplExEr 904.5.1 1-to-2 Demultiplexer 904.5.2 1-to-8 Demultiplexer 90

4.6 dEcodEr 91

4.7 EncodErs 924.7.1 Decimal-to-BCD Encoder 934.7.2 Priority Encoders 94

4.8 parIty gEnErator 954.8.1 Even Parity Generator 954.8.2 Odd Parity Generator 96

5 SEqUENTIAL cIRcUITS5.1 IntroductIon 113

5.2 typEs of sEQuEntIal logIc cIrcuIts 113

5.3 latchEs and flIp-flops 114

5.4 s-r latch 115

5.5 flIp-flops 1165.5.1 S-R Flip-Flop 1165.5.2 D-Flip Flop 1175.5.3 J-K Flip-Flop 1185.5.4 T Flip-Flop 119

5.6 trIggErIng of flIp-flops 1195.6.1 Level Triggering 1205.6.2 Edge Triggering 120

5.7 rEgIstEr 1215.7.1 Buffer Register 1215.7.2 Shift Register 122

5.8 countEr 1235.8.1 Asynchronous and Synchronous

Counter 1245.8.2 Up-Counter and Down-Counter 124

5.9 shIft rEgIstEr countErs 1265.9.1 Ring Counter 1265.9.2 Johnson Counter 128

6 LOGIc FAMILIES6.1 IntroductIon 145

6.2 classIfIcatIon of dIgItal logIc famIly 145

6.3 charactErIstIc paramEtErs of dIgItal logIc famIly 146

6.4 rEsIstor-transIstor logIc 149

6.5 dIrEct couplEd transIstor logIc 150

6.6 dIodE transIstor logIc 150

6.7 transIstor-transIstor logIc 151

6.8 EmIttEr couplEd logIc 152

6.9 IntEgratEd InjEctIon logIc 1546.9.1 IIL Inverter 1546.9.2 IIL NAND Gate 1546.9.3 IIL NOR Gate 155

6.10 mEtal oxIdE sEmIconductor logIc 156

6.10.1 NMOS Inverter 1566.10.2 NMOS NAND Gate 1576.10.3 NMOS NOR Gate 157

6.11 complEmEntary mEtal oxIdE sEmIconductor (cmos) logIc 158

6.11.1 CMOS Inverter 1586.11.2 CMOS NAND Gate 1596.11.3 CMOS NOR Gate 159

7 INTERFAcING TO ANALOG7.1 IntroductIon 173

7.2 dIgItal to analog conVErtEr 173

7.3 dac cIrcuIts 1747.3.1 R- 2R Ladder Type DAC 1747.3.2 Weighted Resistor Type DAC 174

7.4 analog-to-dIgItal conVErtEr 1757.4.1 Sample-and-hold circuit 1757.4.2 Quantization and Encoding 1757.4.3 Parameters of ADC 176

7.5 adc cIrcuIts 1767.5.1 Flash Type A/D Converter 1777.5.2 Counting A/D Converter 177

7.5.3 Dual Slope Type A/D Converter 1797.5.4 Successive Approximation Type ADC

179

7.6 astaBlE multIVIBrator 180

7.7 monostaBlE multIVIBrator 181

7.8 schmItt trIggEr 183

8 MIcROpROcESSOR ANd MIcROcONTROLLER


8.2 mIcroprocEssor archItEcturE 2038.2.1 Microprocessor operation 204

8.3 pIn dIagram of 8085 mIcroprocEssor 205

8.3.1 Address and Data Bus 2058.3.2 Control and Status Signals 2068.3.3 Power Supply and Clock

Frequency 2068.3.4 Interrupts and Other Operations 2068.3.5 Serial I/O Ports 207

8.4 InstructIon sEt of 8085 mIcroprocEssor 207

8.4.1 Data Transfer Instructions 2078.4.2 Arithmetic Instructions 2098.4.3 Branching Instructions 2118.4.4 Logic Instructions 2148.4.5 Control Instructions 216

8.5 mIcrocontrollEr 218

8.6 archItEcturE of 8051 mIcrocontrollEr 218

8.7 InstructIon sEt of 8051 mIcrocontrollEr 220

8.7.1 Addressing mode 2208.7.2 Data Transfer Instructions 2218.7.3 Arithmetic Instructions 2228.7.4 Logical Instructions 223

��

CHAPTEr 1BOOlEAn AlGEBrA AnD lOGIC SIMMPlIFICATIOn

1.1 InTrODUCTIOn

This chapter, concerned with the basic study of Boolean algebra and simplification theory, includes the following topics: • Basic Boolean operations: addition, multiplication, not operation

• Various theorems of Boolean algebra

• Meaning of positive and negative logic

• Various types of logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR gates.

• Universal logic gates

1.2 BASIC BOOlEAn OPErATIOnS

Boolean algebra uses only three basic operations, namely1. OR operation: The OR operation in Boolean algebra is similar

to addition in ordinary algebra i.e., OR means logical addition operation. The logical OR operation on A and B is denoted by

Y A B= + , where ‘+’ is the OR operator

2. AND operation: The AND operation in Boolean algebra is similar to multiplication in ordinary algebra i.e, AND performs logical multiplication operation. The logical AND operation on A and B is denoted by

Y A B:= , where : is the AND operator.

3. NOT operation: NOT is the simplest of the three basic operations of Boolean algebra. It is also known as inversion and complement. The NOT operation is indicated by a bar ‘-’ over the variable. If A is a variable, then NOT of A is expressed as A .

Boolean Algebra and Logic Simmplification Chap 1

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Table� 2.1: Truth Table for OR, AND, and NOT Operation

OR Operation AND Operation NOT Operation

Input Output Input Output Input Output

A B Y A B= + A B Y AB= A Y A=

0 0 0 0 0 0 0 1

0 1 1 0 1 0 1 0

1 0 1 1 0 0

1 1 1 1 1 1

1.3 THEOrEMS OF BOOlEAn AlGEBrA

The theorems of Boolean algebra can be used to simplify many complex Boolean expression and also to transform the given expression into a more useful and meaningful equivalent expression. These theorems are discussed as below.

Complementation Laws

The term complement implies to invert, i.e. to change 1’s to 0’s and 0’s to 1’s. The five laws of complementation are as follows:1. The complement of 0 is 1, i.e. 0 1=

2. The complement of 1 is 0, i.e. 1 0=

3. If A 0= , then A 1=

4. If A 1= , then A 0=

5. The double complementation does not change the function, i.e. A A=

AND Laws

The four AND laws are as follows:1. Null Law: A 0 0: =

2. Identity Law: A A1: =

3. A A A: =

4. A A 0: =

OR Laws

The four OR laws are as follows:1. Null Law: 0A A+ =

2. Identity Law: 1A 1+ =

3. A A A+ =

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Chap 1 Boolean Algebra and Logic Simmplification


GATE STUDY PACKAGE InSTrUMEnTATIOn EnGInEErInG SAlIEnT FEATUrES* Brief Theory * Methodology * Important Points *

*MCQ * Numerical Answer Type Questions * Memory Based Questions * Detailed Solution for Each and Every Problem*

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4. A A 1+ =

Commutative Laws

Commutative law states that the order of the variable in OR and AND operations is not important. The two commutative laws are A B+ B A= +

A B: B A:=

Associative Laws

Associative law states that the grouping of variables in AND or OR expression does not affect the result. There are two associative laws. A B C+ +_ i A B C= + +_ i A B C: :_ i A B C: := _ i

Distributive Law

The distributive laws allow factoring or multiplying out of expressions. There are two distributive laws A B C+_ i AB AC= +

A BC+ A B A C= + +_ _i iRedundant Literal Rule

This law states that ORing of a variable with the AND of the complement of that variable with another variable, is equal to ORing of the two variables, i.e. A AB+ A B= +Another theorem based on this law is A A B+_ i AB=

Idempotent Law

Idempotence means the same value. There are two idempotent laws A A A A: : : :g A=

A A A Ag+ + + + A=

Absorption Law

There are two absorption laws A A B:+ A=

A A B: +_ i A=

Consensus Theorem

There are two consensus theorems, AB AC BC+ + AB AC= +

A B A C B C+ + +_ _ _i i i A B A C= + +_ _i i








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Transposition Theorem

There are two transposition theorems, the first is given as AB AC+ A C A B= + +_ _i i A B A C:+ +_ _i i A C A B: := +

De Morgan’s Theorem

De Morgan’s theorem gives two of the most powerful laws in Boolean algebra. These theorems are very useful in simplification of Boolean expressions, A B+ A B=

AB A B= +

Shannon’s Expansion Theorem

According to this theorem, any switching expression can be decomposed with respect to a variable A into two parts, one containing A and the other containing A . This concept is useful in decomposing complex system into an interconnection of smaller components. , , , ....f A B C_ i , , ... , , , ...A f B C A f B C1 0: := +_ _i i , , , ...f A B C_ i , , , ... , , , ...A f B C A f B C0 1:= + +_ _i i8 8B B

1.4 lOGIC GATES

Logic gates are the fundamental building blocks of digital systems. Logic gates are electronic circuits that perform the most elementary Boolean operations. Before understanding the logic gates, we must understand the meaning of positive and negative logic.

1.4.1 Logic Levels

There are two different ways to assign a signal value to logic level such as positive logic and negative logic.1. Positive Logic: If higher of the two voltage levels represents a

logic ‘1’ and the lower of the two levels represents a logic ‘0’, then the logic system is referred to as a positive logic system. Figure 2.1 shows the positive logic system.

Figure 2.1: Positive Logic System

2. Negative Logic: If the higher of the two voltage levels represents a logic ‘0’ and the lower of the two levels represents a logic ‘1’, then








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the logic system is referred to as a negative logic system. Figure 2.2 shows the representation of negative logic systems.

Figure 2.2: Negative Logic System

3. Mixed Logic: In mixed logic, the assignment of logical values to voltage values is not fixed, and it can be decided by the logic designers. Mixed logic provides a simplified mechanism for the analysis and design of digital circuits. The proper use of mixed logic notation provides logic expressions and logic diagrams that are analogue to each other. Also, a mixed logic diagram provides clear information as to the operation of a circuit.

1.4.2 Types of Logic Gates

Logic gates are electronic circuits with a number of inputs and one output. In the following sections, different types of logic gates are described.

AND Gate

An AND gate is a logic circuit with two or more inputs and one output that performs ANDing operation. The output of an AND gate is HIGH only when all of its inputs are in the HIGH state. In all other cases, the output is LOW. For a positive logic systems, it means that the output of the AND gate is a logic ‘1’ only when all of its inputs are in logic ‘1’ state. In all other cases, the output is logic ‘0’. The logic symbol of a two-input AND gate is shown in Figure 2.3.

Figure 2.3: Logic Symbol of Two-input AND gate

OR Gate

An OR gate is a logic circuit with two or more inputs and one output that performs ORing operation. The output of an OR gate is LOW only when all of its inputs are LOW. For all other possible input combinations, the output is HIGH. For a positive logic system, the output of an OR gate is a logic ‘0’ only when all of its inputs are at logic ‘0’. For all other possible input combinations, the output is a logic








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‘1’. The logic symbol of a two-input OR gate is shown in Figure 2.4.

Figure 2.4: Logic Symbol of Two-input OR gate

NOT Gate

A NOT gate, also called an inverter is a one-input, one-output logic circuit whose output is always the complement of the input. That is, a LOW input produces a HIGH output, and vice versa. It means that for a positive logic system, a logic ‘0’ at the input produces a logic ‘1’ at the output, while a logic ‘1’ at the input produces a logic ‘0’ output. It is also known as a complementing circuit or an inverting circuit. The logic symbol of an inverter is shown in Figure 2.5.

Figure 2.5: Symbol for a NOT gate

NAND Gate

The term NAND implies NOT-AND. A NAND gate is equivalent to AND gate followed by a NOT gate. The standard logic symbol for a 2-input NAND gate is shown in Figure 2.6. This symbol is same as AND gate symbol except for a small circle (bubble) on its output. This circle represents the NOT function.

Figure 2.6: Logic symbol of NAND gate

The truth Table 2.2 of a NAND gate is obtained from the truth Table of an AND gate by complementing the output entries.

Table� 2.2: Truth Table of a 2-input NAND Gate

Input Output

A B Y AB=

0 0 1

0 1 1

1 0 1

1 1 0








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NOR Gate

The term NOR implies NOT-OR. A NOR gate is equivalent to OR gate followed by a NOT gate. The standard logic symbol for a 2-input NOR gate is shown in Figure 2.7. This symbol is same as OR gate symbol except for a small circle (bubble) on its output. This circle represents the NOT function.

Figure 2.7: Logic symbol of NOR gate

The truth Table 2.3 of a NOR gate is obtained from the truth Table of an OR gate by complementing the output entries.

Table� 2.3: Truth table of a 2-input NOR gate

Input Output

A B Y A B= +

0 0 1

0 1 0

1 0 0

1 1 0

Exclusive-OR (XOR) Gate

The Exclusive-OR gate, commonly known as EX-OR gate, is a two-input, one-output gate. The logic symbol for the Ex-OR gate is shown in Figure 2.8.

Figure 2.8: Symbol for 2-input Ex-OR Gate

The truth table for a two-input EX-OR operation is given in Table 2.4. From the truth table it can be stated that, the output of an EX-OR gate is a logic ‘1’ when the two inputs are at different logic and a logic ‘0’ when the two inputs are at the same logic.








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Table� 2.4: Truth Table of a 2-input Ex-OR Gate

Input Output

A B Y A B5=

0 0 0

0 1 1

1 0 1

1 1 0

Exclusive-NOR (XNOR) Gate

The exclusive-NOR gate, commonly known as Ex-NOR, is an Ex-OR gate, followed by an inverter. It has two inputs and one output. The logic symbol for the Ex-NOR gate is shown in Figure 2.9.

Figure 2.9: Symbol for 2-input Ex-NOR Gate

The truth table for the two-input Ex-NOR operation is given in Table 2.12. From the truth table it can be stated that, the output of a two-input EX-NOR gate is a logic ‘1’ when the inputs are same and a logic ‘0’ when they are different.

Table� 2.12: Truth Table of a 2-input Ex-NOR Gate

Input Output

A B Y A B9=

0 0 1

0 1 0

1 0 0

1 1 1

POInT TO rEMEMBEr

NAND and NOR gates are known as universal gates because any of these two gates is capable of implementing all other gate functions.

��








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EEErCISE�

MCQ 1.1 In the following circuit, the output X is

(A) MNQ (B) ( )N Q M+

(C) ( )M Q N+ (D) ( )Q M N+

MCQ 1.2 In the following circuit, the output Z is

(A) ( )AB C D E+ + (B) ( )AB C D E+

(C) AB CD E+ + (D) AB CDE+

nAT 1.3 The number of different sets of input conditions that produces a high output from a five-input OR gate is

��

MCQ 1.4 Which of the following gate corresponds to the action of series switches for the input ?(A) AND

(B) NAND

(C) OR

(D) NOR








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MCQ 1.5 In the following circuit, the output Z is

(A) A B C+ + (B) ABC

(C) AB BC AC+ + (D) Above all

MCQ 1.6 In the following circuit the output Y is

(A) AB AB C+ +

(B) AB AB C+ +

(C) AB AB C+ +

(D) AB AB C+ +

nAT 1.7 In the following circuit the output Z is

��

MCQ 1.8 If a three-input OR gate has eight input possibilities, how many of those possibilities will result in a HIGH output?(A) 1

(B) 2

(C) 7

(D) 8








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MCQ 1.9 In the following circuit the output Z is

(A) ABC (B) ( )AB C B+

(C) ABC (D) ( )AB C B+

MCQ 1.10 A BC+ is equivalent to(A) ( )( )A B A C+ + (B) A B+

(C) A C+ (D) ( )( )A B A C+ +

MCQ 1.11 If a three-input NAND gate has eight input possibilities, how many of those possibilities will result in a HIGH output?(A) 1 (B) 2

(C) 7 (D) 8

MCQ 1.12 The Boolean expression for the truth table shown is

A B C f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

(A) ( )( )B A C A C+ + (B) ( )( )B A C A C+ +

(C) ( )( )B A C A C+ + (D) ( )( )B A C A C+ +

MCQ 1.13 The reduced form of the Boolean expression of ( ) ( )Y AB AB:= is(A) A B+ (B) A B+

(C) AB AB+ (D) AB AB+








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MCQ 1.14 If XY XY Z+ = then XZ XZ+ is equal to(A) Y (B) Y

(C) 0 (D) 1

MCQ 1.15 Symbol in figure given below is IEEE symbol for

(A) AND (B) OR

(C) NAND (D) NOR

MCQ 1.16 The output of logic circuit is HIGH whenever A and B are both HIGH as long as C and D are either both LOW or both HIGH. The logic circuit is

MCQ 1.17 The operation A A: =(A) A 2 (B) A2

(C) 1 (D) A

MCQ 1.18 In the network shown below F can be written as








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(A) ... ...X X X X X X X X X Xn n n0 1 3 5 2 4 5 1 1+ +− −

(B) ... ...X X X X X X X X X Xn n n0 1 3 5 2 3 4 1+ + −

(C) ... ... ...X X X X X X X X X X Xn n n n0 1 3 5 2 3 5 1+ + + −

(D) ... ... ...X X X X X X X X X X X Xn n n n n0 1 3 5 1 2 3 5 1 2+ + + +− − −

MCQ 1.19 The gate G1 and G2 in figure shown below have propagation delays of 10 ns and 20 ns respectively.

If the input Vi makes an abrupt change from logic 0 to 1 at t t0= then the output waveform Vo is

[t t 101 0= + ns, t t 102 1= + ns, t t 103 2= + ns]

MCQ 1.20 Which of the following Boolean expressions correctly represents the relation between , ,P Q R and M1

(A) ( )XM P Q ROR OR1=

(B) ( )XM P Q RAND OR1=

(C) ( )XM P Q RNOR OR1=

(D) ( )X XM P Q ROR OR1=








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MCQ 1.21 The gate shown in Fig. is an alternative symbol of

(A) AND gate (B) OR gate

(C) NAND gate (D) NOR gate

MCQ 1.22 The logic circuit shown in the given figure can be minimized to

MCQ 1.23 Which one of the following logical operations is performed by the digital circuit shown below ?

(A) NOR (B) NAND

(C) Ex-OR (D) OR

MCQ 1.24 The logic operations of two combinational circuits given in Figure - I and Figure - II are








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(A) Entirely different (B) Identical

(C) Complementary (D) Dual

MCQ 1.25 In the following circuit, the motor will turn on when DRIVE 1=

Which of the following give correct values of , , , , , , ,A A A A A A A0 1 2 3 4 5 6 ,A A7 8

, and A9 in order to move motor ?(A) A A A A A A A A A A 10 1 2 3 4 5 6 7 8 9= = = = = = = = = =

(B) ; ;A A A A A A A A A A1 00 1 2 3 4 5 6 9 7 8= = = = = = = = = =

(C) ;A A A A A A A A A A1 00 1 2 3 4 5 6 7 8 9= = = = = = = = = =

(D) ;A A A A A A A A A A1 00 1 2 3 4 5 6 7 8 9= = = = = = = = = =

MCQ 1.26 The output (X ) waveform for the combination circuit shown below for the inputs at A and B (waveform shown in the figure) will be








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SOlUTIOnS�

SOl 1.1 Correct option is (D).From the Boolean properties, we know that

So, its equivalent logic will be

i.e. AND-Invert = Invert-ORApplying the property, we have the modified logic circuit as

So, the output X is X MNQ MNQ MNQ= + +

MQ N N MNQ= + +_ i MQ MNQ= + Q M MN= +_ i Q M N= +_ i

SOl 1.2 Correct option is (A).We convert the AND-Invert logic to equivalent Invert-OR logic as








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or

So, the output Z is given as Z AB E C D= + +_ i

SOl 1.3 Correct answer is 31.We know that, if any one input of the OR gate becomes high logic (1), OR gate gives the high logic (1) output. The output is High only for the case when all the inputs are at Low logic (0). Now, for 5-inputs, we have Total number of input conditions 2 325= =Out of the 32 conditions, all inputs are zero (0) for only one condition. i.e. for only one condition the output is low.Hence, 31 input conditions produce the high output from a five-input OR gate.

SOl 1.4 Correct option is (A).

SOl 1.5 Correct option is (D).From the given logic diagram, expression of the output can be written as Z A AB BC C= + + +_ i A A B B C C= + + + + +

A B C

ABC

= + +

=4

From the above logic function, we can observe that options (A) and (B) are matched. Now, we check the expression given in option (C).








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Z AB BC AC= + +

A B B C A C= + + + + + A B C= + +Hence, all the options are same, and equal to the output Z of the given logic circuit.

SOl 1.6 Correct option is (B).Expression of the output for the circuit is given by

Y A B C5 := _ i AB AB C:= +_ i AB AB C= + +_ i {Using De Morgan’s theorem}

AB A B C= + +_ i {A B A B9 5= or A B A B5 9= }

A B AB C= + +

SOl 1.7 Correct answer is 1.From the given circuit, we can observe that input to last XNOR gate is same. So, the XNOR output is given by (Let input is X ) Z X X X X X X 1: := + = + =i.e. the output will be High (logic 1), irrespective of the inputs A and B .

SOl 1.8 Correct option is (C).OR gate output Y A B C= + +If any one input is HIGH, output will be HIGH. Output will be LOW only when all three inputs become LOW.Out of 8 input possibilities, seven cases have one or more inputs high results in HIGH.

SOl 1.9 Correct option is (A).Expression of the output Z for the circuit is given by Z A B B C: := +_ _i i A B B ABC: := +

ABC= {B B 0: = }

SOl 1.10 Correct option is (A).Given expression is A BC+ . Using distributive law, we have A BC+ A B A C= + +_ _i iThis law states that ANDing of several variables and ORing the result








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with a single variable is equivalent to ORing that single variable with each of the several variables and then ANDing the sums. It can be verified from the table below.

A B C A B+ A C+ A B A C+ +_ _i i A BC+

0 0 0 0 0 0 0

0 0 1 0 1 0 0

0 1 0 1 0 0 0

0 1 1 1 1 1 1

1 0 0 1 1 1 1

1 0 1 1 1 1 1

1 1 0 1 1 1 1

1 1 1 1 1 1 1

SOl 1.11 Correct option is (C)

SOl 1.12 Correct option is (A).From truth table, the expression of the function f is given by f ABC ABC= +

B AC AC= +_ i B A C A C= + +_ _i i

SOl 1.13 Correct option is (D).Given logic expression is Y AB AB:= _ _i iOn simplification by using Boolean algebra, we get Y AB AB:= _ _i i (Using De-Morgan’s theorem) A B A B= + +_ _i i AA A B AB BB= + + +_ i A B AB= +

SOl 1.14 Correct option is (B).Given that Z XY XY= +So, we simplify the given function as XZ XZ+ X XY XY X XY XY= + + +_ _i i X XY X Y XY= + +_ i XY XY= + Y X X= +_ i Y=








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SOl 1.15 Correct option is (B).

SOl 1.16 Correct option is (A).We check the circuits in given option for the required condition. The output of the logic circuit will be high only when both inputs of last AND are high. Now, we have the two conditions:1. Given that A and B are both High. For A and B as logic High,

one input of last AND gate is high for the circuits given in options (A) and (B).

2. Given that C and D are either both LOW or both HIGH. For the circuit given in option (A), if C and D inputs are either both high or both low, i.e. C D= applied to XNOR gate then

C D9 1= for C D= i.e. another input of last AND gate will be High.

Thus, the circuit given in option (A) is HIGH whenever A and B are both HIGH as long as C and D are either both LOW or both HIGH.

SOl 1.17 Correct option is (D).

SOl 1.18 Correct option is (C).For the given network, we obtain Output of gate 1 X X0 1=

Output of gate 2 X X X0 1 2= +

Output of gate 3 X X X X0 1 2 3= +_ i X X X X X0 1 3 2 3= +

Similarly, we may deduce Output of gate 4 X X X X X X0 1 3 2 3 4= + +

Output of gate 5 X X X X X X X0 1 3 2 3 4 5= + +_ i X X X X X X X X X0 1 3 5 2 3 5 4 5= + +Hence, the output of gate n would be

......... ......... .......... ........F X X X X X X X X X X X X X X Xn n n n n0 1 3 5 2 3 5 4 5 7 1= + + + + −

SOl 1.19 Correct option is (C).Given that G1 has delay of 10 ns and G2 has delay of 20 ns. Let output of G1 is X . So, we get the output waveform for the given circuit as shown below.








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www.nodia.co.inSOl 1.20 Correct option is (D).

From the circuit diagram, we have X PQ=

Y P Q= +

and Z X Y PQ P Q:= = +_ _i i P Q P Q= + +_ _i i PQ PQ= + P Q5=

and M1 Z R5=

Hence, M1 P Q R5 5= _ i M1 XOR XORP Q R= _ i

SOl 1.21 Correct option is (C). Y A B A B$= + = = NAND gate logic

SOl 1.22 Correct option is (D).Given logic circuit is

So, the output Z is given by Z X X Y= + + X X Y X X Y: := + = +_ i X XY= + X Y1= +_ i X= X=








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In option (D), the circuit provides the output X as shown below.

Hence, the circuit given in option (D) is minimized form of the logic circuit.

SOl 1.23 Correct option is (C).We redraw the given digital circuit as

Output Y is given by Y AB AB= + XORA B A B5= = _ i

SOl 1.24 Correct option is (D).In order to convert the given circuit using only NAND gate, we apply bubbles at the input terminal of each gates as shown below.

From the Boolean algebra, we have

and

Therefore, by using the above conversion, we get the logic circuit with NAND gates as








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www.nodia.co.inSOl 1.25 Correct option is (B).

We redraw the given logic circuit as

DRIVE is active-HIGH, and it will go high only when X Y 0= =X will be LOW only when either andA A8 9 is HIGH.Y will be LOW only when andW A0 07= =W will be LOW only when A0 through A6 are all HIGH.Putting this all together, we have the condition for DRIVE to be high as A0 A A A A A A 11 2 3 4 5 6= = = = = = =

A7 0=

and either A8 or A9 or both are 1

SOl 1.26 Correct option is (B).For given logic circuit, expression for output X is

X A B B:= +_ i A B B= + +_ i A B B= + +^ h A B= +Output waveform for the given input waveforms is








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