digital circuits for gate exam
TRANSCRIPT
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Test Paper-1
Digital Electronics
Source Book:GATE Multiple Choice Questions ECE
Author: RK Kanodia Edition:6th
ISBN: 9788192276205
Publisher :Nodia and Company
Visit us at:www.nodia.co.in
Q. No. 1 - 10 Carry One Mark Each
MCQ 1.1 11001, 1001 and 11001 correspond to the 2s complement representation of the
following set of numbers
(A) 25, 9 and 57 respectively
(B) 6, 6 and 6 respectively
(C) 7, 7 and 7 respectively
(D) 25, 9 and 57 respectively
SOL 1.1 All are 2s complement of 7
11001 & 00110
1
00111 710
+
=
1001&
01101
0111 710
+
=
111001 & 000110
1
000111 710
+
=
Hence (C) is correct option.
MCQ 1.2 To implement Y ABCD = using only two-input NAND gates, minimum number of
requirement of(A) 3 (B) 4
(C) 5 (D) 6
SOL 1.2 The circuit is as follows
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Hence (D) is correct option.
MCQ 1.3 A four-variable switching function has minterms m6 and m9. If the literals in these
minterms are complemented, the corresponding minterm numbers are
(A) m3 and m0 (B) m9 and m6
(C) m2 and m0 (D) m6 and m9
SOL 1.3 Hence (B) is correct option.
m6 ABCD= ,
m9 ABCD=
After complementing literal
6ml
ABC D m 9= = , 9ml ABCD m 6= =
MCQ 1.4 The network shown below implements
(A) NOR gate (B) NAND gate
(C) XOR gate (D) XNOR gate
SOL 1.4 Hence (B) is correct option.
f1 C D CB CB = + + , S F1=
f f f A CB CBA CB A1 1= + = + = +
C B A ABC = + + =
MCQ 1.5 Consider a circuit shown in figure. The circuit functions as
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(A) D-flip-flop (B) T-flip-flop
(C) Output remains stable at '1' (D) Output remains stable at '0'
SOL 1.5 From the combinational logic
Let D is input, Qn is present state, Qn 1+ is next state, then
R ,D Q S D Q 5 5= =
Characteristic equation of R-S flip-flop is given by
Qn 1+ S RQn= +
So,Qn 1+ ( ) ( )D Q D Q Q n n n5= + +
( ) ( )D Q D Q Q n n n5 5
= + ( )(1 ) ( )D Q Q D Q n n n5 5 5= =
DQ DQ n n= +
For 0D= , Q Qn n1 =+ 1D= , Q Qn n1 =+So, the circuit function as a T-flip flop.
Hence (B) is correct option.
MCQ 1.6 To count from 0 to 1024 the number of required flip-flop is
(A) 10 (B) 11
(C) 12 (D) 13
SOL 1.6 10 flip-flop will count from 0 to 1023. Hence 11 flip-flop are required to count from
0 to 1024.
Hence (B) is correct option.
MCQ 1.7 The circuit shown below is a
(A) NAND (B) NOR
(C) AND (D) OR
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SOL 1.7 If either one or both the inputs are (0) 0V = V the corresponding FET will be
OFF, the voltage across the load FET will be 0 V, hence the output is VDD. If both
inputs are (1)V VDD= , both M1 and M2 are ON and the output is (0) 0V = V. It
satisfy NAND gate.
Hence (A) is correct option.
MCQ 1.8 For the given logic families, correct order of their increasing noise margin is
(A) RTL, ECL, MOS, DTL (B) RTL, ECL, DTL, MOS
(C) ECL, RTL, MOS, DTL (D) ECL, RTL, DTL, MOS
SOL 1.8 The correct order of increasing noise is RTL, ECL, DTL, MOS.
Hence (B) is correct option.
MCQ 1.9 The full scale output of a DAC is 10 mA. If resolution is to be less than 40 A ,
then required bits are
(A) 11 (B) 10
(C) 8 (D) 9
SOL 1.9 Hence (C) is correct option.
Resolution 40 A=
The step required 2504010m
= =
Therefore is requires 8 bits.
MCQ 1.10 Which one of the following is NOT a vectored interrupted ?
(A) TRAP (B) INTR
(C) RST 3 (D) RST 7.5
SOL 1.10 Vectored interrupts are those interrupts in which program control transfer to a
fixed location. In non vectored interrupts the location is not fixed. Here INTR is a
non-vectored interrupt.
Hence (B) is correct option.
Q. No. 11- 21 Carry Two Marks Each
MCQ 1.11 Consider the following loop
LXI H, 000AHLOOP : DCX B
MOV A, B
ORA C
JNZ LOOP
This loop will be executed
(A) 1 time (B) 10 times
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Page 5 Digital Electronics Chapter 1
(C) 11 times (D) infinite times
SOL 1.11 Hence (B) is correct option.
LXI B, 000 AH ; 00" C, 0AH" B
LOOP : DCX B ; CB - 1" B,
; flag not affectedMOV A, B ; B" A
ORA C ; A OR C" A, set flag
JNZ LOOP
Hence this loop will be executed 0AH or ten times.
Hence (B) is correct option.
MCQ 1.12 A 555 IC is connected as shown below. The range of oscillation frequency is
(A) 607 kHz 1.41f< < kHz (B) 208 kHz 496f# # kHz(C) 627 Hz 4.81f# # kHz (D) 5 kHz 9.4f# # kHz
SOL 1.12 Hence (C) is correct option.
f. ( )R R C0 693 2
1A B
=+
RA 10 kR1 = =
RB R xR2 3= +
& 10 Rk < B 110k#
fmin 0.693{10 )}0.016271
k 2(110k =
+= Hz
fmax 0.693{10 )}0.014.811
k 2(10k =
+= kHz
MCQ 1.13 In the circuit shown in figure below the output G is
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(A) G AC BD = + (B) G AB CD = +
(C) G A D5= (D) G B C5=
SOL 1.13 If either A or B is low, then diode D1 or D2 will conduct, and point E will be at
low.
If both A and B are high, diode D1 and D2 both are off, and point E is at high.
Thus D1 and D2 form the AND function E AB= and similarly F CD=
D5 and D6 form a OR gate, so
G E F= + ,
G AB CD = +
Hence (B) is correct option.
MCQ 1.14 A 4-bit right shift register is initialized to value 1000 for ( , , , )Q Q Q Q 3 2 1 0 . The D
input is derived from ,Q Q0 2 and Q3 through two XOR gates as shown in fig. below.
The pattern 1000 will appear at
(A) 3rd pulse (B) 7th pulse
(C) 6th pulse (D) 4 th pulse
SOL 1.14 After t t1= , at the first rising edge of clock, the output of shift register is 0110,
which is input to address line of ROM. At 0110 (6) data 1010 is stored which will
be on bus. At next rising edge of clock 1010 is applied to register. So at this time
data stored in ROM at 1010 (10), 1000 will be on bus.
Hence (C) is correct option.
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MCQ 1.15 For the logic circuit shown below the output Y is
(A) A B5 (B) A B5
(C) A B C5 5 (D) A B C5 5
SOL 1.15 Output is 1 when even parity
Therefore Y A B C 5 5=
Hence (D) is correct option.
MCQ 1.16 Consider the signed binary number 01000110A = and 11010011B= , where B is
in 2s complement and MSB is the sign bit. In list-I operation is given and is List-II
resultant binary number is given
List - I List - II
P. A B+ 1. 1 0 0 0 1 1 0 12. 1 1 1 0 0 1 1 1
Q. A B 3. 0 1 1 1 0 0 1 14. 1 0 0 0 1 1 1 0
R. B A 5. 0 0 0 1 1 0 1 06. 0 0 0 1 1 0 0 1
S. A B 7. 0 0 0 1 1 0 0 18. 0 1 0 1 1 0 1 1
The correct match is
P Q R S
(A) 5 7 4 2
(B) 6 3 1 2(C) 6 7 1 3
(D) 5 3 4 2
SOL 1.16 Here ,A B are 2s complement
A B+ , A 01000110
11010011
1 00011001
+ B
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Discard the carry 1
A B A B = + , A 01000110
00101101
01110011
+ B
B A , B 11010011
10111010
1 11000110
+ A
Discard the carry 1
A B A B = + , A 10111010
00101101
11100111
+ B
Hence (B) is correct option.
MCQ 1.17 The CMOS circuit shown below implements the logic function
(A) AB CD E + + (B) ( )( )A B C D E + +
(C) AB CD E + + (D) ( )( )A B C D E + +
SOL 1.17 If input E is LOW, output will not be LOW. It must be HIGH. Option (B) satisfy
this condition.
Hence (B) is correct option.
MCQ 1.18 Consider a binary weighted n-bit D/A converter shown in the following circuit
of figure. What is the tolerance of resistance to limit the output error to the
equivalent of21
! LSB ?
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(A)2 1
1n
(B)21
n
(C)21
n 1 (D) 2 11
n +
SOL 1.18 Required error in MSB /1 2# LSB
Let %x! is the tolerance in resistance
RV
Rx
V
1100
+a k
R
V21
2n 1#
x
x
1100
1100
1
+
+
a
a
k
k
21
n#
2x100
n# 1 , (2 1) 1
x x100 100
n# #+
x 100
2 1
1n# #
Hence (A) is correct option.
MCQ 1.19 Consider the following program
MVI A, DATA
MVI B, 64H
MVI C, C8H
CMP B
JC RJCT
CMP C
JNC RJCTOUT PORT1
HLT
RJCT : SUB A
OUT PORT1
HLT
If the following sequence of byte is loaded in accumulator,
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DATA (H) 58 64 73 B4 C8 FA
then sequence of output will be
(A) 00, 00, 73, B4, 00, FA (B) 58, 64, 00, 00, C8, FA
(C) 58, 00, 00, 00, C8, FA (D) 00, 64, 73, B4, 00, FA
SOL 1.19 This program will display the number between 64H to C8H including 64H. C8H
will not be displayed.
Hence (D) is correct option.
MCQ 1.20 The ideal inverter in figure below has a reference voltage of 2.5 V. The forward
voltage of the diode is 0.75 V. The maximum number of diode logic circuit, that
may be cascaded ahead of the inverter without producing logic error, is
(A) 3 (B) 4
(C) 5 (D) 9
SOL 1.20 Each diode causes a voltage level loss of 0.75 V.Therefore 0.75 2.5n< V 3n& =
Hence (A) is correct option.
MCQ 1.21 The following serial data are applied to the flip-flop through the AND gates as
shown in figure. There is one clock pulse for each bit time. Q is initially 0 and PRE
and CLR are high. If leftmost bits are applied first then output Q is
J1 : 1010011, J2 : 0111010, J3 : 1111000
K1 : 0001110, K2 : 1101100, K3 : 1010101
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(A) 0000111 (B) 0011000
(C) 0101000 (D) 1010101
SOL 1.21 By applying the serial bits for J and K inputs of the flip-flop
CLK 1 2 3 4 5 6 7J1 1 0 1 0 0 1 1
J2 0 1 1 1 0 1 0
J3 1 1 1 1 0 0 0
K1 0 0 0 1 1 1 0
K2 1 1 0 1 1 0 0
K3 1 0 1 0 1 0 1
J
K
Q
00
0
00
0
10
1
00
1
01
0
00
0
00
0
Hence (B) is correct option.
Common Data for Q. 22-23 :
The input-output voltage specification for the standard TTL family are as follows
: 2.4V ( )minOH = V, 0.4V ( )maxOL = V, 2.0V ( )minIH = V, and 0.8V ( )maxIL = V
MCQ 1.22 The maximum-amplitude nose spike, that can be tolerated when a HIGH input is
driving an input, is
(A) 0.4 V (B) 0.8 V
(C) 0.2 V (D) 0.6 V
SOL 1.22 When an output is HIGH, it may be as low as 2.4V ( )minOH = V. The minimum
voltage that an input will respond to as a HIGH is 2.0V ( )minIH = V. A negative noise
spike that can drive the actual voltage below 2.0 V if its amplitude is greater than
VNH V V( ) ( )min minOH IH =
2.4 2.0 0.4= = V
Hence (A) is correct option.
MCQ 1.23 The maximum-amplitude noise spike, that can be tolerated when a LOW output
is driving an input, is
(A) 0.4 V (B) 0.8 V
(C) 0.2 V (D) 0.6 V
SOL 1.23 When an output is LOW, it may be as high as 0.4V ( )maxOL = V. The maximum
voltage that an input will respond to as a LOW is 0.8V ( )maxIL = V. A positive noise
spike can drive the actual voltage above the 0.8 V level if its amplitude is greater
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than
VNL V V( ) ( )max maxIL OL=
0.8 0.4 0.4= = V
Hence (A) is correct option.
Statement for Linked Question 24-25 :
For the Schmitt trigger oscillator shown below saturation output voltage are 10+
V and 5 V.
MCQ 1.24 The frequency of oscillation is
(A) 2183 Hz (B) 869 Hz
(C) 1369 Hz (D) 1443 Hz
SOL 1.24 The switching voltage are
V+ 5
2
10= = V,
V+ 2.525
= = V
The charging and discharging of capacitor is shown in fig. S4.5.23
Hence 5 10 ( 2.5 10)e RCi1
= +
& e RCi1
52
=
& t1 2.5lnRC=
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2.5 5 (5 ( 5))e RCt2
= +
eRCt2
4lnt RC41
2&= = ,
T 2.5 4 10ln ln lnt t RC RC RC 1 2= + = + =
R 50 k= , 0.01 FC =& T 50 0.01 ln10 1.15k # #= = ms
f 869T1
= = Hz
Hence (B) is correct option.
MCQ 1.25 The duty cycle is
(A) 60.2% (B) 39.8%
(C) 48.4% (D) 51.6%
SOL 1.25 Hence (B) is correct option.Duty cycle 100
t tt
1 2
1#= +
ln .
ln . 100lnRC RC
RC2 5 4
2 5#=
+
. 100 39.8%102 5ln
ln #= =
Answer Sheet
1. (C) 6. (B) 11. (B) 16. (B) 21. (B)
2. (D) 7. (A) 12. (C) 17. (B) 22. (A)
3. (B) 8. (B) 13. (B) 18. (A) 23. (A)
4. (B) 9. (C) 14. (C) 19. (D) 24. (B)
5. (B) 10. (B) 15. (D) 20. (A) 25. (B)
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