simulation lab using verilog
TRANSCRIPT
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Simulation Lab Dept of ECE MREC
MALLA REDDY ENGINEERING COLLEGEMAISAMMAGUDA, DHULAPALLY, SECUNDERABAD-500014
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Certificate
This is to certify that this is the bonafide record work done by
Mr. /Miss.
Roll no..
Branch year.
Academic year.
SIMULATION LAB
Date:
Signature of examiner Signature of facultyWith date
Signature of Head of the Department
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Simulation Lab Dept of ECE MREC
SIMULATION LAB
S.No. LIST OF EXPERIMENTS Page No1 Logic gates 1-5
2 A Half adder 6-9B Full adder 10-15
C Serial adder behavioral model 16-20
D Parallel adder structural model 21-24
E Carry look ahead adder 25-30
3 A 2 x 4 decoder dataflow model 31-34
B 3 x 8 decoder behavioral model 35-37
C 4 x 16 decoder structural model 38-41
D 4:1 multiplexer dataflow & behavior model 42-45
E 16:1 multiplexer structural model 46-49F 8 x 3 Priority encoder structural model 50-56
4 A JK Flip Flop 57-62B RS Flip Flop 63-66
C D Flip Flop 67-70
D T Flip Flop 71-74
5 A Ring Counter 75-78B Johnson Counter 79-83
C Up- Down Counter 84-89
6 A N- bit Register of Serial- in Serial out 90-93
B N- bit Register of Serial in parallel out 94-97
C N- bit Register of Parallel in Serial out 98-102
D N- bit Register of Parallel in Parallel Out 103-107
7 A FSM Melay machine 108-112
B FSM Moore machine 113-117
8 A 4 bit multiplier 118-125
9 ALU 126-132
10 Real time clock 133-140
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Exp. No : 1 Logic gates 2
Simulation Lab Dept of ECE MREC
NAND GATE: NOR GATE:
XOR GATE: XNOR GATE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
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Exp. No : 1 Logic gates 3
Simulation Lab Dept of ECE MREC
PROGRAM:
module allgates(A, B, not1, or2, and3, nor4, nand5, xor6, xnor7);input A;input B;output not1;output or2;output and3;output nor4;output nand5;output xor6;output xnor7;reg not1;reg or2;reg and3;reg nor4;reg nand5;
reg xor6;reg xnor7;always@(A or B)beginnot1 = ~ A;or2 = A | B;and3 = A & B;nor4 = ~ (A | B);nand5 = ~ (A & B);xor6 = (A ^ B);xnor7 = ~ (A ^ B);
endendmodule
RTL SCHEMATIC DIAGRAM:
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Exp. No : 1 Logic gates 5
Simulation Lab Dept of ECE MREC
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Exp. No : 2a Half adder 6
Simulation Lab Dept of ECE MREC
AIM: To design half adder using dataflow,structural & behavioural model of VerilogHDL program and toperform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.2 d Xilinx ISE 9.2i FPGA device (Family: Spartan3, Device: XC3S400, Package: TQ144)
CIRCUIT DIAGRAM:
TRUTH TABLE:
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
BOOLEAN EXPRESSIONS:
S = a b b
C = a . b
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT Initialize JTAG
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Exp. No : 2a Half adder 7
Simulation Lab Dept of ECE MREC
Download program into kit
Verify the function of design model
PROGRAM(data flow model):
module halfadder(a, b, sum, carry);input a;input b;output sum;output carry;reg sum,carry;always@(a or b)beginsum=a^b;carry=a&b;endendmodule
PROGRAM(behavioural model):
module halfadder(a, b, sum, carry);input a;input b;output sum;output carry;reg sum,carry;always@(a or b)beginsum=a^b;carry=a&b;endendmodule
PROGRAM(structural model:
Module ha(a,b,sum,carry);Input a,b;Output sum,carry;
Xor x1(sum,a,b);And a1(carry,a,b);Endmodule
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Exp. No : 2a Half adder 8
Simulation Lab Dept of ECE MREC
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "a" LOC = "p74" ;NET "b" LOC = "p76" ;NET "c" LOC = "p84" ;NET "s" LOC = "p85" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT:Half adder using three models of VerilogHDL program is designed and simulation, synthesis, place & route
and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 2a Half adder 9
Simulation Lab Dept of ECE MREC
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Exp. No : 2b Full adder (dataflow model) 10
Simulation Lab Dept of ECE MREC
AIM: To design full adder using dataflow model of VerilogHDL program and to perform simulation,synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.2 d Xilinx ISE 9.2i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
CIRCUIT DIAGRAM:
TRUTH TABLE:
A B CIN SUM COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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Exp. No : 2b Full adder (dataflow model) 11
Simulation Lab Dept of ECE MREC
BOOLEAN EXPRESSIONS:
S um= ain bin cin
C = ain . bin + bin . cin + cin. ain
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM(dataflow model:
Module fa(a,b,cin,sum,cout);
Input a,b,cin;
Output sum,cout;
Assign #2 sum=a^b^cin;
Assign #2 cout=(a&b)|(b&cin)|(cin&a);
Endmodule
PROGRAM(behavioural model):
module fulladder(a, b, cin, sum, cout);
input a;input b;input cin;output sum;output cout;reg sum,cout;always@(a or b or cin)beginsum=a^b^cin;cout=(a&b)|(b&cin)|(cin&a);end
endmodule
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Exp. No : 2b Full adder (dataflow model) 15
Simulation Lab Dept of ECE MREC
Excersice: Simulate & synthesis half subtractor & Full subtractor using verilog
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Exp. No : 2c Serial Adder 16
Simulation Lab Dept of ECE MREC
AIM: To design serial adder using behavioral model of VerilogHDL program and to perform simulation,synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 dXilinx ISE 8.1 iFPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
CIRCUIT DIAGRAM:
PROCEDURE:
Check syntax.
View RTL schematic.
View Technology schematic.Perform simulation.
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Exp. No : 2c Serial Adder 17
Simulation Lab Dept of ECE MREC
Write ucf file.
Implement design.
View the synthesis report.
Configure target device using iMPACT.
Initialize JTAG.
Download program into kit.Verify the function of design model.
Verilog code for serial adder:module serial_adder(clk,addr,load,clear,data_in,calc,result);input clk,clear,calc,load;input [2:0]addr;input [11:0]data_in;output reg [11:0]result;reg [11:0]ram[7:0];reg [11:0]temp;
always@(negedge clk)beginif(clk)temp = ram[0] + ram[1];temp = (temp + ram[2]);temp = (temp + ram[3]);temp = (temp + ram[4]);temp = (temp + ram[5]);temp = (temp + ram[6]);temp = (temp + ram[7]);endalways@(posedge clk)
beginif(~clear)beginram[0]=12'b0;ram[1]=12'b0;ram[2]=12'b0;ram[3]=12'b0;ram[4]=12'b0;ram[5]=12'b0;ram[6]=12'b0;ram[7]=12'b0;
endelse if(~load)beginresult=data_in;ram[addr] = data_in;endelse if(~calc)result = temp;elseresult = ram[addr];end
endmodule
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Exp. No : 2c Serial Adder 18
Simulation Lab Dept of ECE MREC
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "a_i" LOC = "p84" ;
NET "b_i" LOC = "p86" ;
NET "c_i" LOC = "p87" ;
NET "c_o" LOC = "p89" ;
NET "CLK" LOC = "p74" ;
NET "I" LOC = "p76" ;
NET "I" LOC = "p102" ;
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Exp. No : 2c Serial Adder 19
Simulation Lab Dept of ECE MREC
NET "I" LOC = "p103" ;
NET "I" LOC = "p104" ;
NET "I" LOC = "p105" ;
NET "I" LOC = "p107" ;
NET "I" LOC = "p108" ;
NET "I" LOC = "p77" ;
NET "I" LOC = "p78" ;
NET "I" LOC = "p79" ;
NET "I" LOC = "p80" ;
NET "I" LOC = "p82" ;
NET "I" LOC = "p83" ;
NET "I" LOC = "p98" ;
NET "I" LOC = "p99" ;
NET "I" LOC = "p100" ;
NET "Load" LOC = "p112" ;
NET "O" LOC = "p90" ;
NET "O" LOC = "p92" ;NET "O" LOC = "p93" ;
NET "O" LOC = "p95" ;
NET "O" LOC = "p96" ;
NET "O" LOC = "p97" ;
NET "O" LOC = "p113" ;
NET "O" LOC = "p116" ;
NET "s_o" LOC = "p118" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 input
LUTs
Number of bondedIOBs
RESULT:Serial adder using behavioral model of VerilogHDL program is designed and simulation, synthesis, place &
route and implementation of the design using FPGA device is performed.
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Exp. No : 2c Serial Adder 20
Simulation Lab Dept of ECE MREC
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Exp. No : 2d PARALLEL ADDER 21
Simulation Lab Dept of ECE MREC
AIM: To design parallel adder using structural model of VerilogHDL program and to perform simulation,synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
STRUCTURAL MODEL DIAGRAM:
BOOLEAN EXPRESSIONS FOR FULL ADDER:
S um= ain bin cin
C = ain . bin + bin . cin + cin. ain
PROCEDURE:
Check syntaxView RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
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Exp. No : 2d PARALLEL ADDER 22
Simulation Lab Dept of ECE MREC
PROGRAM:
module padder(a,b,cin, sum, cout);parameter size=4;input [size:1] a, b;input cin;output [size:1]sum;output cout;wire [size-1:1]temp;fa_strfa1(a[1], b[1], cin, sum[1], temp[1]);fa2(a[2], b[2], temp[1], sum[2], temp[2]);fa2(a[3], b[3], temp[2], sum[3], temp[3]);fa2(a[4], b[4], temp[3], sum[4], temp[4]);endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "a" LOC = "p74" ;NET "a" LOC = "p76" ;NET "a" LOC = "p77" ;NET "a" LOC = "p78" ;NET "b" LOC = "p79" ;NET "b" LOC = "p80" ;NET "b" LOC = "p82" ;
NET "b" LOC = "p83" ;NET "ci" LOC = "p98" ;NET "co" LOC = "p84" ;
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Exp. No : 2d PARALLEL ADDER 23
Simulation Lab Dept of ECE MREC
NET "s" LOC = "p86" ;NET "s" LOC = "p87" ;NET "s" LOC = "p89" ;NET "s" LOC = "p90" ;
#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT:
Parallel adder using structural model of VerilogHDL program is designed and simulation, synthesis, place& route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 2d PARALLEL ADDER 24
Simulation Lab Dept of ECE MREC
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Exp. No : 2e Carry Look Ahead Adder 25
Simulation Lab Dept of ECE MREC
AIM: To design carry look ahead adder using behavioral model of VerilogHDL program and to performsimulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
CIRCUIT DIAGRAM:
BOOLEAN EXPRESSIONS:
Pi = Ai Bi Carry propagateGi = AiBi Carry generate
Si = Pi Ci-1Ci+1= Gi + PiCi
PROCEDURE:
Check syntax
View RTL schematic
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Exp. No : 2e Carry Look Ahead Adder 26
Simulation Lab Dept of ECE MREC
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM:
module cla4(s,cout,i1,i2,c0);output [3:0] s;putput cout;input [3:0] i1;input [3:0] i2;input c0;wire [3:0] s;wire cout;wire [3:0] g;wire [3:0] p;wire [3:1] c;assign g[3:0]=i1[3:0] & i2[3:0];assign p[3:0]=i1[3:0] ^ i2[3:0];assign c[1]=g[0] | (p[0] & c0);assign c[2]=g[1] | (g[0] & p[1]) | (p[0] & p[1] & c0);assign c[3]=g[2] | (g[1] & p[2]) | (g[0] & p[1] & p[2]) |(p[0] & p[1] & p[2] & c0);assign cout=g[3] | (g[2] & p[3]) | (g[1] & p[2] & p[3]) | (g[0] & p[1] & p[2] & p[3]) | (p[0] & p[1] & p[2] &p[3] & c0);assign s[0]=p[0]^c0;assign s[3:1]=p[3:1]^c[3:1];Endmodule
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Exp. No : 2e Carry Look Ahead Adder 28
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT:Carry look ahead adder using behavioral model of VerilogHDL program is designed and simulation,synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 2e Carry Look Ahead Adder 29
Simulation Lab Dept of ECE MREC
EXERCISE: Simulate & synthesis Multi Precession Adder using verilog.
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Exp. No : 2e Carry Look Ahead Adder 30
Simulation Lab Dept of ECE MREC
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Exp. No : 3a 2x4 Decoder (data flow model) 31
Simulation Lab Dept of ECE MREC
AIM: To design 2 x 4 decoder using dataflow model of VerilogHDL program and to perform simulation,synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
CIRCUIT DIAGRAM:
TRUTH TABLE:
En1 A(1) A(0) Z(3) Z(2) Z(1) Z(0)
1 X X 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
BOOLEAN EXPRESSIONS:
Z(0) = )0(.)1(.1 AAEN
Z(1) = )0().1(.1 AAEN
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Exp. No : 3a 2x4 Decoder (data flow model) 32
Simulation Lab Dept of ECE MREC
Z(2) = )0().1(.1 AAEN
Z(3) = )0().1(.1 AAEN
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit Verify the function of design model
PROGRAM:
Module dd24(a,b,en,z)Input a,b,en;Output [3:0]z;Wire abar,bbar;Assign #1 abar=~a;Assign #1 bbar=~b;Assign #2 z[0]=(abar & bbar & en);Assign #2 z[1]=(abar & b & en);Assign #2 Z[2]=(a & bbar & en);Assign #2 Z[3]=(a & b & en);Endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "a" LOC = "p74" ;NET "a" LOC = "p76" ;
NET "en1" LOC = "p77" ;NET "z" LOC = "p84" ;
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Exp. No : 3a 2x4 Decoder (data flow model) 33
Simulation Lab Dept of ECE MREC
NET "z" LOC = "p86" ;NET "z" LOC = "p87" ;NET "z" LOC = "p89" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
RESULT:2 x 4 Decoder using dataflow model of VerilogHDL program is designed and simulation, synthesis,place & route an d implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 3a 2x4 Decoder (data flow model) 34
Simulation Lab Dept of ECE MREC
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Exp. No : 3b 3x8 decoder (Behavioral model) 35
Simulation Lab Dept of ECE MREC
AIM: To design 3 x 8 decoder using behavioral model of VerilogHDL program and to perform simulation,synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
TRUTH TABLE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
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Exp. No : 3b 3x8 decoder (Behavioral model) 37
Simulation Lab Dept of ECE MREC
NET "A" LOC = "p76" ;NET "A" LOC = "p77" ;NET "G1" LOC = "p78" ;NET "G2a_l" LOC = "p79" ;NET "G2b_l" LOC = "p80" ;
NET "Y" LOC = "p84" ;NET "Y" LOC = "p86" ;NET "Y" LOC = "p87" ;NET "Y" LOC = "p89" ;NET "Y" LOC = "p90" ;NET "Y" LOC = "p92" ;NET "Y" LOC = "p93" ;NET "Y" LOC = "p96" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT:3 x 8 decoder using behavioral model of VerilogHDL program is designed and simulation, synthesis, place& route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 3c 4x16 decoder (Structural model) 38
Simulation Lab Dept of ECE MREC
AIM: To design 4 x 16 decoder using structural model of VerilogHDL program and to perform simulation,synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
TRUTH TABLE:
inputs outputs
en i3 i2 i1 i0 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y0
0 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 01 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 01 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 01 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 01 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PROCEDURE:Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design mode.
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Exp. No : 3c 4x16 decoder (Structural model) 39
Simulation Lab Dept of ECE MREC
PROGRAM:
module mux_16to1(y,in,en);
input [15:0] in;
input [3:0] sel;
wire lo8,hi8,out1;// Instantiate the 8-1 muxex and the 2-1 mux
Mux_8to1 mux_lo(lo8,in[7:0],sel[2:0]);
Mux_8to1 mux_hi(hi8,in[15:8],sel[2:0]);
Mux_2to1 mux_out(out1,lo8,hi8,sel[3]);
Assign y=out1;
End module
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "d" LOC = "p74" ;
NET "d" LOC = "p87" ;NET "d" LOC = "p89" ;NET "d" LOC = "p90" ;NET "d" LOC = "p92" ;NET "d" LOC = "p93" ;NET "d" LOC = "p95" ;NET "d" LOC = "p76" ;NET "d" LOC = "p77" ;NET "d" LOC = "p78" ;
NET "d" LOC = "p79" ;NET "d" LOC = "p80" ;NET "d" LOC = "p82" ;
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Exp. No : 3c 4x16 decoder (Structural model) 40
Simulation Lab Dept of ECE MREC
NET "d" LOC = "p83" ;NET "d" LOC = "p84" ;NET "d" LOC = "p86" ;NET "en" LOC = "p96" ;NET "s" LOC = "p97" ;NET "s" LOC = "p98" ;NET "s" LOC = "p99" ;NET "s" LOC = "p100" ;NET "y" LOC = "p102" ;NET "yn" LOC = "p103" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
RESULT:4 x 16 decoder using structural model of VerilogHDL program is designed and simulation,synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 3c 4x16 decoder (Structural model) 41
Simulation Lab Dept of ECE MREC
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Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 42
Simulation Lab Dept of ECE MREC
AIM: To design 4 : 1 Multiplexer using dataflow & behavioural model of VerilogHDL program and toperform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
TRUTH TABLE:
S1 S0 Y
0 0 I(0)
0 1 I(1)
1 0 I(2)
1 1 I(3)
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM(dataflow model):
Module mux41(i0, i1,i2, i3, s0, s1, out);Input i0, i1, i2, i3, s0, s1;Output out;Assign out=(`s1 & ~s0 & i0)|(~s1 & s0 & i1)|(s1 & ~s0 & i2)|(s1 & s0 & i3);Endmodule
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Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 43
Simulation Lab Dept of ECE MREC
PROGRAM(BEHAVIOURAL MODEL):
module mux(en, a, y,sel);input en;input [3:0] a;input[1:0] sel;
output y;reg y;always@(en or a)beginif(!en)y=1'b0;else case(sel)2'b00 : y = a[3];2'b01 : y = a[2];2'b10 : y = a[1];2'b11 : y = a[0];
Endcaseendendmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin Assignments
NET "i" LOC = "P74" ;NET "i" LOC = "P76" ;NET "s" LOC = "P77" ;NET "y" LOC = "P86" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
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Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 44
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
RESULT:4 : 1 Multiplexer using dataflow & behavioural model of VerilogHDL program is designed and
simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 45
Simulation Lab Dept of ECE MREC
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Exp. No : 3e 16x1 Multiplexer (Structural model) 46
Simulation Lab Dept of ECE MREC
AIM: To design a 16x1 Multiplexer using behavioral model of VerilogHDL program and to performsimulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
TRUTH TABLE:
PROCEDURE:
Check syntax View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
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Exp. No : 3e 16x1 Multiplexer (Structural model) 48
Simulation Lab Dept of ECE MREC
NET "i" LOC = "p100" ;NET "s3" LOC = "p102" ;NET "s3" LOC = "p103" ;NET "s3" LOC = "p104" ;NET "y8" LOC = "p85" ;
NET "y8l" LOC = "p86" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT:
A 16x1 Multiplexer using behavioral model of VerilogHDL program is designed and simulation, synthesis,place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Exp. No : 3e 16x1 Multiplexer (Structural model) 49
Simulation Lab Dept of ECE MREC
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Expt. No: 3f 8-BIT PRIORITY ENODER 50
Simulation Lab Dept of ECE MREC
AIM: To design an 8-Bit Priority Encoder using behavioral model of VerilogHDL program and to
perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 dXilinx ISE 8.1 iFPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
TRUTH TABLE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis reportConfigure target device using iMPACT
Initialize JTAGDownload program into kit
Verify the function of design model
PROGRAM:
Module priority (sel,code);Input [7:0] sel;Output [2:0] code;
Reg [2:0] code;Always @ (sel)Begin
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Expt. No: 3f 8-BIT PRIORITY ENODER 51
Simulation Lab Dept of ECE MREC
If (sel[0])Code=3b000;
Else if(sel[1])Code=3b001;
Else if(sel[2])
Code=3b010;Else if(sel[3])Code=3b011;
Else if(sel[4])Code=3b100;
Else if(sel[5])Code=3b101;
Else if(sel[6])Code=3b110;
Else if(sel[7])Code=3b111;
Else Code=3bxxx;Endendmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "A_L" LOC = "P85" ;NET "A_L" LOC = "P86" ;NET "A_L" LOC = "P87" ;NET "E0_L" LOC = "P89" ;NET "EI_L" LOC = "P74" ;
NET "GS_L" LOC = "P90" ;NET "I_L" LOC = "P76" ;NET "I_L" LOC = "P77" ;
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Expt. No: 3f 8-BIT PRIORITY ENODER 52
Simulation Lab Dept of ECE MREC
NET "I_L" LOC = "P78" ;NET "I_L" LOC = "P79" ;NET "I_L" LOC = "P80" ;NET "I_L" LOC = "P82" ;NET "I_L" LOC = "P83" ;
NET "I_L" LOC = "P84" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
RESULT:An 8-Bit Priority Encoder using behavioral model of VerilogHDL program is designed and simulation,synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Expt. No: 3f 8-BIT PRIORITY ENODER 53
Simulation Lab Dept of ECE MREC
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Expt. No: 3f 8-BIT PRIORITY ENODER 54
Simulation Lab Dept of ECE MREC
EXERSICE:
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Expt. No: 3f 8-BIT PRIORITY ENODER 55
Simulation Lab Dept of ECE MREC
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Expt.No:4a JK-FlipFlop 57
Simulation Lab Dept of ECE MREC
AIM: To design JK-flipflop with asynchronous reset using behavioral model of VerilogHDL program andto perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using IMPACT
Initialize JTAG Download program into kit
Verify the function of design model
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Expt.No:4a JK-FlipFlop 58
Simulation Lab Dept of ECE MREC
PROGRAM:
module JK_FF (JK, clock, q, qb);input [1:0] JK;input clock;output reg q, qb;always @ (posedge clock)begincase (JK)2'b00 : q = q;2'b01 : q = 1'b0;2'b10 : q = 1'b1;2'b11 : q =~ q;endcaseqb =~ q;endendmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "p74" ;NET "j" LOC = "p76" ;
NET "k" LOC = "p78" ;NET "q" LOC = "p79" ;NET "qn" LOC = "p85" ;NET "reset" LOC = "p80" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
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Expt.No:4a JK-FlipFlop 59
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT:
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBsNumber of Slice FlipFlopsNumber of GCLKs
RESULT:JK-flipflop with asynchronous reset using behavioral model of VHDL program is designed and simulation,synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Expt.No:4a JK-FlipFlop 60
Simulation Lab Dept of ECE MREC
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Expt.No:4a JK-FlipFlop 61
Simulation Lab Dept of ECE MREC
EXERSICE:
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Expt.No:4a JK-FlipFlop 62
Simulation Lab Dept of ECE MREC
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Expt no: 4b SR-FlipFlop 63
Simulation Lab Dept of ECE MREC
AIM: To design RS-flipflop with using behavioral model of VerilogHDL program and to performsimulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using IMPACT
Initialize JTAG
Download program into kitVerify the function of design mode
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Expt no: 4b SR-FlipFlop 64
Simulation Lab Dept of ECE MREC
PROGRAM:
module rs_ff(rs, clock, q, qb);input [1:0] rs;input clock;output reg q, qb;always @ (posedge clock)begincase (rs)2'b00 : q = q ;2'b01 : q = 1'b1 ;2'b10 : q = 1'b0 ;2'b11 : q = 1'dZ ;endcaseqb =~ q;end
endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "p74" ;NET "j" LOC = "p76" ;NET "k" LOC = "p78" ;NET "q" LOC = "p79" ;NET "qn" LOC = "p85" ;NET "reset" LOC = "p80" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
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Expt no: 4b SR-FlipFlop 65
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT:
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBsNumber of Slice FlipFlopsNumber of GCLKs
RESULT:An Asynchronous RS-flipflop using behavioral model of VerilogHDL program is designed and simulation,synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Expt no: 4b SR-FlipFlop 66
Simulation Lab Dept of ECE MREC
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Expt.No:4c D-FlipFlop 67
Simulation Lab Dept of ECE MREC
AIM: To design a D-flipflop with Asynchronous reset using behavioral model of VerilogHDL programand to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using IMPACT
Initialize JTAG
Download program into kit
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Expt.No:4c D-FlipFlop 68
Simulation Lab Dept of ECE MREC
Verify the function of design model
PROGRAM:
module dff (reset, clock, d, q, qb);input reset, clock, d;
output q, qb;reg q;wire qb;always @ (posedge clock)beginif (reset)q
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Expt.No:4c D-FlipFlop 69
Simulation Lab Dept of ECE MREC
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "p74" ;
NET "D" LOC = "p76" ;NET "q" LOC = "p77" ;NET "qbar" LOC = "p78" ;NET "rst" LOC = "p79" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
Number of Slice FlipFlops
Number of GCLKs
RESULT:
A D-flipflop with Asynchronous reset using behavioral model of VHDL program is designed andsimulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Expt.No:4c D-FlipFlop 70
Simulation Lab Dept of ECE MREC
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Expt.No:4d
Simulation Lab
AIM: To design a T-Flip Flop with Synchronprogram and to perform simulation, synthesis, pFPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400
Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
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Expt.No:4d
Simulation Lab
SYNTHESIS REPORT:
Devic
Logic Utilization Used
Number of Slices
Number of 4 inputLUTs
Number of bonded
IOBsNumber of Slice FlipFlops
Number of GCLKs
RESULT:A T-Flip Flop with Synchronous reset using besimulation, synthesis, place & route and implem
SIMULATION RESULT:
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Expt.No:5a Ring Counter 75
Simulation Lab Dept of ECE MREC
AIM: To design a Ring Counter using behavioral model of VerilogHDL program and to perform simulation,synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
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Expt.No:5a
Simulation Lab
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PAC#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "p74" ;NET "q" LOC = "p85" ;NET "q" LOC = "p86" ;NET "q" LOC = "p87" ;NET "q" LOC = "p89" ;#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Devic
Logic Utilization Used
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
Number of Slice Flip
FlopsNumber of GCLKs
RESULT:
A Ring Counter using behavioral model of Veriplace & route and implementation of the design
SIMULATION RESULT:
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Expt.No:5a
Simulation Lab
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Expt.No:5b Johnson Counter 79
Simulation Lab Dept of ECE MREC
AIM: To design a Johnson Counter using behavioral model of VerilogHDL program and toperform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 dXilinx ISE 8.1 iFPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
LOGIC DIAGRAM:
TRUTH TABLE:
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Expt.No:5b
Simulation Lab
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using IMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM:
Module jc(goleft,gorightstop,clk,q);Input goleft,goright,stop,clk;Output [3:0]q;Reg [3:0]q;
Always @(posedge clk)Begin
Reg run, dir;If (goright ==0)) beginDir=1b0;Run=1;EndIf (goleft ==0)) beginDir=1b1;Run=1;EndIf (stop ==0)) beginRun=0;EndIf (run) beginCasez (dir)1b1:begin
G[3:1]
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Expt.No:5b
Simulation Lab
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PAC#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "P74" ;NET "q" LOC = "P76" ;NET "q" LOC = "P85" ;NET "q" LOC = "P86" ;NET "q" LOC = "P89" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Devic
Logic Utilization Used
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
Number of Slice FlipFlops
Number of GCLKs
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Expt.No:5b
Simulation Lab
RESULT:A Johnson Counter using behavioral model of Vsynthesis, place & route and implementation of
SIMULATION RESULT:
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Expt.No:5b Johnson Counter 83
Simulation Lab Dept of ECE MREC
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Expt.No:5c UpDown Counter 84
Simulation Lab Dept of ECE MREC
AIM: To design an updown Counter using behavioral model of VerilogHDL program and to erformsimulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
TRUTH TABLE:
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
.
.
.
.1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
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Expt.No:5c UpDown Counter 85
Simulation Lab Dept of ECE MREC
PROGRAM:module counter1(clk,clr,up_down,q);input clk,clr,up_down;output [3:0] q;reg [3:0] tmp;
always @(posedge clk or posedge clr)beginif(clr)tmp
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Expt.No:5c UpDown Counter 86
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBsNumber of Slice FlipFlopsNumber of GCLKs
RESULT:
An updown Counter using behavioral model of VerilogHDL program is designed and simulation,synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Expt.No:5c UpDown Counter 88
Simulation Lab Dept of ECE MREC
EXERSICE:
Simulate & synthesis Binary ripple counter using Verilog HDL language.
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Expt.No:5c UpDown Counter 89
Simulation Lab Dept of ECE MREC
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93/143
Expt.No:6a
Simulation Lab
AIM: To design a Serial in serial out shift regand to perform simulation, synthesis, place & rodevice.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400
Package: TQ144)
LOGIC DIAGRAM:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT Initialize JTAG
Download program into kit
Verify the function of design model
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Expt.No:6a
Simulation Lab
PROGRAM:module Shiftn(clk, sIn, sOut);parameter n = 60; //number of stagesinput sIn, clk;output sOut;reg sOut;reg [n-1:0]state;always @(posedge clk) //sIn -> [0|1|...|n-1] -> sbeginsOut
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Expt.No:6a
Simulation Lab
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Expt.No:6b SIPO Shift Register 94
Simulation Lab Dept of ECE MREC
AIM: To design a Serial in Parallel out Shift Register using structural model of VerilogHDLprogram and to perform simulation, synthesis, place & route and implementation of the design usingFPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
LOGIC DIAGRAM:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM:
moduleserial_in_parallel_out#(parameterwIDTH=8) (input clk,data_inoutput [width-1:0] data_out);reg [width-1:0] shift_reg);always @ (posedge clk)shift_reg
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Expt.No:6b SIPO Shift Register 95
Simulation Lab Dept of ECE MREC
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "P74" ;NET "inp" LOC = "P76" ;NET "outp" LOC = "P85" ;NET "outp" LOC = "P86" ;NET "outp" LOC = "P87" ;NET "outp" LOC = "P89" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBsNumber of Slice Flip
FlopsNumber of GCLKs
RESULT:A SIPO Shift Register using structural model of VerilogHDL program is designed and simulation,synthesis, place & route and implementation of the design using FPGA device is performed.
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Expt.No:6b
Simulation Lab
SIMULATION RESULT:
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Expt.No:6b
Simulation Lab
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Expt.No:6c P
Simulation Lab
AIM: To design a Parallel in Parallel out Shifprogram and to perform simulation, synthesis, pFPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400
Package: TQ144)
LOGIC DIAGRAM:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using iMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM:
module pipo(din,clk,rst,dout);input [3:0] din;input clk,rst;output [3:0] dout;wire [3:0] din;wire clk,rst;reg [3:0] dout;always @(posedge clk or negedge rst)
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Expt.No:6c P
Simulation Lab
beginif(!rst)begin
dout
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Expt.No:6c P
Simulation Lab
NET "q" LOC = "P85" ;NET "q" LOC = "P86" ;NET "q" LOC = "P87" ;NET "serialin" LOC = "P80" ;NET "shift" LOC = "P82" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Devic
Logic Utilization Used
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
Number of Slice FlipFlops
Number of GCLKs
RESULT:
A PIPO Shift Register using structural model of synthesis, place & route and implementation of t
SIMULATION RESULT:
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Expt.No:6c P
Simulation Lab
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Expt.No:6d PISO Shift Register 106
Simulation Lab Dept of ECE MREC
SIMULATION RESULT:
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Expt.No:6d PISO Shift Register 107
Simulation Lab Dept of ECE MREC
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Expt.No:7a
Simulation Lab
AIM: To design a Mealy Detector using behasimulation, synthesis, place & route and implem
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
STATE DIAGRAM:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation Write ucf file
Implement design
View the synthesis report
Configure target device using IMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
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Expt.No:7a
Simulation Lab
state=2'b10;outp=0;enddefault:beginstate=2'b00;outp=0;endendcaseend
endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:#PACE: Start of Constraints generated by PAC#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "p74" ;NET "rst" LOC = "p76" ;NET "x" LOC = "p77" ;NET "z" LOC = "p85" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:Devic
Logic Utilization Used
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
Number of Slice FlipFlops
Number of GCLKs
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Expt.No:7a
Simulation Lab
RESULT:A Mealy Detector using behavioral model of Vesynthesis, place & route and implementation of t
SIMULATION RESULT:
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Expt.No:7a
Simulation Lab
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Expt.No:7b
Simulation Lab
AIM: To design a Moore Detector using behavsimulation, synthesis, place & route and implem
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
STATE DIAGRAM:
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
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Expt.No:7b
Simulation Lab
Configure target device using IMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM:
module fsmmoore1011( clk,rst,inp,outp);input clk,rst,inp;output outp;
reg [2:0]state;reg outp;always@(posedge clk or posedge rst)if(rst)beginstate=2'b000;outp=0;endelsebegincase(state)3'b000:if(inp)beginstate=3'b001;outp=0;
endelsebeginstate=3'b000;outp=0;end3'b001:if(inp)beginstate=3'b001;outp=0;endelsebeginstate=3'b010;outp=0;end
3'b010:if(inp)beginstate=3'b011;outp=0;endelsebeginstate=3'b000;outp=0;end3'b011:if(inp)
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Expt.No:7b
Simulation Lab
beginstate=3'b100;outp=0;endelsebeginstate=3'b010;outp=0;end
3'b100:if(inp)
beginstate=3'b001;outp=1;endelsebeginstate=3'b011;outp=1;enddefault:beginstate=3'b000;outp=0;endendcaseendendmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:#PACE: Start of Constraints generated by PAC#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "P74" ;NET "rst" LOC = "P76" ;NET "x" LOC = "P77" ;NET "z" LOC = "P85" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
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Expt.No:7b
Simulation Lab
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Expt.No:8 4-bit Multiplier 118
Simulation Lab Dept of ECE MREC
AIM: To design a 4-Bit Multiplier using behavioral model of VerilogHDL program and to performsimulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
CIRCUIT DIAGRAM:
PROCEDURE:
Check syntax
View RTL schematicView Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using IMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
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Expt.No:8 4-bit Multiplier 119
Simulation Lab Dept of ECE MREC
PROGRAM:
module HA(sout,cout,a,b);output sout,cout;input a,b;assign sout=a^b;assign cout=(a&b);endmodulemodule FA(sout,cout,a,b,cin);output sout,cout;input a,b,cin;assign sout=(a^b^cin);assign cout=((a&b)|(a&cin)|(b&cin));endmodulemodule multiply4bits(product,inp1,inp2);output [7:0]product;input [3:0]inp1;
input [3:0]inp2;assign product[0]=(inp1[0]&inp2[0]);wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);endmodule
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Expt.No:8
Simulation Lab
NET "product" LOC = "P89" ;NET "product" LOC = "P90" ;NET "product" LOC = "P92" ;NET "product" LOC = "P93" ;NET "product" LOC = "P96" ;NET "product" LOC = "P95" ;NET "st" LOC = "P99" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Devic
Logic Utilization Used
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
Number of Slice FlipFlops
Number of GCLKs
RESULT:A 4-Bit Multiplier using behavioral model of Vsynthesis, place & route and implementation of
SIMULATION RESULT:
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Expt.No:8
Simulation Lab
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Expt.No:8
Simulation Lab
EXERSICE:
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Expt.No:8
Simulation Lab
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Expt.No:8
Simulation Lab
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Expt.No:9 ALU(16-bit) 127
Simulation Lab Dept of ECE MREC
4'b0010: alu_out=b-4'b0001 ; // decrement data on port B4'b0011: alu_out=a+b; // ADD without CARRY4'b0100: alu_out=a+b+cin; // ADD with CARRY4'b0101: alu_out=a-b ; // SUB without BORROW4'b0110: alu_out=a-b+(~cin); // SUB with BORROW
4'b0111: alu_out=a&b; // AND4'b1000: alu_out=a|b; // OR4'b1001: alu_out=a^b; // EXOR4'b1010: alu_out={b[3:0],1'b0}; // Shift Left4'b1011: alu_out={b[0],1'b0,b[3:1]}; // Shift Right4'b1100: alu_out={b[3:0],cin}; // Rotate Left4'b1101: alu_out={b[0],cin,b[3:1]}; // Rotate Rightdefault : beginalu_out=9'bxxxxxxxxx;$display("Illegal CTL detected!!");end
endcase /* {...,...,...} is for the concatenation.{ADD_WITH_CARRY,SUB_WITH_BORROW}==2'b11 is usedto force the CARRY==1 for the increment operation */endfunction // end of function "result"
function z_flag ;input [4:0] a4 ;beginz_flag = ^(a4[0]|a4[1]|a4[2]|a4[3]) ; // zero flag check for a4endendfunction
endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "s" LOC = "p74" ;
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Expt.No:9 ALU(16-bit) 128
Simulation Lab Dept of ECE MREC
NET "s" LOC = "p76" ;NET "s" LOC = "p77" ;NET "s" LOC = "p111" ;NET "s" LOC = "p101" ;NET "w" LOC = "p78" ;
NET "w" LOC = "p90" ;NET "w" LOC = "p92" ;NET "w" LOC = "p93" ;NET "w" LOC = "p95" ;NET "w" LOC = "p96" ;NET "w" LOC = "p97" ;NET "w" LOC = "p98" ;NET "w" LOC = "p99" ;NET "w" LOC = "p100" ;NET "w" LOC = "p102" ;NET "w" LOC = "p79" ;
NET "w" LOC = "p103" ;NET "w" LOC = "p104" ;NET "w" LOC = "p105" ;NET "w" LOC = "p107" ;NET "w" LOC = "p108" ;NET "w" LOC = "p1" ;NET "w" LOC = "p2" ;NET "w" LOC = "p4" ;NET "w" LOC = "p5" ;NET "w" LOC = "p6" ;NET "w" LOC = "p80" ;NET "w" LOC = "p7" ;NET "w" LOC = "p8" ;NET "w" LOC = "p82" ;NET "w" LOC = "p83" ;NET "w" LOC = "p84" ;NET "w" LOC = "p85" ;NET "w" LOC = "p86" ;NET "w" LOC = "p87" ;NET "w" LOC = "p89" ;NET "x" LOC = "p10" ;NET "x" LOC = "p23" ;NET "x" LOC = "p24" ;NET "x" LOC = "p25" ;NET "x" LOC = "p26" ;NET "x" LOC = "p27" ;NET "x" LOC = "p28" ;NET "x" LOC = "p11" ;NET "x" LOC = "p12" ;NET "x" LOC = "p13" ;NET "x" LOC = "p14" ;NET "x" LOC = "p15" ;NET "x" LOC = "p17" ;NET "x" LOC = "p18" ;NET "x" LOC = "p20" ;NET "x" LOC = "p21" ;
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Expt.No:9 ALU(16-bit) 129
Simulation Lab Dept of ECE MREC
NET "y" LOC = "p30" ;NET "y" LOC = "p47" ;NET "y" LOC = "p50" ;NET "y" LOC = "p51" ;NET "y" LOC = "p52" ;
NET "y" LOC = "p53" ;NET "y" LOC = "p55" ;NET "y" LOC = "p31" ;NET "y" LOC = "p32" ;NET "y" LOC = "p33" ;NET "y" LOC = "p35" ;NET "y" LOC = "p36" ;NET "y" LOC = "p40" ;NET "y" LOC = "p41" ;NET "y" LOC = "p44" ;NET "y" LOC = "p46" ;
NET "z" LOC = "p56" ;NET "z" LOC = "p73" ;NET "z" LOC = "p112" ;NET "z" LOC = "p113" ;NET "z" LOC = "p116" ;NET "z" LOC = "p118" ;NET "z" LOC = "p119" ;NET "z" LOC = "p57" ;NET "z" LOC = "p58" ;NET "z" LOC = "p59" ;NET "z" LOC = "p60" ;NET "z" LOC = "p63" ;NET "z" LOC = "p65" ;NET "z" LOC = "p68" ;NET "z" LOC = "p69" ;NET "z" LOC = "p70" ;#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
Number of 4 inputLUTs
Number of bondedIOBs
Number of Slice FlipFlops
Number of GCLKs
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Expt.No:9 ALU(16-bit) 130
Simulation Lab Dept of ECE MREC
ESULT:ALU using behavioral model of VerilogHDL program is designed and simulation, synthesis, place& route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
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Expt.No:9 ALU(16-bit) 131
Simulation Lab Dept of ECE MREC
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Expt.No:9 ALU(16-bit) 132
Simulation Lab Dept of ECE MREC
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Expt.No:10 REAL TIME CLOCK 133
Simulation Lab Dept of ECE MREC
AIM: To design a Real Time Clock (2 digits, 7 segment LED displays each for Hours,Minutes and Seconds)and demonstrate its working on the FPGA Board.
TOOLS REQUIRED:
Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3
Device: XC3S400Package: TQ144)
PROCEDURE:
Check syntax
View RTL schematic
View Technology schematic
Perform simulation
Write ucf file
Implement design
View the synthesis report
Configure target device using IMPACT
Initialize JTAG
Download program into kit
Verify the function of design model
PROGRAM:
module real_time_clk_verilog (clk,clear,hour1,hour2,minute1,minute2,second1,second2, hour_A2, min_A1, sec_A0, load, data_in);input clk,clear;output reg [6:0]hour1,hour2,minute1,minute2,second1,second2;input load;input hour_A2,min_A1,sec_A0;input [7:0]data_in;reg clk_sec,clk_msec;reg [7:0]sec,min,hr;integer timer_count1=0,timer_count2=0;
always@(posedge clk)47beginif(timer_count1==3999)begintimer_count1=0;clk_msec=1'b1;endelsebegintimer_count1=timer_count1+1;
clk_msec=1'b0;endend
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Expt.No:10 REAL TIME CLOCK 136
Simulation Lab Dept of ECE MREC
default: second1=7'b0;endcaseendalways@(sec)begin
case(sec[7:4])4'b0000: second2=7'b1111110;4'b0001: second2=7'b0110000;4'b0010: second2=7'b1101101;4'b0011: second2=7'b1111001;4'b0100: second2=7'b0110011;4'b0101: second2=7'b1011011;4'b0110: second2=7'b1011111;4'b0111: second2=7'b1110000;4'b1000: second2=7'b1111111;50
4'b1001: second2=7'b1111011;default: second2=7'b0;endcaseendalways@(min)begincase(min[3:0])4'b0000: minute1=7'b1111110;4'b0001: minute1=7'b0110000;4'b0010: minute1=7'b1101101;4'b0011: minute1=7'b1111001;4'b0100: minute1=7'b0110011;4'b0101: minute1=7'b1011011;4'b0110: minute1=7'b1011111;4'b0111: minute1=7'b1110000;4'b1000: minute1=7'b1111111;4'b1001: minute1=7'b1111011;default: minute1=7'b0;endcaseendalways@(min)begincase(min[7:4])4'b0000: minute2=7'b1111110;4'b0001: minute2=7'b0110000;4'b0010: minute2=7'b1101101;4'b0011: minute2=7'b1111001;4'b0100: minute2=7'b0110011;4'b0101: minute2=7'b1011011;4'b0110: minute2=7'b1011111;4'b0111: minute2=7'b1110000;4'b1000: minute2=7'b1111111;4'b1001: minute2=7'b1111011;default: minute2=7'b0;endcaseend
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Expt.No:10 REAL TIME CLOCK 137
Simulation Lab Dept of ECE MREC
always@(hr)begincase(hr[3:0])4'b0000: hour1=7'b1111110;4'b0001: hour1=7'b0110000;
4'b0010: hour1=7'b1101101;4'b0011: hour1=7'b1111001;514'b0100: hour1=7'b0110011;4'b0101: hour1=7'b1011011;4'b0110: hour1=7'b1011111;4'b0111: hour1=7'b1110000;4'b1000: hour1=7'b1111111;4'b1001: hour1=7'b1111011;default: hour1=7'b1111110;endcase
endalways@(hr)begincase(hr[7:4])4'b0000: hour2=7'b1111110;4'b0001: hour2=7'b0110000;4'b0010: hour2=7'b1101101;default: hour2=7'b1111110;endcaseend
end module
UCF File(User Constraint File):
NET "clear" LOC = "p137" ;NET "clk" LOC = "p52" ;NET "data_in" LOC = "p92" ;NET "data_in" LOC = "p96" ;NET "data_in" LOC = "p74" ;NET "data_in" LOC = "p76" ;NET "data_in" LOC = "p77" ;NET "data_in" LOC = "p79" ;NET "data_in" LOC = "p84" ;NET "data_in" LOC = "p85" ;NET "hour1" LOC = "p95" ;NET "hour1" LOC = "p97" ;NET "hour1" LOC = "p98" ;NET "hour1" LOC = "p99" ;NET "hour1" LOC = "p104" ;NET "hour1" LOC = "p125" ;NET "hour1" LOC = "p122" ;
NET "hour2" LOC = "p112" ;NET "hour2" LOC = "p116" ;NET "hour2" LOC = "p119" ;NET "hour2" LOC = "p118" ;NET "hour2" LOC = "p123" ;
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Expt.No:10 REAL TIME CLOCK 138
Simulation Lab Dept of ECE MREC
NET "hour2" LOC = "p131" ;NET "hour2" LOC = "p93" ;NET "hour_A2" LOC = "p78" ;NET "load" LOC = "p83" ;NET "min_A1" LOC = "p82" ;
NET "minute1" LOC = "p14" ;NET "minute1" LOC = "p15" ;NET "minute1" LOC = "p17" ;NET "minute1" LOC = "p18" ;NET "minute1" LOC = "p21" ;NET "minute1" LOC = "p23" ;NET "minute1" LOC = "p24" ;NET "minute2" LOC = "p129" ;NET "minute2" LOC = "p132" ;NET "minute2" LOC = "p135" ;NET "minute2" LOC = "p140" ;
NET "minute2" LOC = "p1" ;NET "minute2" LOC = "p12" ;NET "minute2" LOC = "p13" ;NET "sec_A0" LOC = "p80" ;NET "second1" LOC = "p32" ;NET "second1" LOC = "p35" ;NET "second1" LOC = "p36" ;
NET "second1" LOC = "p40" ;NET "second1" LOC = "p41" ;NET "second1" LOC = "p56" ;NET "second1" LOC = "p60" ;NET "second2" LOC = "p26" ;NET "second2" LOC = "p27" ;NET "second2" LOC = "p6" ;NET "second2" LOC = "p7" ;NET "second2" LOC = "p8" ;NET "second2" LOC = "p11" ;
NET "second2" LOC = "p10" ;
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization Used Available Utilization
Number of Slices
umber of 4 input LUTs
umber of bonded IOBsumber of Slice Flip Flops
Number of GCLKs
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Expt.No:10 REAL TIME CLOCK 139
Simulation Lab Dept of ECE MREC
RESULT: Real time clock using VerilogHDL program is designed and simulation, synthesis, place & routeand implementation of the design using FPGA device is performed.
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