verilog lab manual

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1 LABORATORY MANUAL ECE 420 Digital VLSI Design

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Page 1: verilog lab manual

1

LABORATORY

MANUAL

ECE 420

Digital VLSI Design

Page 2: verilog lab manual

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Content

Experiment

No.

Name of Experiment Tool Used

1 Introduction to Xilinx software and

experiments before MTP

Xilinx 12.4

2 Write a program in Verilog to implement all

logic gates.

Xilinx 12.4

3 Write a program in verilog to implement half

adder/full adder/subtractor

Xilinx 12.4

4 Write a program in verilog to implement

multiplexer/demultiplexer

Xilinx 12.4

5 Write a program in verilog to implement

decoder/encoder

Xilinx 12.4

6 Write a program in verilog to implement 4

bit parallel adder using Gate level modelling

Xilinx 12.4

7 Introduction to experiments after MTP

Xilinx 12.4

8 Write a program in verilog to implement 4

bit ALU

Xilinx 12.4

9 Write a program in verilog to implement

code converters

Xilinx 12.4

10 Write a program in verilog to implement flip

flops

Xilinx 12.4

11 Write a program in verilog to implement

counters

Xilinx 12.4

12 Write a program in verilog to implement

sequence detector(0110/10101)

Xilinx 12.4

Page 3: verilog lab manual

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EXPERIMENT- 1

AIM: Introduction to Xilinx (ISE) Software and experiments before

MTP ISE controls all aspects of the design flow. Through the Project Navigator interface, you

can access all of the design entry and design implementation tools. You can also access

the files and documents associated with your project. Project Navigator maintains a flat

directory structure.

Project Navigator Interface:

The Project Navigator Interface is divided into four main sub windows. On the top left is

the Sources window which hierarchically displays the elements included in the project.

Beneath the Sources window is the Processes window, which displays available

processes for the currently selected source. The third window at the bottom of the Project

Navigator is the Transcript window which displays status messages, errors, and warnings

and also contains interactive tabs for Tcl scripting and the Find in Files function. The

fourth window to the right is a multi-document interface (MDI) window referred to as the

Workspace. It enables you to view html reports, ASCII text files, schematics, and

simulation waveforms.

Creating a New Project:

Fig 1.1

To create a new project, the user provides the project name is the window given below.

After naming the project the next step is to choose the simulator for the project.

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Then the New source file is opened by selecting the VHDL module and naming of the

file is also done by the user. The user can select the path of the file where he wants to

save his file. The input and output variables are defined in the next window show in the

figure along with its type i.e. in, out, inout. The figures are shown below for clear details:

Fig 1.2

For simulation of the project the clock values are required to be set ,this can be done by

using the below shown window. The single clock or multiple clock option is available

there according to the projects requirements. Also the value of clock delays is set here in

this window.

Fig 1.3

Logic Gates:

A logic gate is a general purpose electronic device used to construct logic circuits. All

logic gates have inputs and outputs. The state of the output is set by the input states using

Page 5: verilog lab manual

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different rules depending on the type of gate. The different types of gates have different

shaped circuit symbols.

AND GATE

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are

high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is

sometimes omitted i.e. AB.

Fig 1.4: AND GATE

Table1.1: Truth Table for AND Gate

A B out= A AND B

0 0 0

0 1 0

1 0 0

1 1 1

OR GATE

The OR gate is an electronic circuit that gives a high output (1) if one or more of its

inputs are high. A plus (+) is used to show the OR operation.

Fig 1.5: OR GATE

Table1.2: Truth Table for OR Gate

A B out= A OR B

0 0 0

0 1 1

1 0 1

1 1 0

NOT GATE

The NOT gate is an electronic circuit that produces an inverted version of the input at its

output. It is also known as an inverter. If the input variable is A, the inverted output is

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known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the

outputs.

Fig 1.6: NOT GATE

Table1.3: Truth Table for NOT Gate

A out= NOT A

0 1

1 0

HALF ADDER A half adder is a logical circuit that performs an addition operation on two one-bit binary

numbers often written as A and B. The half adder output is a sum of the two inputs

usually represented with the signals Sum and Carry i.e.

Sum= A xor B

Carry= A and B

Fig 1.7: Half Adder

FULL ADDER

A full adder is a logical circuit that performs an addition operation on three one-bit binary

numbers often written as A, B and C. The full adder output is a sum of the three inputs

usually represented with the signals Sum and Carry i.e.

Sum= A xor B xor C

Carry= (A and B) or (B and C) or (C and A)

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Fig 1.8: Full Adder

HALF SUBTRACTOR

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs D (difference)

and B (borrow).

Difference=a xor b;

Borrow=(not a) and b;

Fig 1.9: Half Subtractor

FULL SUBTRACTOR

The Full subtractor is a combinational circuit which is used to perform subtraction of

three bits. It has three inputs, A (minuend) and B (subtrahend) and C (subtrahend) and

two outputs D (difference) and B (borrow).

Difference=(a xor b) xor c;

Borrow= ((not a) and b) or (b and c) or (c and (not a));

Fig 1.10: Full Subtractor

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MULTIPLEXER

A multiplexer (MUX) is a digital switch which connects data from one of n sources to the

output. A number of select inputs determine which data source is connected to the output.

Fig 1.11: 4:1 Multiplexer

DEMULTIPLEXER

A multiplexer (MUX) is a digital switch which connects data from one input to the n

output. A number of select inputs determine input is connected to which output.

Fig 1.12: 1:4 De-multiplexer

ENCODER

In digital electronics, an encoder can take the form of a multiple-input, multiple-output

logic circuit that converts un-coded inputs into coded outputs, where the input and output

codes are different. e.g. 2n-to-n, binary-coded decimal encoders. Enable inputs must be

on for the encoder to function, otherwise its outputs assume a single "disabled" output

code word.

Page 9: verilog lab manual

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Fig 1.13: 4:2 Encoder

DECODER

In digital electronics, a decoder can take the form of a multiple-input, multiple-output

logic circuit that converts coded inputs into coded outputs, where the input and output

codes are different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be

on for the decoder to function, otherwise its outputs assume a single "disabled" output

code word.

Fig 1.14: 2:4 Decoder

PARALLEL ADDER

It is possible to create a logical circuit using multiple full adders to add N-bit numbers.

Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder

is a Parallel adder, since each bit is added in parallels. Note that the first (and only the

first) full adder may be replaced by a half adder.

Fig 1.15: 4-bit Parallel Adder

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EXPERIMENT- 2

AIM: Write a program in Verilog to implement all logic gates.

LEARNING OBJECTIVE:-To make the students familiar with concept of logic gates

using Verilog HDL and Simulate using Xilinx 12.4.

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Verilog Code for different gates

1. OR Gate using Data flow modeling

module or2 (a,b,c);

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input a,b;

output c;

assign c= a|b;

endmodule

2. AND Gate using behaviour modeling

module AND2gate (A, B, F);

input A;

input B;

output F;

reg F;

always @ (A or B)

begin

F <= A & B;

end

endmodule

3. NOT Gate using behaviour modeling

module NOTgate1(A, F);

input A;

output F;

reg F;

always @ (A)

begin

F <= ~A;

end

endmodule

Page 12: verilog lab manual

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Worksheet of the student

Date of Performance Registration

Number:

Aim: Write a program in Verilog to implement all logic gates.

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 13: verilog lab manual

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EXPERIMENT- 3

AIM : Write a program in verilog to implement half adder/full adder/subtractor

LEARNING OBJECTIVE:-To make the students Familiar different modeling style in

verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Page 14: verilog lab manual

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Half Adder Using Assign Statement

module halfadder (Cout, sum,a,b)

input a,b;

output Cout, sum);

assign sum = a ^ b;

assign Cout = a & b;

endmodule

Half Adder Gate level Description

module halfadder (Cout, sum,a,b)

input a,b;

output Cout, sum;

xor (sum, a, b);

and (Cout ,a,b);

endmodule

Testbench

Module half_addertb();

Reg a,b;

Wire Cout,sum;

Half_adder A1(a,b,Cout,sum);

Initial

Begin a=0;b=0;

#2 a=0;b=1;

#2 a=1;b=0;

#2 a=1;b=1;

#2 $stop;

end

endmodule

Full Adder Using Assign statement

module full_adder (a, b, ci, s, co);

input a, b, ci;

output s, co;

assign s = a ^ b ^ ci;

assign co = (a & b) | (a & ci) | (b & ci);

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endmodule

Full Adder with Gate level Description

module full_adder (a, b, ci, s, co);

input a, b, ci;

output s, co);

wire NET1, NET2, NET3, NET4 ;

xor ( NET1, a, b ); xor ( s , NET1, ci );

and ( NET2, a, b );

and ( NET3, a, ci );

and ( NET4, b, ci );

or ( co, NET2, NET3, NET4 );

endmodule

Testbench

Module full_addertb();

reg a,b,ci;

Wire co,s;

full_adder A1(a,b,ci,s,co);

Initial Begin a=0;b=0;c=0

#2 a=0;b=0;c=1

#2a=0;b=1;c=0

#2 a=0;b=1;c=1

#2a=1;b=0;c=0

#2 a=1;b=0;c=1

#2a=1;b=1;c=0

#2 a=1;b=1;c=1

#2 $stop;

end

endmodule

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Half Subtractor Gate level Description

module halfsubtractor (difference, borrow,a,b);

output difference, borrow;

input a,b;

wire Abar;

not #1 n1 (Abar, a);

and #1 a1(borrow,Abar,b);

xor #2 x1 (difference,a,b);

endmodule

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Worksheet of the student

Date of Performance Registration

Number:

Aim: Write a program in verilog to implement half adder/full adder/subtractor

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 18: verilog lab manual

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EXPERIMENT- 4

AIM: Write a program in verilog to implement multiplexer/ demultiplexer

LEARNING OBJECTIVE:-To make the students familiar with concept of

Multiplexer/ Demultiplexer using verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the top

left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Page 19: verilog lab manual

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Gate level Description

module mux4_1(D0,D1,D2,D3,S1,S0,Y);

input D0,D1,D2,D3,S1,S0;

output Y;

wire S1bar,S0bar,Y0,Y1,Y2,Y3;

not n1(S1bar,S1);

not n2(S0bar,S0);

and a1(Y0,S1bar,S0bar,D0);

and a2(Y1,S1bar,S0,D1);

and a3(Y2,S1,S0bar,D2);

and a4(Y3,S1,S0,D3);

or o1(Y,Y0,Y1,Y2,Y3);

endmodule

Using Case statement

module mux_using_case(din_0 ,din_1,sel,mux_out);

input din_0, din_1, sel ;

output mux_out;

reg mux_out;

always @ (sel or din_0 or din_1)

begin : MUX

case(sel ) 1'b0 :

mux_out = din_0; 1'b1 :

mux_out = din_1;

endcase

end

endmodule

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Worksheet of the student Date of Performance Registration

Number:

Aim: Write a program in verilog to implement multiplexer/ demultiplexer

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 21: verilog lab manual

21

EXPERIMENT 5

AIM: Write a program in verilog to implement decoder/encoder

LEARNING OBJECTIVE:-To make the students familiar with concept of

Decoder/Encoder using verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Page 22: verilog lab manual

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3:8 decoder using always

module decoder_always (in,out);

input [2:0] in;

output [7:0] out;

reg [7:0] out;

always @ (in)

begin

out = 0;

case (in)

3'b001 : out = 8'b0000_0001;

3'b010 : out = 8'b0000_0010;

3'b011 : out = 8'b0000_0100;

3'b100 : out = 8'b0000_1000;

3'b101 : out = 8'b0001_0000;

3'b110 : out = 8'b0100_0000;

3'b111 : out = 8'b1000_0000;

endcase

end

endmodule

8:3 encoder using always

module encoder_if( A, Y);

input [7:0] A;

output [2:0] Y;

reg [2:0] Y;

always @ (A)

begin

if (A==8'b00000001) Y=0;

else if (A==8'b00000010) Y=1;

else if (A==8'b00000100) Y=2;

else if (A==8'b00001000) Y=3;

else if (A==8'b00010000) Y=4;

else if (A==8'b00100000) Y=5;

else if (A==8'b01000000) Y=6;

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else if (A==8'b10000000) Y=7;

else Y=3'bX;

end

endmodule

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Worksheet of the student

Date of Performance Registration

Number:

Aim: Write a program in verilog to implement decoder/encoder

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 25: verilog lab manual

25

EXPERIMENT 6

AIM: Write a program in verilog to implement 4 bit parallel adder using Gate level

modeling

LEARNING OBJECTIVE:-To make the students familiar with concept of 4 bit

parallel adder using verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

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module parad4(sum,carry,a,b);

output [3:0]sum;

output carry;

input [3:0]a,b;

wire c1,c2,c3;

ha u1(sum[0],c1,a[0],b[0]);

fa u2(sum[1],c2,a[1],b[1],c1);

fa u3(sum[2],c3,a[2],b[2],c2);

fa u4(sum[3],carry,a[3],b[3],c3);

endmodule

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Worksheet of the student Date of Performance Registration

Number:

Aim: Write a program in verilog to implement 4 bit parallel adder using Gate level

modeling

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 28: verilog lab manual

28

EXPERIMENT 7

AIM: Introduction to experiments after MTP

LEARNING OBJECTIVE:-To make the students familiar with concept of all

practicals after MTP

ALU:

In computing, an arithmetic and logic unit (ALU) is a digital circuit that

performs integerarithmetic and logical operations. The ALU is a fundamental building

block of the central processing unit of a computer, and even the

simplest microprocessors contain one for purposes such as maintaining timers.

Code converters: Conversion of signals, or groups of signals, in one code into

corresponding signals, or groups of signals, in another code.

E.g. Grey to binary code converter

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EXPERIMENT 8

AIM: Write a program in verilog to implement 4 bit ALU

LEARNING OBJECTIVE:-To make the students familiar with concept of 4 bit

ALU using verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Page 30: verilog lab manual

30

Verilog code for 4 bit ALU

module alu(z,a,b,sel);

input [8:0]a,b;

input [3:0]sel;

output [8:0]z;

reg [8:0]z;

always@(sel,a,b)

begin

case(sel)

4′b0000: z=a+b;

4′b0001: z=a-b;

4'b0010: z=b-1;

4′b0011: z=a*b;

4′b0100: z=a&&b;

4′b0101: z=a||b;

4′b0110: z=!a;

4′b0111: z=~a;

4′b1000: z=a&b;

4′b1001: z=a|b;

4′b1010: z=a^b;

4′b1011: z=a<<1;

4′b1100: z=a>>1;

4′b1101: z=a+1;

4′b1110: z=a-1;

endcase

end

endmodule

Page 31: verilog lab manual

31

Worksheet of the student Date of Performance Registration

Number:

Aim: Write a program in verilog to implement 4 bit parallel adder using Gate level

modeling

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 32: verilog lab manual

32

EXPERIMENT 9

AIM: Write a program in verilog to implement code converters

LEARNING OBJECTIVE:-To make the students familiar with concept of code

converters i.e BCD to Grey and Grey to BCD etc. using verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

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BCD TO GRAY

module bcd2gray(Gray,BCD);

output [3:0]Gray;

input [3:0]BCD;

reg [3:0]Gray;

always @(BCD)

begin

Gray[3]=BCD[3];

Gray[2]=BCD[3]^BCD[2];

Gray[1]=BCD[2]^BCD[1];

Gray[0]=BCD[1]^BCD[0];

end endmodule

GRAY TO BCD

module bcd2gray(Gray,BCD);

output [3:0]BCD;

input [3:0]Gray;

reg [3:0]BCD;

always @(Gray)

begin

BCD[3]=Gray[3];

BCD[2]=BCD[3]^Gray[2];

BCD[1]=BCD[2]^Gray[1];

BCD[0]=BCD[1]^Gray[0];

end endmodule

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34

Worksheet of the student Date of Performance Registration

Number:

Aim: Write a program in verilog to implement code converters

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

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35

EXPERIMENT 10

AIM: Write a program in verilog to implement flip flops

LEARNING OBJECTIVE:-To make the students familiar with concept of flip flops

i.e D flip flop, T flipflop, SR flipflop and JK flip flop using verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Page 36: verilog lab manual

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JK FLIP FLOP

module JK_Flip_Flop (Q,Qbar,clk,reset,J,K);

output Q,Qbar;

input clk, reset,J,K;

reg Q;

always @(posedge clk)

if (reset)

begin

Q <= 0;

end

else if (J == 0 && K == 0)

begin

Q <= Q;

end

else if (J == 0 && K == 1)

begin

Q <= 0;

end

else if (J == 1 && K == 0)

begin

Q <= 1;

end

else if (J == 1 && K == 1)

begin

Q <= Qbar;

end

assign Qbar = ~Q;

endmodule

SR FLIP FLOP

module SR_Flip_Flop (Q,Qbar,clk,reset,S,R);

output Q,Qbar;

input clk, reset,S,R;

reg Q;

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37

always @(posedge clk)

if (reset)

begin

Q <= 0;

end

else if (S == 0 && R == 0)

begin

Q <= Q;

end

else if (S == 0 && R == 1)

begin

Q <= 0;

end

else if (S == 1 && R == 0)

begin

Q <= 1;

end

else if (S == 1 && R == 1)

begin

Q <= 1'bx;

end

assign Qbar = ~Q;

endmodule

D FLIP FLOP

module D_Flip_Flop (Q,clk,reset,d);

output Q;

input clk,reset,d;

reg Q;

always @(posedge clk)

if (reset)

begin

Q <= 0;

end

else begin

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38

Q <= d;

end

endmodule

T FLIP FLOP

module T_Flip_Flop (Q,clk,reset,t);

output Q;

input clk,reset,t;

reg Q;

always @(posedge clk)

if (reset)

begin

Q <= 0;

end

else if (t == 0)

begin

Q <= Q;

end

else if (t == 1)

begin

Q <= ~Q;

end

endmodule

Page 39: verilog lab manual

39

Worksheet of the student

Date of Performance Registration

Number:

Aim: To make the students familiar with concept of flip flops i.e D flip flop, T

flipflop, SR flipflop and JK flip flop using verilog HDL

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 40: verilog lab manual

40

EXPERIMENT 11

AIM: Write a program in verilog to implement counters

LEARNING OBJECTIVE:-To make the students familiar with concept of counters

i.e. UP DOWN Counter using verilog HDL

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Page 41: verilog lab manual

41

Verilog code for updown counter

module up_down_counter (out,up_down,clk,reset);

output [7:0] out;

input up_down, clk, reset;

reg [7:0] out;

always @(posedge clk)

if (reset) begin // active high reset

out <= 8'b0 ;

end else if (up_down) begin

out <= out + 1;

end else begin

out <= out - 1;

end

endmodule

Page 42: verilog lab manual

42

Worksheet of the student Date of Performance Registration

Number:

Aim: To make the students familiar with concept of counters i.e.UP DOWN Counter

using verilog HDL

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained

Page 43: verilog lab manual

43

EXPERIMENT 12

AIM: Write a program in verilog to implement sequence detector(0110/10101)

LEARNING OBJECTIVE:-To make the students familiar with concept of FSM and

how to implement different sequences using FSM

PROCEDURE:

1. Open a new project from the drop down menu by clicking in FILE given on the

top left of the screen.

2. Create a new project and name it.

3. Click on next to enter the device properties.

4. Select the appropriate properties according to the hardware to be used.

5. Click on the next button to enter the new source.

6. Here select the Verilog MODULE and give the file name.

7. Click on next button and enter the entity name.

8. Select the define module.

9. Select the ports as input and output and name them.

10. Click on next and then to on finish.

11. Write the code for the project under the library entity.

12. Save the program.

13. Select the behavioral simulation option from the three modeling options.

14. Now select the syntax check.

15. If the syntax check comes out to be correct, then precede further, otherwise check

errors.

16. Now select simulation option and select the test bench option.

17. Initialize the clock and other properties from the window that appears on the

screen.

18. Give the clock pulse to one of the inputs and save the program.

19. Click on simulate to get the output.

Page 44: verilog lab manual

44

SEQUENCE DETECTOR 0110 MOORE

module seq_dect_0110 (clk,data_in,reset,data_out);

input clk, data_in, reset;

output reg data_out;

reg [2:0]pr_state,nx_state;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;

always @ (posedge clk or posedge reset) begin

if (reset)

pr_state <= S0;

else

pr_state <= nx_state;

end

always @ (pr_state or data_in) begin

case (pr_state)

S0:

begin

data_out <= 0;

if (data_in ==1)

nx_state <= S0;

else

nx_state <= S1;

end

S1:

begin

data_out <= 0;

if (data_in==1)

nx_state <= S2;

else

nx_state <= S1;

end

S2:

begin

data_out <= 0;

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45

if (data_in ==1)

nx_state <= S3;

else

nx_state <= S1;

end

S3:

begin

data_out <= 0;

if (data_in==1)

nx_state <= S0;

else

nx_state <= S4;

end

S4:

begin

data_out <= 1;

if (data_in)

nx_state <= S2;

else

nx_state <= S1;

end

endcase

end

endmodule

SEQUENCE DETECTOR 10101 MOORE

module seq_dect_10101(clk,data_in,reset,data_out);

input clk, data_in, reset;

output reg data_out;

reg [2:0]pr_state,nx_state;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5;

always @ (posedge clk or posedge reset) begin

if (reset)

pr_state <= S0;

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46

else

pr_state <= nx_state;

end

always @ (pr_state or data_in) begin

ase (pr_state)

S0:

begin

data_out <= 0;

if (data_in ==1)

nx_state <= S1;

else

nx_state <= S0;

end

S1:

begin

data_out <= 0;

if (data_in==1)

nx_state <= S1;

else

nx_state <= S2;

end

S2:

begin

data_out <= 0;

if (data_in ==1)

nx_state <= S3;

else

nx_state <= S0;

end

S3:

begin

data_out <= 0;

if (data_in==1)

nx_state <= S1;

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47

else

nx_state <= S4;

end

S4:

begin

data_out <= 0;

if (data_in)

nx_state <= S5;

else

nx_state <= S0;

end

S5:

begin

data_out <= 1;

if (data_in)

nx_state <= S1;

else

nx_state <= S2;

end

endcase

end

endmodule

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48

Worksheet of the student

Date of Performance Registration

Number:

Aim: Write a program in verilog to implement sequence detector(0110/10101)

State Diagram/ ASM Chart (if any)

Attach Graph/Simulation Waveforms:

Result and Discussion:

Learning Outcomes (what I have learnt):

To be filled in by Faculty

S.No. Parameter (Scale from 1-10, 1 for very poor and 10 Marks Max. Marks excellent) Obtained

1 Understanding of the student about the 20 procedure/apparatus.

2 Observations and analysis including learning 20 Outcomes

3 Completion* of experiment, Discipline and 10 Cleanliness

Signature of Faculty Total marks Obtained