verilog hdl lab 2 (1)

7/23/2019 Verilog HDL LAB 2 (1)

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VERILOG HDL

LAB 2

Modeling TechniquesReg vs. Wire

Always @

parameterClock generator

D-flip-flop

UMKC FS 2015 A. Es-SakhiRohit Abhishek

1



Identifers

• An identifer is comosed o! a sace-!reese"#ence o! #ercase and $o%ercase $etters!rom a$habet& di'its (0,1,….9)& #nderscore

(*)& and the $ s+mbo$.• ,eri$o' is a case sensitie $an'#a'e.

– c_out_bar and C_OUT_BAR are t%o dierentidentifers

•

/he name o! a ariab$e ma+ not be'in %ith adi'it or $& and ma+ be # to 1&02 characters$on'. – e.'. clock_, state_3

UMKC FS 2015 A.Es-Sakhi Rohit Abhishek

2



Seci!+ Connectiit+

• ositiona$ association – Kee the same order as +o#r

mod#$e dec$aration – A3 test*nand1(o#t1& a& b)4

• E$icit association

– 6isted at an+ order (to aoid an+

and $osin' track o! +o#r orts. – A3 test*nand1 (.out(out1),.in1(a),

.in2(b));


7



3ata /+e

et8• %ire e$ements are #sed to connect in#t and

o#t#t orts o! a mod#$e instantiation to'ether%ith some other e$ement in +o#r desi'n.

•

%ire e$ements m#st be drien b+ somethin'&and cannot store a a$#e %itho#t bein' drien.

• %ire e$ements cannot be #sed as the $e!t-handside o! an 9 or :9 si'n in an a$%a+s; b$ock.

• %ire e$ements are a state$ess %a+ o! connectin'

t%o ieces in a ,eri$o'-based desi'n.%ire A & < & C & 3 & E 4 == sim$e 1 -bit %ide %ires

%ire >?80@ ide 4 == a B -bit %ide %ire




et cont.

assi'n A 9 < C 4 == #sin' a %ire%ith an assi'n statement

Eam$e

mod#$e %ire*eam$e( a& b& +)4in#t a& b4

o#t#t +4

%ire a& b& +4assi'n + 9 a b4

endmod#$eUMKC FS 2015 A.

Es-Sakhi Rohit Abhishek5

6e!t-hand side



3ata /+e

Re' (s+nthesiDed to a stora'e e$ement)

• re' is the on$+ $e'a$ t+e on the $e!t-hand side o! an a$%a+s; b$ock 9 or

:9 si'n.• re' is the on$+ $e'a$ t+e on the $e!t-

hand side o! an initia$ b$ock 9 si'n(#sed in /est <enches).

• re' cannot be #sed on the $e!t-handside o! an assi'n statement.


ire on$+



Re' cont.

re' & G & K 4 == sim$e 1 -bit %ide re'e$ements

re' >?80@ ide 4 == a B -bit %ide re'

e$ementa$%a+s ; ( A or < )

be'in

9 A H < 4 == #sin' a re' as the $e!t-hand side o! an a$%a+s; assi'nment

endIUMKC FS 2015 A.

Es-Sakhi Rohit AbhishekJ

re' on$+



Value Logic System

• 3ata t+e !or si'na$s

• <its (a$#e on a %ire) – 0, 1

– x #nkno% a$#e

• ,ectors o! bits (ara$$e$ %ires or re'isters) – !"#0$ is a ector o! bits8 A>7@& A>2@& A>1@&

A>0@

– Concatenatin' bits=ectors into a ector• %!&#0$ ' !"$, !"$, !"$, !"$, !"#0$;

• %!&#0$ ' "!"$, !"#0$;


?



M#$ti-<it Re'isters

• Eam$e – re' >J8 0@ </E4 ==? bites

– re' >18 1@ LR34 == 1 bits

–

re' >10278 0@ mem4 == 1k bits – #ide$ine8 #se >8 0@ !ormat

– re' >158 0@ ord4

– re' >J80@ </E4

– re' /em4

– /em9ord >@4

– </E9>158 ?@ ord4


B



,a$#e 6o'ic S+stem

• 088 $o'ic-0 or FA6SE

• 188 6o'ic-1 or /RUE

• N88 Unkno%n (or donOt care)

• P88 Qi'h imedance

• A$$ #nconnected nets set to DO

•

A$$ re'ister ariab$es set to O


10



*ata +yes# -onstants

• A constant is dec$ared %ith theke+%ord arameter in a statementassi'nin' a name and a a$#e to the

constant• /he a$#e o! a constant is fed

d#rin' sim#$ation.

• Eam$es8 – arameter QQ*3EN9 714 == inte'er

– arameter </E*SPE 9 ?4UMKC FS 2015 A.




rimiti/es

• o dec$aration re"#ired (redefned) 4• Can on$+ be instantiated• Eam$e8 and a1 (C& A& <)4 ==instance

name – Us#a$$+ better to roide instance name !ordeb#''in'.

• Eam$e8• or o1 (SE/& A& C )&

o2(& A<C&SE/ )4• Eam$e8

• and T(10) a2(o& i1& i2)4 == name de$a+


12



3ata /+es8 Constantsarameter

• mod#$e m+*mod#$e (C$k& 3& V) 4

•

arameter %idth 9 2& de$a+ 9 10 4• in#t >%idth - 1 8 0@ 3 4

• in#t C$k 4

•

o#t#t >%idth 8 0@ V 4• assi'n Tde$a+ V 9 34

• endmod#$e


17



Mode$in' t+es

• 3ataWo% Mode$in'

• <ehaiora$ Mode$in'

•

Str#ct#ra$ Mode$in'


1



3ataWo% mode$in'

• Continuous assignents

• A contin#o#s assi'nment statement starts%ith the ke+%ord assi'n

•

==S+nta o! assi'n statement in the sim$est!orm : contin#o#s*assi'n X

8 8 9 assi'n : drie*stren'th X Y : de$a+ X Y :$ist*o!*assi'nments X 4

Eam$e8assi'n o#t9in1in24

assi'n Zc*o#t&s#m>780@[9a>780@b>780@ c*in 4


15



<ehaiora$ mode$in'

• Contains roced#ra$ statements%hich contro$ the sim#$ation andmani#$ate ariab$es o! the data

t+es reio#s$+ described.• /hese statements are contained

%ithin roced#res.

• Each roced#re has an actiit+ Wo%associated %ith it.


1



• ,eri$o' contains t%o str#ct#red roced#re or behaiors8 initia$ and a$%a+s

•A behaior ma+ consist o! a sin'$e statement or ab$ock o! statement de$imited b+ ke+%ords begin….en!

• A mod#$e ma+ hae m#$ti$e initia$ and a$%a+sstatements

A$%a+s statement eec#tes the behaiora$ statement %ithin

the a$%a+s b$ock in a $ooin' mannerS+nta

A$%a+s>otiona$ timin' contro$@ roced#ra$ statement or b$ocko! roced#ra$ statements

• nitia$ statement s+nta – nitia$>otiona$ timin' contro$@ roced#ra$ statement or

b$ock o! roced#ra$ statements


1J




1?



Str#ct#ra$ mode$in'

• /o $ee$ desi'n that is s+nthesiDedb+ instantiatin' $o%er $ee$ $o'icmod#$es into a $ar'er str#ct#ra$

mod#$e.• Can be described #sin' b#i$t-in 'ate

rimities& #ser-defned rimities& or

mod#$e instances in an+combination.


1B




20




21



Qa$! Adder

mod#$e ha$!*adder (in*& in*+& o#t*s#m&o#t*carr+)4

in#t in*4

in#t in*+4o#t#t o#t*s#m4

o#t#t o#t*carr+4

assi'n o#t*s#m 9 in*\in*+4assi'n o#t*carr+ 9 in*in*+4

endmod#$e


22



F#$$ Addermod#$e !#$*adder (in*1& in*+1&cin& o#t*s#m1& o#t*carr+1)4

in#t in*14

in#t in*+1&cin4

o#t#t o#t*s#m14

o#t#t o#t*carr+14

%ire in*1& in*+1&cin4

%ire o#t*s#m1& o#t*carr+14

%ire net1&net2&net&net54

assi'n o#t*s#m19net4assi'n o#t*carr+19net1Hnet54

ha$!*adder inst1(

.in*(in*1)&

.in*+(in*+1)&

.o#t*s#m(net2)&

.o#t*carr+(net1)

)4

ha$!*adder inst2( .in*(net2)&

.in*+(cin)&

.o#t*s#m(net)&

.o#t*carr+(net5)

)4

endmod#$e


27



/est <ench !or !#$$ addermod#$e !#$$*adder*tb4

re' in*1& in*+1&cin4

%ire o#t*s#m1& o#t*carr+14

initia$

]monitor(^in*19_b&in*+19_b&cin9_b&o#t*s#m19_b&o#t*carr+19_b&^&in*1& in*+1&cin& o#t*s#m1&o#t*carr+1)4

initia$

be'in

T0 in*191`b04in*+191`b04cin91`b04

T10 in*191`b04 in*+191`b04cin91`b14

T10 in*191`b04 in*+191`b14cin91`b04

T10 in*191`b04 in*+191`b14cin91`b14

T10 in*191`b14 in*+191`b04cin91`b04

T10 in*191`b14 in*+191`b04cin91`b14

T10 in*191`b14 in*+191`b14cin91`b04

T10 in*191`b14 in*+191`b14cin91`b14

T10 ]sto4end

!#$*adder inst1(in*1& in*+1&cin& o#t*s#m1& o#t*carr+1)4

endmod#$e


2



Assi'nment

• bit ri$e Adder #sin' str#ct#ra$mode$in'.


25



Ed'e-tri''ered 3 Wi-Wo


2

C6K



3FF

• mod#$e d*(c$k& d& ")4

• in#t c$k4

• in#t d4

•

o#t#t "4• re' "4

• a$%a+s ;(osed'e c$k)

• be'in

• " :9 d4• end

• endmod#$e


2J



3FF 3FF*tbRe'isters and %ires


2?

Stim#$#s

ResonseRes#$tchecker



-reating -locs

xamle 2Qere are eam$es o! a s+mmetric c$ock %ith de$a+ed start#8


2B

0 20 0 0c$kre' c$k4

initia$ be'in

T20 c$k 9 14 !oreer be'in T10 c$k 904 T10 c$k 914 end endre' start4nand T10(c$k&c$k&start)4initia$ be'in

T10 start 9 04 T10 start 9 14



C6K data !or 3FF

• re' d*in90& reset91& c$ock904

• a$%a+s T7J d*in 9 d*in 74

• a$%a+s T11 c$k 9 c$k4

• initia$ T150 ]sto4UMKC FS 2015 A.


Variables used in theleft-hand-sides in theprocedural blocks aredeclared as reg

eriods o clock and

d3in can bec4anged to mae c4ect4e /alidity our design

A stoppedsimulationcan be resumed.

A stopped

simulationcan be resumed.



C$ock 'enerator

• Fallowing examples show simple clock generators with 50% duty cycles .

EXAMPLE:

initial clk = 0;

always #10 clk = ~clk;

UMKC FS 2015 A.E S khi R hit Abhi h k

71

EXAMPLE:

always

beginclk = 0;

#10;

clk = 1;

#10;end

EXAMPLE:

always

beginclk = 0;

foreer #10 clk =

~clk;

end

verilog hdl lab 2 (1)

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