session 07 v.3

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Session Seven

Introduced by

Cairo-Egypt

Version 03 – June 20121


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about Start Group

2

Mahmoud AbdellatifAlaa Salah Shehata Mohamed SalahMohamed Talaat

[email protected] www.slideshare.net/StartGroup

www.facebook.com/groups/start.group www.startgroup.weebly.com [email protected]

+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011+ 02 0128-0090250 A.S

Session Six



mini-Project Discussion

Session Four 3

ScramblerA(i) B(i)

B(i)=[A(i)+C(i)]mod2



Outline

Session Seven 4

Structural Description

Generic Using Package

Generate Statement

7



Outline

Session Seven 5



Generate Statement




Session Seven 6

Structural description allows having multiple levels of hierarchy in the design

Top- Down Design

The Design starts with the top-level block. This design is then partitioned into lower-level blocks till the root-level of your design is reached.

8 bit Adder

Full Adder

Half Adder




Session Seven 7

Bottom-Up Design

Used when the design is very large.

When using a bottom-up design methodology. the design begins with knowledge of the root and is then partitioned based on which primitives are available as leaf-nodes.



Structural Description [Component]

Session Seven 8

1-Component Declaration

The basic element of hirarichal design is component

Component : Creates an instance of another entity.Note The definition of the component is like the definition of the entity. Component is Previously coded, simulated, synthesized and placed in design library Components are defined inside Architecture in Architecture Declaration before begin

component <component_name>port ( <port_names>: <mode> <type>;

<port_names>: <mode> <type>;….

);end component;



Structural Description [Instantiation]

Session Seven 9

2-Component instantiation and Interconnections method 1

Each signal is written in the position that describe which port it belongs to which means that the first signal written here represent the first port in the component.That is named association-instantiation by position.

Noteif you needn't use special output port, Using the key word open (that mean this port will be unconnected). This method is easier but bad in readability.

instance_name: component_name port map (signal1,signal2,…);



Structural Description [Instantiation]

Session Seven 10

2-Component instantiation and Interconnections method 2

That is named instantiation by name.Order is not important.

• The left part of the expression serve as name of port of the component• The right part of the expression serves as name of connected signal (or port of other component).

<instance_name>: <component_name >port map(<port_name> => <sig_name>,<port_name> => <sig_name>,

….<port_name> => <sig_name> );



Example 25

Session Seven 11

Logic Gate

entity test is Port (

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; f : out STD_LOGIC);

end test; architecture Behavioral of test is component or_gate is

Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_or : out STD_LOGIC);

end component ;

component and_gate is Port ( in1 : in STD_LOGIC;

in2 : in STD_LOGIC; out_and : out STD_LOGIC);

end component;

AND gate

AND gate

ORgate



Example 25

Session Seven 12

Logic Gate

…signal sig1,sig2 : std_logic;

begin u1:and_gate port map (a,b,sig1);

u2:and_gate port map (c,d,sig2);

u3:or_gate port map (sig1,sig2,f);

end Behavioral;

AND gate

AND gate

ORgate



Example 26

Session Seven 13

Logic Gate

AND gate

AND gate

ORgate

entity test is Port (

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; f : out STD_LOGIC);

end test; architecture Behavioral of test is component or_gate is

Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_or : out STD_LOGIC);

end component ;

component and_gate is Port ( in1 : in STD_LOGIC;

in2 : in STD_LOGIC; out_and : out STD_LOGIC);

end component;



Example 26

Session Seven 14

Logic Gatesignal sig1,sig2 : std_logic;

begin u1:and_gate port map (

in1 => a, in2 => b, out_and => sig1);

u2:and_gate port map (

in1 => c, in2 => d, out_and => sig2);

u3:or_gate port map (

in1 => sig1, in2 => sig2, out_or => f);

end Behavioral;

AND gate

AND gate

ORgate



Lab 09

Session Seven 15

Title:Using Structural Description

Goal: Using Xilinx to Generate Instantiations Using Structural Described codes



Lab 09

Session Seven 16

Entity comp4 is port ( a , b : in std_logic_vector(3 downto 0); eq : out std_logic ); End comp4 ;

Architecture struct of comp4 is

Component xnor_2 is port ( g , f : in std_logic ;

y : out std_logic ); End component ;

Component and_4 is port ( in1,in2,in3,in4 :in std_logic;out1 : out std_logic );

End component ; …



Lab 09

Session Seven 17

…Signal x : std_logic_vector ( 3 downto 0 ) ;

Begin U1 : xnor_2 port map ( a(0) , b(0) , x(0) ) ; U2 :

xnor_2 port map ( a(1) , b(1) , x(1) ) ; U3 : xnor_2 port map ( a(2) , b(2) , x(2) ) ; U4 : xnor_2 port map ( a(3) , b(3) , x(3) ) ; U5 : and_4 port map ( x(0) , x(1) , x(2) , x(3) ,

eq ) ;End struct ;



Outline

Session Seven 18



Generate Statement



Generic

Session Seven 19

VHDL provides an easy way to create generic design units that can be used several times with different properties in the design hierarchy

Syntax

generic ( <identifier>: type [:= default_value];

<identifier>: type [:= default_value]) );

4-bit counter

8-bit counter

N-bit counter



Example 27

Session Seven 20

Logic Gate

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity generic_and is generic (N : integer := 4 ); port(A, B : in std_logic_vector (N-1 downto 0); Z : out std_logic_vector(N-1 downto 0) ); End entity;

Architecture behave of generic_and is Begin Z <= A and B; End architecture

AND gate



Example 28

Session Seven 21

N-bit Full Adder

Entity F_adder is Generic ( N : integer := 4 );Port ( A, B : in std_logic_vector(N-1 downto 0); C_in : in std_logic ; Sum : out std_logic_vector(N-1 downto 0); C_out : out std_logic ) ;End F_adder ; …

N bitFull Adder

A

B

Sum

C_out

C_in



Example 28

Session Seven 22

N-bit Full AdderArchitecture struct of f_adder is

Component n_adder Generic ( N : integer := 4 ); Port ( A,B : in std_logic_vector(N-1 downto 0); C_in : in std_logic ; Sum : out std_logic_vector(N-1 downto 0); C_out : out std_logic );End component ;

Begin U1 : n_adder generic map (8) port map (

A => A, B => B , c_in => C_in , sum => Sun , c_out => C_out);

End struct

N bitFull Adder

A

B

Sum

C_out

C_in



Outline

Session Seven 23



Generate Statement



Using Packages

Session Seven 24

Instead of declaring all components can declare all components in a PACKAGE, and INCLUDE the package once

1) This makes the top-level entity code cleaner 2) It also allows that complete package to be used by another designer

A package can contain

1) Components2) Functions, Procedures3) Types, Constants



Example 29

Session Seven 25

Logic circuit using package library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

package logic_circuit is component or_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_or : out STD_LOGIC); end component ;

component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC); end component;

constant const1: STD_LOGIC_vector (3 downto 0) := "0011"; ---const definition end logic_circuit;

AND gate

AND gate

ORgate

constant const1: STD_LOGIC_vector (3 downto 0) := "0011";



Example 29

Session Seven 26

Logic circuit using package

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.logic_circuit.all;

entity test is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; Out1 : out STD_LOGIC_vector (3 downto 0); f : out STD_LOGIC); end test;

architecture Behavioral of test is signal sig1,sig2 : std_logic;

begin .

. u1:and_gate port map ( in1 => a, in2 => b, out_and => sig1);

u2:and_gate port map ( in1 => c, in2 => d, out_and => sig2);

u3:or_gate port map ( in1 => sig1, in2 => sig2, out_or => f);

out1<= const1;

end Behavioral;



Outline

Session Seven 27



Generate Statement



Generate Statement

Session Seven 28

The generate statement simplifies description of regular design structures. Usually it is used to specify a group of identical components using just one component specification and repeating it using the generate mechanism.

Declaration

Label : for identifier IN range GENERATE (concurrent assignments)

.

. END GENERATE;



Example 30

Session Seven 29

SEREIS OF XOR GATES

ENTITY parity IS PORT(

parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC );

END parity;



Example 30

Session Seven 30

SEREIS OF XOR GATES

xor_out(1) <= parity_in(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);parity_out <= xor_out(6) XOR parity_in(7);

xor_out(1)xor_out(2)

xor_out(3) xor_out(4)xor_out(5) xor_out(6)



Example 30

Session Seven 31

SEREIS OF XOR GATES xor_out(1)

xor_out(2)xor_out(3) xor_out(4)

xor_out(5) xor_out(6)xor_out(0)

xor_out(7)

xor_out(0) <= parity_in(0);xor_out(1) <= xor_out(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);xor_out(7) <= xor_out(6) XOR parity_in(7);parity_out <= xor_out(7);



Example 30

Session Seven 32

SEREIS OF XOR GATES

ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN xor_out(0) <= parity_in(0);

G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i);

END GENERATE G2;

parity_out <= xor_out(7);

END parity_dataflow;



Session Six 33

Start Notes [Synthesis Notes]


In VHDL-93 standard, an entity-architecture pair may be directly instantiated, i.e.component need not declared. This is easier. but not readably.

architecture rtl of full adder Is signal col .co2: std_logic; signal a_xor_b : std_logic; begin ul: entity work.half_adder(behave)

port map (a,b.axorb.col); u2: entity work.half_adder(behave)

port map( axorb,ci,s,co2); co< col or cO2;

end architecture rtl;



Assignment 07

Session Seven 34

Study Well for Next session’s Evaluation Test



Summary

Session Seven 35

- Structural description allows having multiple levels of hierarchy in the design - VHDL provides an easy way to create generic design units that can be used several times with

different properties in the design hierarchy.- The generate statement used to specify a group of identical components using just one

component specification and repeating it using the generate mechanism.

Examples Exercises Labs

25-30 - 9



Time for Your Questions

Session Seven 36



Take Your NotesPrint the slides and take your notes here

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See You Next Session .. Don’t miss

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You

session 07 v.3

Technology