session 05 v.3

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Session Five

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Cairo-Egypt

Version 03 – June 20121Session Five


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about Start Group

2

Mahmoud AbdellatifAlaa Salah Shehata Mohamed SalahMohamed Talaat

[email protected] www.slideshare.net/StartGroup

www.facebook.com/groups/start.group www.startgroup.weebly.com [email protected]

+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011+ 02 0128-0090250 A.S

Session Five



Outline

Session Five 3

Data Types- Scalar- Composite- User defined

Modeling Memories

Mini Project no.2 Scrambler

5



Outline

Session Five 4


Modeling Memories




Data Types Hierarchy

Session Five 5

Dat

a Ty

pes

Scalar

Discrete

IntegersNatural

Positive

Enumeration

Boolean

Character

BitPhysical Time

Floating Point Real

CompositeArray

Bit Vector

StringRecord

File



Data Types

Session Five 6

-Type declaration is made inside architecture declaration, entity declaration, process declaration

-VHDL is a strongly typed language, meaning that data objects of different types cannot be assigned to one another without the use of a type conversion function.

Data Types can be classified into:

1–Scalar typesRefers to all types whose objects have a single value at any time instant.

2–Composite typesRefers to types that have a regular structure consisting of elements of the same type

such as array or elements of different types such as record.

3–User defined types Types that are defined by default and to be defined by the user before using.



Outline

Session Five 7


Modeling Memories




Data Types [Scalar Types]

Session Five 8

-Refers to all types whose objects have a single value at any time instant. 1- Discrete types -Enumerated types a–Bit

defines two standard logic values (‘0’, ‘1’) b–Boolean

defined as FALSE or TRUE c–Character

type enumerates the ASCII character set character ( ‘@’,’#’, …. ‘A’ , ‘B’, ...) ;

-Integer Range -2147483648 to 2147483648

2–Floating Point -Real has no meaning in synthesis so it is only used for simulation. Range -1.0E308 to 1.0E3083–Physical types Physical types represent measurements of some quantity such as time, length, resistance…



Data Types [Scalar] >>Boolean

Session Five 9

Boolean Type

Type Boolean is used in the conditional operationsBoolean ( false , true ) ;

Logical functions such as equality (=) and comparison (<) functions return a BOOLEAN value.Logical operators returns BOOLEAN if operands are also Boolean type.

Example

Evaluate the following relational expression: ”1011” < ”110”. Comment The expression evaluates to true.



Example 21

Session Five 10

entity ex_enum is Port ( inp1 : in STD_LOGIC; inp2 : in STD_LOGIC; outp1 : out Boolean; outp2 : out Character; outp3 : out string(1 to 5) );end ex_enum;

architecture Behavioral of ex_enum isBegin

outp1 <= ‘true’ when inp1 < inp2 else ‘false’ ;outp2 <= ‘t’ when inp1 < inp2 else ‘f’ ; outp3 <= “equal” when inp1=inp2 else “notEQ”;

end Behavioral;



Example 22

Session Five 11

Real

entity ex_enum is Port ( inp1 : in STD_LOGIC; inp2 : in STD_LOGIC; outp : out real );end ex_enum;

architecture Behavioral of ex_enum isBegin

outp<= 1.5 when inp1 < inp2 else 2.5; end Behavioral;



Data Types [Scalar] >>Integers

Session Five 12

Integers

integer range -2147483648 to 2147483648 ;-231 to 231

Example

Note

The implementation of the type integer in the synthesis and depends on the range specified by the user.

Subtypes natural and positive are predefined subtypes of integer.

Signal counter : integer range 0 to 15 ;

Subtype natural is integer range 0 to integer’high; Subtype positive is integer range 1 to integer’high;



Data Types [Scalar] >>Physical

Session Five 13

Predefined Physical Type

What about time, How it is represented inside VHDL

Notephysical types are not synthesizable

type time is range -2147483647 to 2147483647 Units

fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min;

end units;



Example 23

Session Five 14

Which Lines true ?

PROCESS (X) variable a: integer; variable b: integer range 0 to 15; type int is range -10 to 10; variable d: int; BEGIN

a := 1; b := -1; d := -12; a := 1.0;a := -1; b := 10; d := a;

END PROCESS;



Outline

Session Five 15


Modeling Memories




Data Types [Composite Types]

Session Five 16

-Refers to all types whose objects have a single value at any time instant. 1- Array types Multiple elements of the same type

a–Bit Vectorpredefined as 1D array type each element being of type bitIts size defined at declaration signal x : bit_vector(4 downto 0);

b–Stringif we need to write string of characters signal st : string(1 to 5);

2– Record types Multiple elements of the different types



Data Types [Composite] >>Array

Session Five 17

Group elements of same type.

Syntax

Example 1D Array

2D Array

Type <type_name> is array <range> of <data_type>;

type data is array (7 downto 0) of bit ;signal D_bus : data ;D_bus <= “10101010”;

.

.

.

012701

15Architecture type memory is array (0 to 15) of std_logic_vector(7 downto 0); signal word : memory ; ….Begin word (5) <= “10010110” ; word (15,4) <= ‘1’ ;



Data Types [Composite] >>Record

Session Five 18

Group elements of possibly different types Elements are indexed via field names

Syntax

Example Data Packet

type <type_name> is record identifier: type; identifier: type; …end record;

type packet is record ID : integer range 0 to 15 ; C : std_logic ; SOF : std_logic_vector(7 downto 0) ; PAYLOAD : std_logic_vector( 127 downto 0) ; CRC : std_logic_vector(3 downto 0) ; EOF : std_logic_vector(7 downto 0);

end record ;

signal tx_packet : packet;tx_packet.ID <= 3 ;tx_packet.PAYLOAD <= “1000..10101”;



Data Types Assigning values

Session Five 19

Here is summary of valid assigning values

type word is array (0 to 31) of std_logic; type byte is array (7 downto 0) of std_logic;type memory is array (0 to 15) of std_logic_vector(7 downto 0); Signal y : std_logic; Signal xv : std_logic _vector(7 downto 0); Signal D_bus : word; Signal mem1 : memory; Signal x : byte; ------ Y <= xv(4); Y <= ‘1’; mem1(5) <= "10010110" ; mem1(15,4) <= '1' ; y := x(5);



Outline

Session Five 20


Modeling Memories




Data Types [User defined Types]

Session Five 21

Types that are defined by default and to be defined by the user before using, such as encoding FSM next and present states.

Syntax

Most often used in the encoding of FSM states. When encoding the states of the FSM of the control unit in a microprocessor, one can define it as follows.

Type <type_name> is (value1, value2, )

Type states is (reset, fetch, decode, excute, store) Signal P_state : states;



Data Conversion

Session Five 22

VHDL is a strongly typed language, meaning that data objects of different types cannot be assigned to one another without the use of a type conversion function.

If A and B are both integer variables, the assignment

a := b + ‘1’ ; is illegal because ‘1’ is of type bit.

Example

SIGNAL a,b : IN integer; SIGNAL y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ... y <= CONV_STD_LOGIC_VECTOR ((a+b), 8); -- to change from integer to std_logic function conv_integer + rangea <=conv_integer(y); --to change from std_logic to integer



Outline

Session Five 23


Modeling Memories




Modeling Memories

Session Five 24

First we will think how to make a RAM unit, You may think that we need :

• Clock Source for Synchronization• Enable to control writing on memory• Enable to control reading from memory• Address to control which data to read or write• Input data• Output data

!LET’s DO THAT



Lab 06

Session Five 25

Title:RAM with separate read and write ports

Goal: Dealing with Memories Creating new project on Xilinx ISE Synthesis Reports on Xilinx ISE Simulation of Memories

Tutorial [2]Slides



Lab 06

Session Five 26

RAM with separate read and write ports

Assignment



Lab 06

Session Five 27

RAM with internal address control

Assignment



Lab 06

Session Five 28

Synchronous 16 * 8 ROM

Assignment



Session Five 29

Start Notes [Synthesis Notes]

Synthesizing data types

Integers used in care usually in constants. Also we use std_logic and std_logic_vector instead of bit and bit_vector and also we will use signed and unsigned only for internal calculations , Signals of User types translated into certain no. of bits.

Integers Precautions• IF not to be Unconstrained as synthesize tool create 32-bit

wide resources for them• Use in Constants.• Don’t use in interfaces

User defined data typesTranslated into certain no. of bits

Type sum is (may, june, july, august); -- May = “00”-- June = “01”-- July = “10”-- August = “11”



Outline

Session Five 30


Modeling Memories




Mini Project

Session Five 31

1) One purpose of scrambling is to reduce the length of strings of 0s or 1s in a transmitted signal, since a long string of 0s or 1s may cause transmission synchronization problems, i.e. cause the clock regeneration at the receiver more difficult.

2) Also for making the transmitted signal more secured.

ScramblerA(i) B(i)

B(i)=[A(i)+C(i)]mod2

A(i) : Input to the scrambler.

B(i) : Scrambled code word the Output of the scrambler

C(i) : Output of the Pseudo-random sequence generation



Mini Project

Session Five 32

Pseudo-random sequence generation

C(i) will be Xored with the input of the scrambler A(i) generating the scrambled output B(i)

In Communication expression XORing is defined as module-2

B(i)=[A(i)+C(i)]mod2



Mini Project

Session Five 33

- Required-VHDL code of this Scrambler-Verify functionality using Modelsim (Waveforms required)-Test Synthesizability using Xilinx ISE

-Utilization Summary from Output Report-Pattern Generated by MATLAB =

- Deadline-After Next session



Summary

Session Five 34

- Type declaration is made inside architecture declaration, entity declaration, process declaration- VHDL is a strongly typed language.- Data Types can be classified into:

1–Scalar types2–Composite types3–User defined types

Examples Exercises Labs

18-20 - 4-5



Time for Your Questions

Session Five 35



Download Session 02 Files

Session Five 36

Read Session- 2 Examples carefully to be ready for the next session’s LAB QUIZ

Lab 06 www.startgroup.weebly.com/vhdl-examples.html

Related Sessions

Tutorial 2

http://www.startgroup.weebly.com/vhdl-examples.html



Take Your NotesPrint the slides and take your notes here

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