session 03 v.3

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Session Three

Introduced by

Cairo-Egypt

Version 03 – June 20121


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about Start Group

2

Mahmoud AbdellatifAlaa Salah Shehata Mohamed SalahMohamed Talaat

[email protected] www.slideshare.net/StartGroup

www.facebook.com/groups/start.group www.startgroup.weebly.com [email protected]

+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011+ 02 0128-0090250 A.S

Session Three



Lab 02

Session Three 3

Title:Simulation of a Register on Modelsim

Goal: Be familiar with synchronous sequential circuits Solution of last session Assignment



Lab 02

Session Three 4

RegisterLibrary ieee; use ieee.std_logic_1164.all;Entity d_ff is Port( d, clk, rst : in std_logic; Q,Q_inv : out std_logic);end entity;Architecture behav of d_ff is Signal Q_sig : std_logic;Begin process(clk, rst) begin If (rst = '1') then Q_sig <= '0'; elsif rising_edge(clk) then

Q_sig <= d; end if; end process; Q <= Q_sig; Q_inv <= not Q_sig;end behav;

Register

D

clk

QReset

Q’



Outline

Session Three 5

Concurrent Statements1-Assign Statement 2-Process3-When-else4-With-select

Data Objects1-Signals2-Variables3-Constants

3



Outline

Session Three 6





VHDL Statements

Session Three 7

Statements

Concurrent

Assignment

Process

When-Else

With-Select

Sequential

IF

CASE

FOR

WAIT



Concurrency Concept

Session Three 8

We can consider any system to be consisted of many blocks each has a specific function and work together concurrently (in parallel) to form the whole function.

As VHDL is a Hardware Description Language so the default statements in VHDL are those who are executed in parallel.These statements are called Concurrent statements.

VHDL is concurrent by nature



Concurrent Statements [1-Assign <=]

Session Three 9

- Assignments relating outputs to inputs- Non Blocking Assignment <= is used - Assign statements can be written in any order.

In this Example, the value of x depends on a AND b, whenever a/b changes x will change accordingly

Similarly the value of y will always change whenever c/d changes

It might happen that the value of x changes at the same time the value of y changes -> Both changes happen concurrently

begin x <= a AND b; y <= c AND d; e <= x AND y; end rtl;

ab

cd

x

ye



Concurrent Statements [2-Process]

Session Three 10

Process allows writing sequential statements within concurrent environment

Process declaration

<Process Name> : PROCESS (sensitivity list) -- process declaration;

Begin -- sequential statements ;

End PROCESS <Process Name> ;

12

3

56

4

7

1 <Process Name> : Optional Label2 PROCESS : Keyword3 sensitivity list : Signals inside it when make an event, the process trigger4 process declaration5 Begin : Keyword 6 Sequential statements 7 End : Process Suspend



Connecting Processes

Session Three 11

Processes and other concurrent operations are seen to take place at the same point in discrete simulation time

a suspended process is activated when any of signal of sensitivity list changes.

If we have multiple process and all is activated then all statement is each process is executed sequentially .

all process in any architecture are executed concurrently with each other.

bc

a

Process 2b

c

a

Process 3

Process 1



Transactions and Events

Session Three 12

-Transaction occurs once a statement is read and executed during if condition -only one branch is transacted ‘the true condition

statements.-The current value of A,B is read and the process is begun .

C <= A AND B ; causes a transaction-The value in C is updated when the process suspend.-If the value of C is changed as a result of this transaction, an event occurs on this signal.

Process (enable,A,B) begin if enable =‘1‘ then C <= A AND B ; end if; end process ;

A B C

0 1 0

1 0 0

1 1 1

Transaction occurs when the process suspend on read and executed signalsEvent occurs on signal when the value changes on a transacted signal



Transactions and Events

Session Three 13

All signal assignment cause a transaction to be scheduled, but not every transaction will result in an event on the target signal.

NoteOnly an event on a given signal will cause a process to trigger if that signal is included in its sensitivity list.

1-Signal A =02-Signal B changes to 03-process triggers on signal B event4-Expression reevaluated5-Transaction scheduled logic 0 on C6-Process suspend7-Tranasction applied to C8-Value of C does not changed9-No event on C only Transaction

A

BC

Transaction applied at signal ‘C’

0

0



Example 13

Session Three 14

Find values of A,D and B after run simulation

Process (A,B) begin A <= B + C ; D <= B + E ; B <= F + G ; end process ;

Signal Value Stored

E 3

C 2

F 4

B 1

G 5Signal After first time this Process

Trigger for the first time

After Process Suspend

A 3 11

D 4 12

B 9 9



Concurrent Statements [3-When Else]

Session Three 15

– LHS can be an internal signal or an output port– RHS is an expression that operates on internal signal and/or input ports when

the branch condition is true– Last “else” branch covers all missing conditions

<target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition>

… else<expression> ;



Example 14

Session Three 16

4 x 1 Multiplexer

Architecture behave of mux_when isBegin

F <= a when sel = "00" elseb when sel = "01" elsec when sel = "10" elsed when sel = "11" else‘Z’;

-- This is one statement with semicolon at the end onlyEnd behave ;

A

Sel

FBCD



Concurrent Statements [4-With Select]

Session Three 17

– <select_signal> can be an internal signal or an input port– <target> can be an internal signal or an output port– <value> constants representing one of possible <select_signal> values.– “When others” is a must if not all values of <select_signal> are covered

With <select_signal> select <target> <= <expression> when <value>, <expression> when <value>, ….

< expression> when others;



Example 15

Session Three 18

4 x 1 Multiplexer

Architecture behave of mux_with isBegin

With sel selectF <= a when "00", b when "01", c when "10",

d when "10", ‘Z’ when others;

-- When Others needed to cover missing “sel” values

End behave ;

A

Sel

FBCD



Question !!

Session Three 19

What is the result in the two cases

Are the Same ?!!

Are the Same ?!!

Which SWAP ?!!

Process (B,C)begin A <= B ; A <= C ;end

A <= B ;A <= C ;

A <= D;B <= C;

B <= C;A <= D;

A <= B;C <= A;

Process (B,A)begin A <= B ; B <= A ;end

A <= B;B <= A;

Process (clk)begin

A <= B;C <= A;

end



Question !!

Session Three 20

What is the result in the two cases

Are the Same ?!!

Are the Same ?!!

Which SWAP ?!!

Process (B,C)begin A <= B ; A <= C ;end

A <= B ;A <= C ;

A <= D;B <= C;

B <= C;A <= D;

Process (clk)begin

A <= B;C <= A;

end

A <= B;C <= A;

Process (B,A)begin A <= B ; B <= A ;end

A <= B;B <= A;

Inside Process connected as registers A = last B

C = last AOutside Process wiring B=C

The Same

The First

1st : A = C2nd : Conflict



Lab 03

Session Three 21

Title:Simulate 2X4 Decoder or 4X2 Encoder Using When-else and With-Select-When Make the Code enabled by input ‘ENABLE’

Goal: Main Lab on Concurrent Statements



Lab 03

Session Three 22

WHEN-ELSE vs WITH SELECT WHEN

With <select_signal> select <target> <= <expression> when <value>, <expression> when <value>, ….

< expression> when others; ------------------------------------------------------------------------------------

<target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition> … else <expression> ;



Lab 03

Session Three 23

2X4 DecoderArchitecture behave of decoder2x4 is Begin

F <= "0001" when a = "00" else "0010" when a = "01" else "0100" when a = "10" else “1000" when a = "11" else “ZZZZ";

End behave ;---------------------------------------------

Architecture behave of decoder2x4 is Begin

With a select F <= "0001" when "00", "0010" when "01", “0100" when "10", “1000" when "11", “ZZZZ" when others;

End behave ;



Lab 03

Session Three 24

4X2 EncoderArchitecture behave of encoder4x2 is Begin

F <= “00" when a = “1000" else "01" when a = “0100" else "10" when a = “0010" else

"11" when a = “0001" else “ZZ";

End behave ; --------------------------------------------- Architecture behave of encoder4x2 is Begin

with A select F <= "00" when “1000", "01" when "0100", "10" when “0010", "11" when “0001", “ZZ" when others;

End behave ;



25

BreakBe ready for the 2nd part of this session

03:12 AM

15 minutes started from



Outline

Session Three 26





Data Objects

Session Three 27

-Data Objects are the Value holders -VHDL offers different data objects:

1-SignalsUsed to model connections

Signals can be:- External Signals- Internal Signals

2-VariablesUsed for computations

3-ConstantsUsed to store values that can’t be changed during synthesis or simulation time



Data Objects [1- Signals]

Session Three 28

Signals Used to model connections, signals can be divided into two main types :

External Signals (Ports)Used as an interface for the Entity to the outside world pass values in and out the circuit, between its internal units.Declared in EntityAll PORTS of an ENTITY are signals by default

Internal Signals Used inside the Architecture to connect different logic parts Declared in ArchitectureRepresents circuit interconnects (wires)




Session Three 29

External Signal declaration

Internal Signal declaration

entity <entity_name> isport ( <port_name> : <mode> <type>;

-----<port_name> : <mode> <type>

);End <entity_name> ;

ExampleENTITY AND_GATE IS

port ( a,b : in BIT; C : out BIT);

END ENTITY AND_GATE ;

architecture <arch_name> of <entity_name> is -- architecture declarations signal <sig_name> : <sig_type>;begin

---End <arch_name> ;

Example

SIGNAL control: BIT ;SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);




Session Three 30

Assignment OperatorAssigned using “<=”Non-Blocking Assignment

Example

BehaviorUsed in Concurrent or Sequential

- Outside a process its value is updated when their signal assignment is executed.- Inside a process its value is updated after the process suspends only last assignment to signal listed inside the process is effective .

inp_x <=“0000”; sig_1 <=‘1’;



Example 16

Session Three 31

Using Signals inside Process

A=1 ,B=1 ,C=1, D=2 ? C changes from 1 to 2 What is the values of A,B and C ?

----------------------------------Process (C,D) Begin

A <=2; B <=A+C; A <=D+1; C <=B+A;

End process;----------------------------------

Answer:A=3B=3C=2



Exercise 02

Session Three 32

Find the value of result

signalsignal1: integer :=1; -- initial value signalsignal2: integer :=2; -- initial value signalsignal3: integer :=3; -- initial value begin process() begin

signal1 <= signal2; signal2 <= signal1 + signal3; signal3 <= signal2; RESULT <= signal1 + signal2 + signal3;

end process;

Answer:6



Exercise 03

Session Three 33

All Signals have the uninitialized value ‘U’ Force A = '1' then force A='0' then A='1'

library IEEE; USE ieee.std_logic_1164.all; entity signal_lab is port( A: in std_logic ); End signal_lab;Architecture behave of signal_lab is Signal Z,G,F,X : STD_LOGIC; begin process (A) Begin

Z <= A; G <= '1'; F <= G; X <= F; G <= '0'; Z <= G;

end process ; end behave;

A 1 0 1

Z U 0 0

G 0 0 0

F U 0 0

X U U 0



Exercise 04

Session Three 34

All Signals have the uninitialized value ‘U’ Force A = '1' then force A='0' then A='1'

library IEEE; USE ieee.std_logic_1164.all; entity signal_lab is port( A: in std_logic ); End signal_lab;Architecture behave of signal_lab is Signal Z,G,F,X : STD_LOGIC; begin process (A) Begin

Z <= A; G <= '1'; F <= G; X <= F;

end process ; G <= '0'; Z <= G;

end behave;

A 1 0 1

Z X X X

G X X X

F U 0 0

X U U 0

Any statement written outside process is concurrent statement ,

It execute concurrently with process G and Z has two values at same time



Data Objects [2- Variables]

Session Three 35

Variables are used for computationsRepresent only local informationDeclared inside a processcan only be used inside a PROCESS (in sequential code).

Variable declaration

architecture behave of MPU is begin process()

variable x, y : std_logic ; variable intbus : std_logic_vector(7 downto 0);

begin . . .

end process ; . .

end behave;



Data Objects [2- Variables]

Session Three 36

Assignment OperatorAssigned using “:=”Blocking Assignment

Example

Behaviorits value can not be passed out directlyits update is immediate, so the new value is used in the next line of code.As long as signal and variable have same type they can be assign to each other .

var_x :=“0000”; var_1 :=‘1’;



Example 17

Session Three 37

Using Variables inside the process

A=1 ,B=1 ,C=1, D=2 ? C changes from 1 to 2 What is the values of A,B and C ?

----------------------------------Process (C,D) ….Begin

A :=2; B :=A+C; A :=D+1; C :=B+A;

End process;----------------------------------

Answer:A=3B=4C=7



Exercise 05

Session Three 38

Find Result value

begin

process() variable variable1: integer :=1; -- initial value variable variable2: integer :=2; -- initial value variable variable3: integer :=3; -- initial value

begin variable1 := variable2; variable2 := variable1 + variable3; variable3 := variable2; RESULT := variable1 + variable2 +

variable3; end process;

Answer:12



Exercise 06

Session Three 39

Force A = "0001" and find values of signals

-- Force A = “0001" library IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity signal_lab is port( A : in std_logic_vector(3 downto 0) ); End signal_lab;

Architecture behave of signal_lab is begin process (A) Variable Z,G,F,X : std_logic_vector(2 downto 0); Begin

G := A + A; F := G + A; X := G + F; Z := X + F;

end process ; end behave;

A 0001

G 0010

F 0011

X 0101

Z 0111



Data Objects [3-Constants]

Session Three 40

A constant can have a single value of a given type and cannot be changed during the simulation.

Constant Declaration

Constants can be declared at the start of an architecture and can then be used anywhere within the architecture.

Constants declared within a process can only be used inside this Process.

Example

CONSTANT set_bit : BIT := '1';

constant <con_name> : <data_type> := <con_value>;



Data Objects [Initialization]

Session Three 41

we make Initialization to values to start with a certain value instead of ‘U’ on the simulationwhen we declare the variable or the Signal using :=

signal sigbus : std_logic_vector(7 downto 0) := "01011110"; variable z : std_logic := '1'; variable varbus : std_logic_vector(3 downto 0) := "0001";



Signal vs Variable

Session Three 42

Signals Variables

Declaration Internal : Inside Architecture Declaration

Inside Process Declaration

External : Inside Port entity

Assignment Non-Blocking Assign <= Blocking Assign :=

Initialization := :=

Update After the process suspend Immediately

Scope Seen by the whole code

Can be used in either type of code, concurrent or sequential.

Local onside process

Can only be used inside a sequential code

UTILITY Represents circuit interconnects(wires)

Represents local informationNOT APPEAR on SIMULATION



Object Scope

Session Three 43

-Ports are signals and declared at the top level (entity)-Within the architecture, local signals are declared-Within the process, local variables can be declared

ENTITY…….

IN PORTS OUT PORTS

ARCHITECTURE…….

Signals

PROCESS…….

variables



Exercise 07

Session Three 44

Calculate the values of var1, sig1& Q

process (a,b) variable var1: integer;begin var1 := a + b; sig1 <= var1; Q <= sig1; end process;

Var1 sig1 Q

Intial values

3 4 6

A=2 B=3

5 5 4

A=5 B=2

7 7 5

Var1 sig1 Q

Intial values

3 4 6



Session Three 45

Start Notes [Synthesis Notes]

Combinational Process

Process is combinational if all the signals in your process are in the sensitivity list . Process that translate a combinational logic is for sure doesn’t include any clock signals.

Example of Combinational Process 4X1 MUX

process (a,b,c,d,sel) begin Case sel is When "00" =>

f <= a; When "01" =>

f <= b; When "10" =>

f <= c; When "11" =>

f <= d; when others =>

f <= ‘Z’; End case; End process;



Session Three 46

Start Notes [Synthesis Notes]

Signals Initialization

Signals inside your design should have initial valuesSynthesis tools ignore initial values specified for a variable or a signal in its declaration. The best way for initialization is to initialize the signals when the reset signal is active.

Initialization

If reset = 1 then sig_1 <= 0 ; sig_2 <= 00000; sig_3 <= 10101010; out_1 <= 00

elsif ris………..…



Session Three 47

Start Notes [Simulation Notes]

Modeling Concurrency

A VHDL simulator is event driven. More events occurs, more time your simulator runs. The event scheduler is the heart of the HDL behavioral environment.

- At any single point of discrete simulation time: (1) All processes execute until they suspend (2) Signals are updated (3) Events on signals cause more processes to resume executionThis is referred to as a delta cycle

Each transaction is scheduled at its appropriate discrete timeDiscrete time advances only when no more transactions are scheduled at the current time

998 999 1000 1001 1002

Simulation discrete time step

Concurrent Operations

Delta cycles in-between



Summary

Session Three 48

- VHDL is a Hardware Description Language so the default statements in VHDL are those who are executed in parallel

- External Signals describe interface while Internal Signals describe internal wiring . - Variables describe internal calculations inside a process.

Examples Exercises Labs

13-17 2-7 2-3



Time for Your Questions

Session Three 49



Download Session 02 Files

Session Three 50

Read Session- 3 Examples carefully to be ready for the next session’s LABs

Lab 02 www.startgroup.weebly.com/vhdl-examples.html

Lab 03 www.startgroup.weebly.com/vhdl-examples.html

http://www.startgroup.weebly.com/vhdl-examples.html

http://www.startgroup.weebly.com/vhdl-examples.html



Take Your NotesPrint the slides and take your notes here

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See You Next Session .. Don’t miss

Thank

You

session 03 v.3

Technology

level q

level fourthg

allentity d

clksignal q

master text stylestitle

ff isreset register

levelarchitecture behav

salah mohamed talaat