section 6. parallel input/output (i/o) ports

M68HC11E Family — Rev. 2.0 Technical Data

MOTOROLA Parallel Input/Output (I/O) Ports 131

Technical Data — M68HC11E Family�

Section 6. Parallel Input/Output (I/O) Ports

6.1 Contents

6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

6.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

6.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

6.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

6.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

6.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

6.8 Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

6.9 Parallel I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .139

6.2 Introduction

All�

M68HC11 E-series MCUs have five input/output (I/O) ports and up to38 I/O lines, depending on the operating mode. Refer to Table 6-1 for asummary of the ports and their shared functions.

T�

able 6-1. Input/Output P orts

PortInput�Pins

Output�

PinsBidirectional

PinsShared Functions�

Port A 3 3 2 Timer

Port B — 8 — High-order address

Port C — — 8 Low-order address and data bus

Port D — — 6Ser�

ial communications interface(SCI) and serial peripheral interface(SPI)

Port E 8 — — Analog-to-digital (A/D) converter

T�echnical Data M68HC11E Family — Rev. 2.0

132 Parallel Input/Output (I/O) Ports MOTOROLA

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Port pin function is mode dependent. Do not confuse pin function withthe electrical state of the pin at reset. Port pins are either driven to a-specified logic level or are configured as high-impedance inputs. I/O pinsconfigured as high-impedance inputs have port data that isindeterminate.

The contents of the corresponding latches are dependent upon the.electrical state of the pins during reset. In port descriptions, an I indicatesthis-

condition. Port pins that are driven to a known logic level during resetare shown with a value of either 1 or 0. Some control bits are unaffectedby reset. Reset states for these bits are indicated with a U.

6.3 Port A

Port A shares functions with the timer system and has:

• Three input-only pins

• Three output-only pins

• Two bidirectional I/O pins

/10204365478789;:2<4=4=2=>@? A&B C D E F G < >@? A&=

HI54J4029 K /1B K /1C K /1D K /1E K /1F K /1G K /1< K /1=LM3N? A'529HI54785 A'9 O = = = O O O O/1P A'523NQ4JRA'5ISUT4Q4V�A'? W4Q29 K /1O X(YIG X(YIF X(YIE O YIE Z'X(YID O YI< O YIG O YIF

/1Q40RZ'W4369 X(YI< X(YI< X(YI< X(YI< X(YI< [ [ [O4\]YIW4Q A'52Q A'7(WRS4A'^45_V8W4363N527a`2W4Q402? Q2bcP J AUVa^2547(J4365c0254`452Q40452Q A&T2`4W4QdA'^45_54P 54V�A'36? VaJ2P87UAUJ A'5_W S4A'^25c`2? Q27(04T436? Q4bc3654785RA'e

Figure 6-1. Port A Data Register (PORTA)

Parallel Input/Output (I/O) PortsPort A



DDRA7 — Data Direction for Port A Bit 7

Overridden if an output compare function is configured to control thePA7 pin

0 = Input1 = Output

The pulse accumulator uses port A bit 7 as the PAI input, but the pincan also be used as general-purpose I/O or as an output compare.

NOTE: Even when port A bit 7 is configured as an output, the pin still drives theinput to the pulse accumulator.

PAEN — Pulse Accumulator System Enable Bit

Refer to Section 9. Timing System .

PAMOD — Pulse Accumulator Mode Bit


PEDGE — Pulse Accumulator Edge Control Bit



This bit is overridden if an output compare function is configured tocontrol the PA3 pin.

0 = Input1 = Output

I4/O5 — Input Capture 4/Output Compare 5 Bit


RTR[1:0] — RTI Interrupt Rate Select Bits


/10204365478789;:2<4=4G2C>@? A&B C D E F G < >@? A&=

HI54J4029gfhf Hi/1B K /1j2Llk K /1m_X f K j fhn j fhf Hi/1F O E Z'X(D HiopHI< HiopHI=LM3N? A'529HI54785 AU9 = = = = = = = =Figure 6-2. Pulse Accumulator Control Register (PACTL)



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6.4 Port Bq

In single-chip or bootstrap modes, port B pins are general-purposeoutputs. In expanded or special test modes, port B pins are high-orderaddress outputs.

6.5 Port C

In single-chip and bootstrap modes, port C pins reset to high-impedanceinputs. (DDRC bits are set to 0.) In expanded and special test modes,port C pins are multiplexed address/data bus and the port C registeraddress is treated as an external memory location.

/10204365478789;:2<4=4=2E>@? A&B C D E F G < >@? A&=

r ? Q4b2P 52sNV8^4? `_W43ut4W4WRA'7�A'3NJ2`cv_W40452789HI54J4029 K >@B K >@C K >@D K >@E K >@F K >@G K >@< K >@=LM3N? A'529HI54785 AU9 = = = = = = = =

j2w#`2J4Q402540cW23#78`254V8? J2P�A'547�A&v_W40452789HI54J4029 / fhf HI<4Dx/ fhf HI<4Ex/ fIf HI<4Fx/ fIf HI<4Gx/ fIf HI<4<x/ fIf HI<4= / fIf HIy / fIf HIzLM3N? A'529HI54785 AU9 = = = = = = = =

Figure 6-3. Port B Data Register (PORTB)

/10204365478789;:2<4=4=2F>@? A&B C D E F G < >@? A&=

r ? Q4b2P 52sNV8^4? `_W43ut4W4WRA'7�A'3NJ2`cv_W40452789HI54J4029 K YhB K YhC K YhD K YhE K YhF K YhG K Yh< K Yh=LM3N? A'529HI54785 AU9 O O O O O O O O

j2w#`2J4Q402540cW23#78`254V8? J2P�A'547�A&v_W40452789HI54J4029 / fIf HIBf /@ou/1B / fIf HICf /@ou/1C / fIf HIDf /@ou/1D / fIf HIEf /@ou/1E / fIf HIFf /@ou/1F / fIf HIGf /@ou/1G / fIf HI<f /@ou/1< / fIf HI=f /@ou/1=LM3N? A'529HI54785 AU9 O O O O O O O O

O4\]YIW4Q AU54Q A'7(WRS4A'^25cV8W4363N5278`4W4Q204? Q4bcP J AUV8^4547(J23N5_0454`254Q40254Q A@T4`4W2QIA'^25c54P 54V�A'36? V8J4P87�A'J A'5_W S4AU^45c`2? Q27(04T23N? Q4b_3N54785RA'eFigure 6-4. Port C Data Register (PORTC)

Parallel Input/Output (I/O) PortsPort C



PORTCL is used in the handshake clearing mechanism. When an activeedge occurs on the STRA pin, port C data is latched into the PORTCLregister. Reads of this register return the last value latched into PORTCLand clear STAF flag (following a read of PIOC with STAF set).

DDRC[7:0] — Port C Data Direction Bits

In handshake output mode, DDRC bits select the 3-stated outputoption (DDCx = 1).

0 = Input1 = Output

/10204365478789;:2<4=4=2D>@? A&B C D E F G < >@? A&=

HI54J4029 K YI{4B K Yh{4C K YI{4D K Yh{4E K Yh{2F K Yh{4G K Yh{2< K Yh{2=LM3N? A'529HI54785 AU9 O O O O O O O O

O4\]YIW4Q AU54Q A'7(WRS4A'^25cV8W4363N5278`4W4Q204? Q4bcP JRA'V8^4547(J23N5_0454`254Q40254Q A@T4`4W2QIA'^25c54P 54V�A'36? V8J4P87�A'J A'5_W S4AU^45c`2? Q47(04T23N? Q4b_3N54785RA'eFigure 6-5. Port C Latched Register (PORTCL)

/10204365478789;:2<4=4=2B>@? A&B C D E F G < >@? A&=

HI54J4029 fhf HhYIB fhf HhYIC fhf HhYID fhf HhYIE fhf HhYIF fhf HhYIG fhf HhYI< fhf HhYI=LM3N? A'529HI54785 AU9 = = = = = = = =

Figure 6-6. Port C Data Direction Register (DDRC)



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6.6 Port Dq

In all modes, port D bits [5:0] can be used either for general-purpose I/Oor with the serial communications interface (SCI) and serial peripheralinterface (SPI) subsystems. During reset, port D pins PD[5:0] areconfigured as high-impedance inputs (DDRD bits cleared).

Bits [7:6] — Unimplemented

Always read 0�

DDRD[5:0] — Port D Data Direction Bits

When DDRD bit 5 is 1 and MSTR = 1 in SPCR, PD5/SS is ageneral-purpose output and mode fault logic is disabled.

0 = Input1 = Output

/10204365478789;:2<4=4=2z>@? A&B C D E F G < >@? A&=

HI54J4029 = = K f D K f E K f F K f G K f < K f =LM3N? A'529HI54785RA'9 [ [ O O O O O O

/1P A'5436Q4J A'5_|uT4Q4V�A'? W4Q29 [ [K f Dr@r

K f Er YI}K f Fm_X r O

K f Gm_O r XK f <o#w

K f =Huw fO4\]YIW4Q A'52Q A'7(WRS4A'^45_V8W4363N527a`2W4Q402? Q2bcP J AUVa^2547(J4365c0254`452Q40452Q A&T2`4W4QdA'^45_54P 54V�A'36? VaJ2P87UAUJ A'5_W S4A'^25c`2? Q27(04T436? Q4bc3654785 AUe

Figure 6-7. Port D Data Register (PORTD)

/10204365478789;:2<4=4=2y>@? A&B C D E F G < >@? A&=

HI54J4029 fhf H f D fhf H f E fhf H f F fhf H f G fhf H f < fhf H f =LM3N? A'529HI54785RA'9 = = = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 6-8. Port D Data Direction Register (DDRD)

Parallel Input/Output (I/O) PortsPort E



6.7 Port E

Port E is used for general-purpose static inputs or pins that sharefunctions�

with the analog-to-digital (A/D) converter system. When someport E pins are being used for general-purpose input and others arebeing used as A/D inputs, PORTE should not be read during the sampleportion of an A/D conversion.

6.8 Handshake Protocol

Simple and full handshake input and output functions are available onports B and C pins in single-chip mode. In simple strobed mode, port Bis a strobed output port and port C is a latching input port. The twoactivities are available simultaneously.

The.

STRB output is pulsed for two E-clock periods each time there is awrite to the PORTB register. The INVB bit in the PIOC register controlsthe-

polarity of STRB pulses. Port C levels are latched into the alternateport C latch (PORTCL) register on each assertion of the STRA input.STRA edge select, flag, and interrupt enable bits are located in the PIOCregister. Any or all of the port C lines can still be used asgeneral-purpose I/O while in strobed input mode.

/10204365478789�:4<2=4= />@? A&B C D E F G < >@? A&=

HI54J4029 K j@B K j@C K j@D K j@E K j@F K j@G K j@< K j@=LM3N? A'529HI54785 AU9 O O O O O O O O

/1P A'5436Q4J A'5_|uT4Q4V�A'? W4Q29 /1khB /1khC /1khD /1khE /1khF /1khG /1kh< /1kh=O4\]YIW4Q A'52Q A'7(WRS4A'^45_V8W4363N527a`2W4Q402? Q2bcP J AUVa^2547(J4365c0254`452Q40452Q A&T2`4W4QdA'^45_54P 54V�A'36? VaJ2P87UAUJ A'5_W S4A'^25c`2? Q27(04T436? Q4bc3654785RA'e

Figure 6-9. Port E Data Register (PORTE)



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Full handshake modes use port C pins and the STRA and STRB lines.Input and output handshake modes are supported, and outputhandshake mode has a 3-stated variation. STRA is an edge-detectinginput and STRB is a handshake output. Control and enable bits arelocated in the PIOC register.

In full input handshake mode, the MCU asserts STRB to signal anexternal system that it is ready to latch data. Port C logic levels arelatched into PORTCL when the STRA line is asserted by the externalsystem. The MCU then negates STRB. The MCU reasserts STRB afterthe-

PORTCL register is read. In this mode, a mix of latched inputs, staticinputs, and static outputs is allowed on port C, differentiated by the datadirection bits and use of the PORTC and PORTCL registers.

In full output handshake mode, the MCU writes data to PORTCL which,in turn, asserts the STRB output to indicate that data is ready. Theexternal system reads port C data and asserts the STRA input toacknowledge that data has been received.

In the 3-state variation of output handshake mode, lines intended as3-state handshake outputs are configured as inputs by clearing thecorresponding DDRC bits. The MCU writes data to PORTCL and assertsSTRB. The external system responds by activating the STRA input,which forces the MCU to drive the data in PORTC out on all of the portC lines. After the trailing edge of the active signal on STRA, the MCUnegates the STRB signal. The 3-state mode variation does not allow partof port C to be used for static inputs while other port C pins are beingused for handshake outputs. Refer to the 6.9 Parallel I/O ControlRegister for further information.

Parallel Input/Output (I/O) PortsParallel I/O Control Register



6.9 Parallel I/O Control Register

The parallel handshake functions are available only in the single-chipoperating mode. PIOC is a read/write register except for bit 7, which isread only. Table 6-2 shows a summary of handshake operations.

STAF — Strobe A Interrupt Status Flag

STAF is set when the selected edge occurs on strobe A. This bit canbe cleared by a read of PIOC with STAF set followed by a read ofPORTCL (simple strobed or full input handshake mode) or a write toPORTCL (output handshake mode).

0 = No edge on strobe A1 = Selected edge on strobe A

STAI — Strobe A Interrupt Enable Mask Bit0 = STAF does not request interrupt1 = STAF requests interrupt

CWOM — Port C Wired-OR Mode Bit (affects all eight port C pins)

It is customary to have an external pullup resistor on lines that aredriven by open-drain devices.

0 = Port C outputs are normal CMOS outputs.1 = Port C outputs are open-drain outputs.

HNDS — Handshake Mode Bit0 = Simple strobe mode1 = Full input or output handshake mode

/10204365478789;:2<4=4=2G>@? A&B C D E F G < >@? A&=

HI54J4029 r ou/1| r o#/1O YiLMX(m �Ik f r X(O k K { r j n / O kI�@>LM3N? A'529HI54785 AU9 = = = = = ~ < <

~�\]~hQ2J S S'52VUAU540Figure 6-10. Parallel I/O Control Register (PIOC)



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OIN — Output or Input Handshake Select Bit

HNDS must be set to 1 for this bit to have meaning.0 = Input handshake1 = Output handshake

PLS — Pulsed/Interlocked Handshake Operation Bit

HNDS must be set to 1 for this bit to have meaning. When interlockedhandshake is selected, strobe B is active until the selected edge ofstrobe A is detected.

0 = Interlocked handshake1 = Pulsed handshake (Strobe B pulses high for two E-clock

cycles.)

EGA — Active Edge for Strobe A Bit0 = STRA falling edge selected, high level activates port C outputs

(output handshake)1 = STRA rising edge selected, low level activates port C outputs

(output handshake)

INVB — Invert Strobe B Bit0 = Active level is logic 0.1 = Active level is logic 1.

Parallel Input/Output (I/O) PortsParallel I/O Control Register



Table 6-2. Parallel I/O Contr ol

STAF�

Clearing�

Sequence� HNDS

�OIN PLS EGA Port B Port C

Simple�strobed�mode

ReadPIOC withST�

AF = 1then read�PORTCL

0 X�

X

Inputs latchedinto PORTCL onan� y active edgeon STRA�

STRB pulses�on wr� itesto POR�

TB

Full-inputhand-shak� emode

ReadPIOC withST�

AF = 1then read�PORTCL

1 0

0 = STRB�activ� e level

1 = STRBactiv� e pulse

Inputs latchedinto PORTCL onan� y active edgeon STRA�

Normal outputpor� t,unaff� ected inhandshakemodes

Full-output�hand-shak� emode

ReadPIOC withST�

AF = 1then wr�

itePORTCL

1 1

0 = STRB�activ� e level

1 = STRBactiv� e pulse

Driven as outputsif STRA at activelevel; followsDDRCif STRA not atactiv� e level

Normal outputpor� t,unaff� ected inhandshakemodes

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MOTOROLA Serial Communications Interface (SCI) 143


Section 7. Serial Communications Interface (SCI)

7.1 Contents

7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

7.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

7.4 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

7.5 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

7.6 Wakeup Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1467.6.1 Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1487.6.2 Address-Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . .148

7.7 SCI Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

7.8 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1507.8.1 Serial Communications Data Register . . . . . . . . . . . . . . . .1507.8.2 Serial Communications Control Register 1 . . . . . . . . . . . .1517.8.3 Serial Communications Control Register 2 . . . . . . . . . . . .1527.8.4 Serial Communication Status Register. . . . . . . . . . . . . . . .1537.8.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

7.9 Status Flags and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .158

7.10 Receiver Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

7.2 Introduction

The.

serial communications interface (SCI) is a universal asynchronousreceiver transmitter (UART), one of two independent serial input/output(I/O) subsystems in the M68HC11 E series of microcontrollers. It has astandard non-return-to-zero (NRZ) format (one start bit , eight or ninedata bits, and one stop bit). Several baud rates are available. The SCI


144 Serial Communications Interface (SCI) MOTOROLA

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transmitter-

and receiver are independent, but use the same data formatand bit rate.

All members of the E series contain the same SCI, with one exception.The SCI system in the MC68HC11E20 and MC68HC711E20 MCUs.have an enhanced SCI baud rate generator. A divide-by-39 stage hasbeen added that is enabled by an extra bit in the BAUD register. Thisincreases the available SCI baud rate selections. Refer to Figure 7-8and 7.8.5 Baud Rate Register .

7.3 Data Format

The serial data format requires these conditions:

1. An idle line in the high state before transmission or reception of amessage

2. A start bit, logic 0, transmitted or received, that indicates the startof each character

3. Data that is transmitted and received least significant bit (LSB) first

4. A stop bit, logic 1, used to indicate the end of a frame. A frameconsists of a start bit, a character of eight or nine data bits, and astop bit.

5. A break, defined as the transmission or reception of a logic 0 forsome multiple number of frames

Selection of the word length is controlled by the M bit of SCI controlregister (SCCR1).

7.4 Transmit Operation

The SCI transmitter includes a parallel transmit data register (SCDR).and a serial shift register. The contents of the serial shift register can bewritten´ only through the SCDR. This double buffered operation allows acharacter to be shifted out serially while another character is waiting inthe-

SCDR to be transferred into the serial shift register. The output of theserial shift register is applied to TxD as long as transmission is in

Serial Communications Interface (SCI)�

Transmit Operation



progress or the transmit enable (TE) bit of serial communication controlregister 2 (SCCR2) is set. The block diagram, Figure 7-1 , shows thetransmit serial shift register and the buffer logic at the top of the figure.-

Figure 7-1. SCI Transmitter Block Diagram

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Note: Refer to Figure B-1. EVBU Schematic Diagram for an example of connecting TxD to a PC.



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7.5 Receive Operation�

During receive operations, the transmit sequence is reversed. The serialshift register receives data and transfers it to a parallel receive dataregister (SCDR) as a complete word. This double buffered operationallows a character to be shifted in serially while another character isalready in the SCDR. An advanced data recovery scheme distinguishesvalid data from noise in the serial data stream. The data input is�selectively sampled to detect receive data, and a majority voting circuitdetermines the value and integrity of each bit. See Figure 7-2 .

7.6 Wakeup Feature

The wakeup feature reduces SCI service overhead in multiple receiversystems. Software for each receiver evaluates the first character of eachmessage. The receiver is placed in wakeup mode by writing a 1 to theRWU bit in the SCCR2 register. While RWU is 1, all of thereceiver-related status flags (RDRF, IDLE, OR, NF, and FE) areinhibited (cannot become set). Although RWU can be cleared by asoftware write to SCCR2, to do so would be unusual. Normally, RWU isset by software and is cleared automatically with hardware. Whenever anew message begins, logic alerts the sleeping receivers to wake up andevaluate the initial character of the new message.

Two methods of wakeup are available:.

• Idle-line wakeup

• Address-mark wakeup

During idle-line wakeup, a sleeping receiver awakens as soon as theRxD line becomes idle. In the address-mark wakeup, logic 1 in the mostsignificant bit (MSB) of a character wakes up all sleeping receivers.


Wakeup Feature



Figure 7-2. SCI Receiver Block Diagram

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Figure B-1. EVBU Schematic Diagram for an example of connecting RxD to a PC.



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7.6.1 Idle-Line Wakeup

To use the receiver wakeup method, establish a software addressing.scheme to allow the transmitting devices to direct a message toindividual receivers or to groups of receivers. This addressing schemecan take any form as long as all transmitting and receiving devices areprogrammed to understand the same scheme. Because the addressinginformation is usually the first frame(s) in a message, receivers that arenot part of the current task do not become burdened with the entire setof addressing frames. All receivers are awake (RWU = 0) when eachmessage begins. As soon as a receiver determines that the message isnot intended for it, software sets the RWU bit (RWU = 1), which inhibitsfurther flag setting until the RxD line goes idle at the end of the message.As soon as an idle line is detected by receiver logic, hardware�automatically clears the RWU bit so that the first frame of the nextmessage can be received. This type of receiver wakeup requires aminimum of one idle-line frame time between messages and no idle timebetween frames in a message.

7.6.2 Address-Mark Wakeup

The serial characters in this type of wakeup consist of seven (eight ifM = 1) information bits and an MSB, which indicates an addresscharacter (when set to 1, or mark). The first character of each messageis an addressing character (MSB = 1). All receivers in the systemevaluate this character to determine if the remainder of the message isdirected toward this particular receiver. As soon as a receiverdetermines that a message is not intended for it, the receiver activatesthe-

RWU function by using a software write to set the RWU bit. Becausesetting RWU inhibits receiver-related flags, there is no further softwareoverhead for the rest of this message.

When the next message begins, its first character has its MSB set, whichautomatically clears the RWU bit and enables normal characterreception. The first character whose MSB is set is also the first characterto-

be received after wakeup because RWU gets cleared before the stopbit for that frame is serially received. This type of wakeup allowsmessages to include gaps of idle time, unlike the idle-line method, but


SCI Error Detection�



there is a loss of efficiency because of the extra bit time for each-character (address bit) required for all characters.

7.7 SCI Error Detection

Three error conditions – SCDR overrun, received bit noise, andframing – can occur during generation of SCI system interrupts. Threebits (OR, NF, and FE) in the serial communications status register(SCSR) indicate if one of these error conditions exists.

The overrun error (OR) bit is set when the next byte is ready to be.transferred-

from the receive shift register to the SCDR and the SCDR isalready full (RDRF bit is set). When an overrun error occurs, the datathat-

caused the overrun is lost and the data that was already in SCDR isnot disturbed. The OR is cleared when the SCSR is read (with OR set),followed by a read of the SCDR.�The noise flag (NF) bit is set if there is noise on any of the received bits,including the start and stop bits. The NF bit is not set until the RDRF flagis set. The NF bit is cleared when the SCSR is read (with FE equal to 1)followed by a read of the SCDR.

When no stop bit is detected in the received data character, the framingerror (FE) bit is set. FE is set at the same time as the RDRF. If the bytereceived causes both framing and overrun errors, the processor onlyrecognizes the overrun error. The framing error flag inhibits furthertransfer of data into the SCDR until it is cleared. The FE bit is cleared-when the SCSR is read (with FE equal to 1) followed by a read of the´SCDR.



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7.8 SCI Registers�

Five addressable registers are associated with the SCI:

• Four control and status registers:

– Serial communications control register 1 (SCCR1)

– Serial communications control register 2 (SCCR2)

– Baud rate register (BAUD)

– Serial communications status register (SCSR)

• One data register:

– Serial communications data register (SCDR)

The SCI registers are the same for all M68HC11 E-series devices with.one exception. The SCI system for MC68HC(7)11E20 contains an extrabit in the BAUD register that provides a greater selection of baudprescaler rates. Refer to 7.8.5 Baud Rate Register , Figure 7-8 , andFigure 7-9 .

7.8.1 Serial Communications Data Register

SCDR is a parallel register that performs two functions:

• The receive data register when it is read

• The transmit data register when it is written

Reads access the receive data buffer and writes access the transmitdata buffer. Receive and transmit are double buffered.

/10204365478789 :4<2=4G4|>@? A&B C D E F G < >@? A&=

HI54J4029 HIB Z opB HhC Z opC HID Z opD HIE Z opE HhF Z opF HhG Z opG Hh<RZ op< Hh= Z op=LM3N? A'529HI54785RA'9 O O O O O O O O

O4\]YIW4Q AU54Q A'7(WRS4A'^25cV8W4363N5278`4W4Q204? Q4bcP JRA'V8^4547(J23N5_0454`254Q40254Q A@T4`4W2QIA'^25c54P 54V�A'36? V8J4P87�A'J A'5_W S4AU^45c`2? Q47(04T23N? Q4b_3N54785RA'eFigure 7-3. Serial Communications Data Register (SCDR)


SCI Registers�



7.8.2 Serial Communications Control Register 1

The.

SCCR1 register provides the control bits that determine word lengthand select the method used for the wakeup feature.

R8 — Receive Data Bit 8

If M bit is set, R8 stores the ninth bit in the receive data character.

T8 — Transmit Data Bit 8

If M bit is set, T8 stores the ninth bit in the transmit data character.

Bit 5 — Unimplemented

Always reads 0

M — Mode Bit (select character format)1 = Start bit, 8 data bits, 1 stop bit1 = Start bit, 9 data bits, 1 stop bit

WAKE — Wakeup by Address Mark/Idle Bit0 = Wakeup by IDLE line recognition1 = Wakeup by address mark (most significant data bit set)


Always read 0

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HI54J4029 HIz opz m L /1}@jLM3N? A'529HI54785RA'9 O O = = = = = =

O2\ YIW4Q AU54Q A'7(WRS4A'^25cV8W4363N5278`4W4Q204? Q4bcP JRA'V8^4547(J23N5_0454`254Q40254Q A@T4`4W2QIA'^25c54P 54V�A'36? V8J4P87�A'J A'5_W S4AU^45c`2? Q47(04T23N? Q4b_3N54785RA'e\]~hQ2? v_`4P 54v_54Q A'520

Figure 7-4. Serial Communications Control Register 1 (SCCR1)



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7.8.3 Serial Communications Control Register 2

The SCCR2 register provides the control bits that enable or disable.individual SCI functions.

TIE — Transmit Interrupt Enable Bit0 = TDRE interrupts disabled1 = SCI interrupt requested when TDRE status flag is set

TCIE — Transmit Complete Interrupt Enable Bit0 = TC interrupts disabled1 = SCI interrupt requested when TC status flag is set

RIE — Receiver Interrupt Enable Bit0 = RDRF and OR interrupts disabled1 = SCI interrupt requested when RDRF flag or the OR status flag

is set

ILIE — Idle-Line Interrupt Enable Bit0 = IDLE interrupts disabled1 = SCI interrupt requested when IDLE status flag is set

TE — Transmitter Enable Bit

When TE goes from 0 to 1, one unit of idle character time (logic 1) isqueued as a preamble.

0 = Transmitter disabled1 = Transmitter enabled

RE — Receiver Enable Bit0 = Receiver disabled1 = Receiver enabled

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HI54J4029 ohO j ohYhO j HhO j O {2O j ohj Hhj HuLl~ r >@}LM3N? A'529HI54785 AU9 = = = = = = = =Figure 7-5. Serial Communications Control Register 2 (SCCR2)


SCI Registers�



RWU — Receiver Wakeup Control Bit0 = Normal SCI receiver1 = Wakeup enabled and receiver interrupts inhibited

SBK — Send Break

At least one character time of break is queued and sent each timeSBK is written to 1. As long as the SBK bit is set, break characters arequeued and sent. More than one break may be sent if the transmitteris idle at the time the SBK bit is toggled on and off, as the baud rateclock edge could occur between writing the 1 and writing the 0 to SBK.

0 = Break generator off1 = Break codes generated

7.8.4 Serial Communication Status Register

The.

SCSR provides inputs to the interrupt logic circuits for generation ofthe SCI system interrupt.-

TDRE — Transmit Data Register Empty Flag

This.

flag is set when SCDR is empty. Clear the TDRE flag by readingSCSR with TDRE set and then writing to SCDR.

0 = SCDR busy0 = SCDR empty

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HI54J4029 o f Hhj ohY H f HI| O f {4j X(H kh| |ujLM3N? A'529HI54785RA'9 < < = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 7-6. Serial Communications Status Register (SCSR)



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TC — Transmit Complete Flag.

This flag is set when the transmitter is idle (no data, preamble, orbreak transmission in progress). Clear the TC flag by reading SCSRwith TC set and then writing to SCDR.

0 = Transmitter busy1 = Transmitter idle

RDRF — Receive Data Register Full Flag

This.

flag is set if a received character is ready to be read from SCDR.Clear the RDRF flag by reading SCSR with RDRF set and thenreading SCDR.

0 = SCDR empty1 = SCDR full

IDLE — Idle Line Detected Flag

This flag is set if the RxD line is idle. Once cleared, IDLE is not setagain until the RxD line has been active and becomes idle again. TheIDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSRwith IDLE set and then reading SCDR.´

0 = RxD line active1 = RxD line idle

OR — Overrun Error Flag

OR is set if a new character is received before a previously receivedcharacter is read from SCDR. Clear the OR flag by reading SCSRwith OR set and then reading SCDR.

0 = No overrun1 = Overrun detected

NF — Noise Error Flag

NF is set if majority sample logic detects anything other than aunanimous decision. Clear NF by reading SCSR with NF set and thenreading SCDR.

0 = Unanimous decision1 = Noise detected


SCI Registers�



FE — Framing Error Flag

FE is set when a 0 is detected where a stop bit was expected. Clearthe FE flag by reading SCSR with FE set and then reading SCDR.-

0 = Stop bit detected1 = Zero detected


Always reads 0

7.8.5 Baud Rate Register

Use this register to select different baud rates for the SCI system. TheSCP[1:0] (SCP[2:0] in MC68HC(7)11E20) bits function as a prescaler forthe SCR[2:0] bits. Together, these five bits provide multiple baud rate-combinations for a given crystal frequency. Normally, this register iswritten´ once during initialization. The prescaler is set to its fastest rate bydefault out of reset and can be changed at any time. Refer to Table 7-1for normal baud rate selections.�

TCLR — Clear Baud Rate Counter Bit (Test).SCP[2:0] — SCI Baud Rate Prescaler Select Bits

NOTE: SCP2 applies to MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0]must equal 0s. Any other values for SCP[1:0] are not decoded in theprescaler and the results are unpredictable. Refer toU Figure 7-8 andFigure 7-9.

/10204365478789�:4<2=4G4>>@? A&B C D E F G < >@? A&=

HI54J4029 ohYh{4H r Y K G r Y K < r Y K = HIYh}Ë> r YIHhG r YIHh< r YIHh=LM3N? A'529HI54785 AU9 = = = = = ~ ~ ~

~�\]~hQ2J S S'52VUAU540Figure 7-7. Baud Rate Register (BAUD)



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Table 7-1. Baud Rate V alues

PrescaleDivide

BaudSet�

Divide

Crystal Frequency (MHz)�

4.00V

4.9152 8.00 10.00 12.00 16.00

Prescaler Selects Bus Frequency (MHz)

SCP2�

SCP1 SCP0 SCR2 SCR1 SCR0 1.00 1.23 2.00 2.50 3.00 4.00

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0�10�10�10�1

11111111

124W8X1632Y64Z128

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7680038400Y192009600[48002400\1200600Z

12500062500Z31250Y1562578133906Y1953977[

1562507812539063Y195319766[4883W24411221

18750093750[46875W23438117195859]29301465

25000012500062500Z31250Y156257813^3906Y1953

0�0�0�0�0�0�0�0�

0�0�0�0�0�0�0�0�

11111111

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0�10�10�10�1

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25600\128006400Z3200Y1600800X400W200

41667W20833104175208]26041302651Z326Y

52083]26042130216510Z3255Y1628814X407

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83333X4166720833\104175208]2604\1302651Z

0�0�0�0�0�0�0�0�

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4W444W444W4

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11111111

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1313131313131313

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120196010Z3005Y1502751^376Y18894[

144237212^3606Y1803901[451225113

192319615[480824041202601Z300Y150

11111111

0�0�0�0�0�0�0�0�

0�0�0�0�0�0�0�0�

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3205Y1603801X401200\10050]25\

40062003\1002501]250\12563Z31Y

48082404\1202601Z300Y1507538Y

6410Z3205Y1603801X401W200\10050]

Shaded areas reflect standard baud rates._On MC68HC(7)11E20 do not set SCP1 or SCP0 when SCP2 is 1.`


SCI Registers�



RCKB — SCI Baud Rate Clock Check Bit (Test)

SCR[2:0] — SCI Baud Rate Select Bits

Selects receiver and transmitter bit rate based on output from baudrate prescaler stage. Refer to Figure 7-8 and Figure 7-9 .

The prescaler bits, SCP[2:0], determine the highest baud rate, and.the-

SCR[2:0] bits select an additional binary submultiple (÷a 1, ÷a 2, ÷a 4,through-

÷128) of this highest baud rate. The result of these twodividers in series is the 16X receiver baud rate clock. The SCR[2:0]bits are not affected by reset and can be changed at any time,although they should not be changed when any SCI transfer is inprogress.

Figure 7-8 and Figure 7-9 illustrate the SCI baud rate timing chain.The prescaler select bits determine the highest baud rate. The rateselect bits determine additional divide by two stages to arrive at thereceiver timing (RT) clock rate. The baud rate clock is the result ofdividing the RT clock by 16.



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Figure 7-8. SCI Baud Rate Generator Block Diagram

7.9 Status Flags and Interrupts

The.

SCI transmitter has two status flags. These status flags can be readby software (polled) to tell when the corresponding condition exists.Alternatively, a local interrupt enable bit can be set to enable each ofthese status conditions to generate interrupt requests when the-corresponding condition is present. Status flags are automatically set byhardware logic conditions, but must be cleared by software, whichprovides an interlock mechanism that enables logic to know when

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Status Flags and Interrupts�



Figure 7-9. MC68HC(7)11E20 SCI Baud RateGenerator Block Diagram

software has noticed the status indication. The software clearingsequence for these flags is automatic. Functions that are normallyperformed in response to the status flags also satisfy the conditions ofthe clearing sequence.-TDRE.

and TC flags are normally set when the transmitter is first enabled(TE set to 1). The TDRE flag indicates there is room in the transmitqueue to store another data character in the TDR. The TIE bit is the local

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interrupt mask for TDRE. When TIE is 0, TDRE must be polled. WhenTIE and TDRE are 1, an interrupt is requested.

The TC flag indicates the transmitter has completed the queue. TheTCIE.

bit is the local interrupt mask for TC. When TCIE is 0, TC must bepolled. When TCIE is 1 and TC is 1, an interrupt is requested.

Writing a 0 to TE requests that the transmitter stop when it can. Thetransmitter completes any transmission in progress before actually-shutting down. Only an MCU reset can cause the transmitter to stop andshut down immediately. If TE is written to 0 when the transmitter isalready idle, the pin reverts to its general-purpose I/O function(synchronized to the bit-rate clock). If anything is being transmitted whenTE is written to 0, that character is completed before the pin reverts togeneral-purpose I/O, but any other characters waiting in the transmitqueue are lost. The TC and TDRE flags are set at the completion of thislast character, even though TE has been disabled.

7.10 Receiver Flags

The SCI receiver has five status flags, three of which can generateinterrupt requests. The status flags are set by the SCI logic in responseto-

specific conditions in the receiver. These flags can be read (polled) atany time by software. Refer to Figure 7-10 , which shows SCI interruptarbitration.

When an overrun takes place, the new character is lost, and thecharacter that was in its way in the parallel RDR is undisturbed. RDRFis set when a character has been received and transferred into theparallel RDR. The OR flag is set instead of RDRF if overrun occurs. Anew character is ready to be transferred into RDR before a previouscharacter is read from RDR.

The.

NF and FE flags provide additional information about the characterin the RDR, but do not generate interrupt requests.

The last receiver status flag and interrupt source come from the IDLEflag. The RxD line is idle if it has constantly been at logic 1 for a full�character time. The IDLE flag is set only after the RxD line has been


Receiver Flags



busy and becomes idle, which prevents repeated interrupts for the wholetime RxD remains idle.-

Figure 7-10. Interrupt Source Resolution Within SCI

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MOTOROLA Serial Peripheral Interface (SPI) 163


Section 8. Serial Peripheral Interface (SPI)

8.1 Contents

8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

8.4 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

8.5 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . .167

8.6 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1678.6.1 Master In/Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1688.6.2 Master Out/Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1688.6.3 Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1688.6.4 Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

8.7 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

8.8 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1708.8.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . .1718.8.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . .1738.8.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . .174


164 Serial Peripheral Interface (SPI) MOTOROLA

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8.2 Introduction�

The serial peripheral interface (SPI), an independent serialcommunications subsystem, allows the MCU to communicatesynchronously with peripheral devices, such as:

• Frequency synthesizers

• Liquid crystal display (LCD) drivers

• Analog-to-digital (A/D) converter subsystems

• Other microprocessors

The SPI is also capable of inter-processor communication in a multiplemaster system. The SPI system can be configured as either a master ora slave device. When configured as a master, data transfer rates can beas high as one-half the E-clock rate (1.5 Mbits per second for a 3-MHzbus frequency). When configured as a slave, data transfers can be asfast as the E-clock rate (3 Mbits per second for a 3-MHz bus frequency).

8.3 Functional Description

The central element in the SPI system is the block containing the shiftregister and the read data buffer. The system is single buffered in thetransmit direction and double buffered in the receive direction. This-means that new data for transmission cannot be written to the shifteruntil the previous transfer is complete; however, received data istransferred-

into a parallel read data buffer so the shifter is free to accepta second serial character. As long as the first character is read out of theread data buffer before the next serial character is ready to betransferred,-

no overrun condition occurs. A single MCU register addressis used for reading data from the read data buffer and for writing data tothe shifter.-The SPI status block represents the SPI status functions (transfer.complete, write collision, and mode fault) performed by the serialperipheral status register (SPSR). The SPI control block representsthose-

functions that control the SPI system through the serial peripheralcontrol register (SPCR).

Serial Peripheral Interface (SPI)�

Functional Description



Refer to Figure 8-1 , which shows the SPI block diagram.

Figure 8-1. SPI Block Diagram

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8.4 SPI Transfer Formats�

During an SPI transfer, data is simultaneously transmitted and received.A�

serial clock line synchronizes shifting and sampling of the informationon the two serial data lines. A slave select line allows individual selectionof a slave SPI device; slave devices that are not selected do not interferewith SPI bus activities. On a master SPI device, the select line canoptionally be used to indicate a multiple master bus contention. Refer toFigure 8-2 .

Figure 8-2. SPI Transfer Format

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Clock Phase and Polarity Controls�



8.5 Clock Phase and Polarity Controls

Software can select one of four combinations of serial clock phase andpolarity using two bits in the SPI control register (SPCR). The clockpolarity is specified by the CPOL control bit, which selects an active highor active low clock, and has no significant effect on the transfer format.The clock phase (CPHA) control bit selects one of two different transferformats.�

The clock phase and polarity should be identical for the masterSPI device and the communicating slave device. In some cases, thephase and polarity are changed between transfers to allow a masterdevice to communicate with peripheral slaves having differentrequirements.

When CPHA equals 0, the SS line must be negated and reassertedbetween each successive serial byte. Also, if the slave writes data to theSPI data register (SPDR) while SS is low, a write collision error results.

When CPHA equals 1, the SS line can remain low between successivetransfers.-

8.6 SPI Signals

This subsection contains descriptions of the four SPI signals:

• Master in/slave out (MISO)

• Master out/slave in (MOSI)

• Serial clock (SCK)

• Slave select (SS)

Any SPI output line must have its corresponding data direction bit in�DDRD register set. If the DDR bit is clear, that line is disconnected fromthe SPI logic and becomes a general-purpose input. All SPI input lines-are forced to act as inputs regardless of the state of the correspondingDDR bits in DDRD register.



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8.6.1 Master In/Slave Out

MISO is one of two unidirectional serial data signals. It is an input to amaster device and an output from a slave device. The MISO line of aslave device is placed in the high-impedance state if the slave device isnot selected.

8.6.2 Master Out/Slave In

The.

MOSI line is the second of the two unidirectional serial data signals.It is an output from a master device and an input to a slave device. Themaster device places data on the MOSI line a half-cycle before the clockedge that the slave device uses to latch the data.

8.6.3 Serial Clock

SCK, an input to a slave device, is generated by the master device andsynchronizes data movement in and out of the device through the MOSIand MISO lines. Master and slave devices are capable of exchanging abyte of information during a sequence of eight clock cycles.

Four possible timing relationships can be chosen by using control bitsCPOL and CPHA in the serial peripheral control register (SPCR). Bothmaster and slave devices must operate with the same timing. The SPIclock rate select bits, SPR[1:0], in the SPCR of the master device, selectthe clock rate. In a slave device, SPR[1:0] have no effect on the-operation of the SPI.

8.6.4 Slave Select

The.

slave select (SS) input of a slave device must be externally assertedbefore a master device can exchange data with the slave device. SSmust be low before data transactions and must stay low for the durationof the transaction.

The SS line of the master must be held high. If it goes low, a mode faulterror flag (MODF) is set in the serial peripheral status register (SPSR).To disable the mode fault circuit, write a 1 in bit 5 of the port D data


SPI System Errors�



direction register. This sets the SS pin to act as a general-purposeoutput rather than the dedicated input to the slave select circuit, thusinhibiting the mode fault flag. The other three lines are dedicated to theSPI whenever the serial peripheral interface is on.

The state of the master and slave CPHA bits affects the operation of SS.CPHA settings should be identical for master and slave. WhenCPHA = 0, the shift clock is the OR of SS with SCK. In this clock phasemode, SS must go high between successive characters in an SPImessage. When CPHA = 1, SS can be left low between successive SPIcharacters. In cases where there is only one SPI slave MCU, its SS linecan be tied to VSS

� as long as only CPHA = 1 clock mode is used.

8.7 SPI System Errors

Two.

system errors can be detected by the SPI system. The first type oferror arises in a multiple-master system when more than one SPI devicesimultaneously tries to be a master. This error is called a mode fault. Thesecond type of error, write collision, indicates that an attempt was madeto write data to the SPDR while a transfer was in progress.-When the SPI system is configured as a master and the SS input linegoes to active low, a mode fault error has occurred — usually becausetwo-

devices have attempted to act as master at the same time. In caseswhere more than one device is concurrently configured as a master,there is a chance of contention between two pin drivers. For push-pull-CMOS drivers, this contention can cause permanent damage. The modefault mechanism attempts to protect the device by disabling the drivers.The MSTR control bit in the SPCR and all four DDRD control bits.associated with the SPI are cleared and an interrupt is generated subjectto masking by the SPIE control bit and the I bit in the CCR.-Other precautions may need to be taken to prevent driver damage. If twodevices are made masters at the same time, mode fault does not helpprotect either one unless one of them selects the other as slave. Theamount of damage possible depends on the length of time both devicesattempt to act as master.



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A�

write collision error occurs if the SPDR is written while a transfer is inprogress. Because the SPDR is not double buffered in the transmitdirection, writes to SPDR cause data to be written directly into the SPIshift register. Because this write corrupts any transfer in progress, awrite collision error is generated. The transfer continues undisturbed,´and the write data that caused the error is not written to the shifter.

A write collision is normally a slave error because a slave has no controlover when a master initiates a transfer. A master knows when a transferis in progress, so there is no reason for a master to generate awrite-collision´ error, although the SPI logic can detect write collisions inboth master and slave devices.

The SPI configuration determines the characteristics of a transfer inprogress. For a master, a transfer begins when data is written to SPDRand ends when SPIF is set. For a slave with CPHA equal to 0, a transferstarts when SS goes low and ends when SS returns high. In this case,SPIF is set at the middle of the eighth SCK cycle when data istransferred from the shifter to the parallel data register, but the transfer-is still in progress until SS goes high. For a slave with CPHA equal to 1,transfer begins when the SCK line goes to its active level, which is the-edge at the beginning of the first SCK cycle. The transfer ends in a slavein which CPHA equals 1 when SPIF is set.

8.8 SPI Registers

The three SPI registers are:.

• Serial peripheral control register (SPCR)

• Serial peripheral status register (SPSR)

• Serial peripheral data register (SPDR)

These registers provide control, status, and data storage functions..


SPI Registers�



8.8.1 Serial Peripheral Control Register

SPIE — Serial Peripheral Interrupt Enable Bit

Set the SPE bit to 1 to request a hardware interrupt sequence eachtime-

the SPIF or MODF status flag is set. SPI interrupts are inhibitedif this bit is clear or if the I bit in the condition code register is 1.

0 = SPI system interrupts disabled1 = SPI system interrupts enabled

SPE — Serial Peripheral System Enable Bit

When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicatedto the SPI function. If the SPI is in the master mode and DDRD bit 5-is set, then the port D bit 5 pin becomes a general-purpose outputinstead of the SS input.

0 = SPI system disabled1 = SPI system enabled

DWOM — Port D Wired-OR Mode Bit

DWOM affects all port D pins.0 = Normal CMOS outputs1 = Open-drain outputs

MSTR — Master Mode Select Bit

It is customary to have an external pullup resistor on lines that aredriven by open-drain devices.

0 = Slave mode1 = Master mode

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CPOL — Clock Polarity Bit

When the clock polarity bit is cleared and data is not beingtransferred,-

the SCK pin of the master device has a steady state lowvalue. When CPOL is set, SCK idles high. Refer to Figure 8-2 and8.5 Clock Phase and Polarity Controls .

CPHA — Clock Phase Bit

The clock phase bit, in conjunction with the CPOL bit, controls theclock-data relationship between master and slave. The CPHA bitselects one of two different clocking protocols. Refer to Figure 8-2and 8.5 Clock Phase and Polarity Controls .

SPR[1:0] — SPI Clock Rate Select Bits

These two bits select the SPI clock (SCK) rate when the device is.configured as master. When the device is configured as slave, thesebits have no effect. Refer to Table 8-1 .

T�

able 8-1. SPI Cloc k Rates

SPR[1:0]� Divide

E Clock ByFrequency at

E = 1 MHz (Baud)Frequency at



E = 4 MHz (Baud)

0 0�

2 500 kHz 1.0 MHz 1.5 MHz 2 MHz

0 1�

4 250 kHz 500 kHz 750 kHz 1 MHz

1 0 16 62.5 kHz 125 kHz 187.5 kHz 250 kHz

1 1 32 31.3 kHz 62.5 kHz 93.8 kHz 125 kHz


SPI Registers�



8.8.2 Serial Peripheral Status Register

SPIF — SPI Interrupt Complete Flag

SPIF is set upon completion of data transfer between the processorand the external device. If SPIF goes high, and if SPIE is set, a serialperipheral interrupt is generated. To clear the SPIF bit, read theSPSR with SPIF set, then access the SPDR. Unless SPSR is read(with SPIF set) first, attempts to write SPDR are inhibited.

WCOL — Write Collision Bit

Clearing the WCOL bit is accomplished by reading the SPSR (withWCOL set) followed by an access of SPDR. Refer to 8.6.4 SlaveSelect and 8.7 SPI System Errors .

0 = No write collision1 = Write collision


Always reads 0�

MODF — Mode Fault Bit

To.

clear the MODF bit, read the SPSR (with MODF set), then write tothe SPCR. Refer to-

8.6.4 Slave Select and 8.7 SPI System Errors .0 = No mode fault1 = Mode fault


Always read 0�

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8.8.3 Serial Peripheral Data I/O Register

The.

SPDR is used when transmitting or receiving data on the serial bus.Only a write to this register initiates transmission or reception of a byte,and this only occurs in the master device. At the completion oftransferring a byte of data, the SPIF status bit is set in both the master-and slave devices.

A�

read of the SPDR is actually a read of a buffer. To prevent an overrunand the loss of the byte that caused the overrun, the first SPIF must becleared by the time a second transfer of data from the shift register to theread buffer is initiated.

SPI is double buffered in and single buffered out.

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MOTOROLA Timing System 175

Technical Data — M68HC11E Family

Section 9. Timing System

9.1 Contents

9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

9.3 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

9.4 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1809.4.1 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .1819.4.2 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . .1829.4.3 Timer Input Capture 4/Output Compare 5 Register . . . . . .184

9.5 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1849.5.1 Timer Output Compare Registers . . . . . . . . . . . . . . . . . . .1859.5.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . .1889.5.3 Output Compare Mask Register. . . . . . . . . . . . . . . . . . . . .1899.5.4 Output Compare Data Register . . . . . . . . . . . . . . . . . . . . .1909.5.5 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .1919.5.6 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .1929.5.7 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . .1939.5.8 Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . .1949.5.9 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . .1949.5.10 Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . .196

9.6 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .1979.6.1 Timer Interrupt Mask Register 2. . . . . . . . . . . . . . . . . . . . .1989.6.2 Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . .1999.6.3 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . .200

9.7 Computer Operating Properly (COP) Watchdog Function . . .201

9.8 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2019.8.1 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . .2039.8.2 Pulse Accumulator Count Register . . . . . . . . . . . . . . . . . .2049.8.3 Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . .205


176 Timing System MOTOROLA

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9.2 Introduction�

The M68HC11 timing system is composed of five clock divider chains.The main clock divider chain includes a 16-bit free-running counter,.which is driven by a programmable prescaler. The main timer’sprogrammable prescaler provides one of the four clocking rates to drivethe 16-bit counter. Two prescaler control bits select the prescale rate.-The.

prescaler output divides the system clock by 1, 4, 8, or 16. Taps offof this main clocking chain drive circuitry that generates the slowerclocks used by the pulse accumulator, the real-time interrupt (RTI), andthe computer operating properly (COP) watchdog subsystems, also-described in this section. Refer to Figure 9-1 .

All main timer system activities are referenced to this free-running�counter. The counter begins incrementing from $0000 as the MCUcomes out of reset and continues to the maximum count, $FFFF. At themaximum count, the counter rolls over to $0000, sets an overflow flag,and continues to increment. As long as the MCU is running in a normaloperating mode, there is no way to reset, change, or interrupt thecounting. The capture/compare subsystem features three input capturechannels, four output compare channels, and one channel that can beselected to perform either input capture or output compare. Each of thethree input capture functions has its own 16-bit input capture register-(time capture latch) and each of the output compare functions has itsown 16-bit compare register. All timer functions, including the timeroverflow and RTI, have their own interrupt controls and separateinterrupt vectors.

The.

pulse accumulator contains an 8-bit counter and edge select logic.The pulse accumulator can operate in either event counting mode orgated time accumulation mode. During event counting mode, the pulseaccumulator’s 8-bit counter increments when a specified edge isdetected on an input signal. During gated time accumulation mode, aninternal clock source increments the 8-bit counter while an input signalhas a predetermined logic level.

The.

real-time interrupt (RTI) is a programmable periodic interrupt circuitthat permits pacing the execution of software routines by selecting one-of four interrupt rates.

Timing System�

Introduction



The.

COP watchdog clock input (E ÷a 215) is tapped off of the free-runningcounter chain. The COP automatically times out unless it is servicedwithin´ a specific time by a program reset sequence. If the COP is allowedto-

time out, a reset is generated, which drives the RESET pin low to resetthe-

MCU and the external system. Refer to Table�

9-1 for�

crystal-relatedfrequencies and periods.�

Figure 9-1. Timer Clock Divider Chains

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9.3 Timer Structure�

Figure 9-2 shows the capture/compare system block diagram. Theport A pin control block includes logic for timer functions and forgeneral-purpose I/O. For pins PA3, PA2, PA1, and PA0, this blockcontains both the edge-detection logic and the control logic that enablesthe-

selection of which edge triggers an input capture. The digital level onPA[3:0] can be read at any time (read PORTA register), even if the pinis being used for the input capture function. Pins PA[6:3] are used foreither general-purpose I/O, or as output compare pins. When one ofthese pins is being used for an output compare function, it cannot be-written directly as if it were a general-purpose output. Each of the outputcompare functions (OC[5:2]) is related to one of the port A output pins.Output compare one (OC1) has extra control logic, allowing it optionalcontrol of any combination of the PA[7:3] pins. The PA7 pin can be usedas a general-purpose I/O pin, as an input to the pulse accumulator, or asan OC1 output pin.

Table 9-1. Timer Summar y

XTAL Frequencies®

Control Bits�

PR1, PR0

4.0 MHz 8.0 MHz 12.0 MHz Other Rates

1.0 MHz 2.0 MHz 3.0 MHz (E)

1000 ns 500 ns 333 ns (1/E)

Main Timer Count Rates

0 0�

1 count —o� verflow —

1000 ns65.536 msZ 500 ns

]32.768 msY 333 ns

Y21.845 ms

(E/1)

(E/216)¯

0 1�

1 count —o� verflow —

4.0 µs�262.14 ms\ 2.0 µs�

131.07 ms1.333 µs�

87.381 msX (E/4)

(E/218)¯

1 01 count —o� verflow —

8.0X

µs�524.29 ms] 4.0

W µs�

262.14 ms2.667\

µs�174.76 ms

(E/8)

(E/219)¯

1 11 count —o� verflow —

16.0 µs�1.049 s

8.0X

µs�524.29 ms] 5.333

] µs�

349.52 msY (E/16)

(E/220)¯

Timing System�Timer Structure



Figure 9-2. Capture/Compare Block Diagram

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9.4 Input Capture�

The input capture function records the time an external event occurs bylatching the value of the free-running counter when a selected edge isdetected at the associated timer input pin. Software can store latchedvalues� and use them to compute the periodicity and duration of events.For example, by storing the times of successive edges of an incomingsignal, software can determine the period and pulse width of a signal. Tomeasure period, two successive edges of the same polarity arecaptured. To measure pulse width, two alternate polarity edges arecaptured.

In most cases, input capture edges are asynchronous to the internaltimer-

counter, which is clocked relative to an internal clock (PH2). Theseasynchronous capture requests are synchronized to PH2 so that thelatching occurs on the opposite half cycle of PH2 from when the timercounter is being incremented. This synchronization process introducesa delay from when the edge occurs to when the counter value isdetected. Because these delays offset each other when the timebetween two edges is being measured, the delay can be ignored. Whenan input capture is being used with an output compare, there is a similardelay between the actual compare point and when the output pinchanges state.

The control and status bits that implement the input capture functionsare contained in:

• Pulse accumulator control register (PACTL)

• Timer control 2 register (TCTL2)

• Timer interrupt mask 1 register (TMSK1)

• Timer interrupt flag 2 register (TFLG1)

To configure port A bit 3 as an input capture, clear the DDRA3 bit of thePACTL register. Note that this bit is cleared out of reset. To enable PA3as the fourth input capture, set the I4/O5 bit in the PACTL register.Otherwise, PA3 is configured as a fifth output compare out of reset, withbit I4/O5 being cleared. If the DDRA3 bit is set (configuring PA3 as anoutput), and IC4 is enabled, then writes to PA3 cause edges on the pin

Timing System�

Input Capture



to result in input captures. Writing to TI4/O5 has no effect when the-TI4/O5 register is acting as IC4.

9.4.1 Timer Control Register 2

Use the control bits of this register to program input capture functions todetect a particular edge polarity on the corresponding timer input pin.Each of the input capture functions can be independently configured todetect rising edges only, falling edges only, any edge (rising or falling),or to disable the input capture function. The input capture functionsoperate independently of each other and can capture the same TCNTvalue if the input edges are detected within the same timer count cycle.

EDGxB and EDGxA — Input Capture Edge Control Bits

There are four pairs of these bits. Each pair is cleared to 0 by resetand must be encoded to configure the corresponding input captureedge detector circuit. IC4 functions only if the I4/O5 bit in the PACTLregister is set. Refer to Table 9-2

� for timer control configuration.

/10204365478789;:2<4=4G2<>@? A&B C D E F G < >@? A&=

HI54J4029 j fIn E4> j fIn E / j fIn <4> j fIn < / j fIn G4> j fIn G / j fIn F4> j fIn F /LM3N? A'529HI54785 AU9 = = = = = = = =

Figure 9-3. Timer Control Register 2 (TCTL2)

T�

able 9-2. Timer Contr ol Configuration

EDGxB EDGxA Configuration

0�

0 Capture disabled

0�

1 Capture on rising edges only

1 0 Capture on falling edges only

1 1 Capture on any edge



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9.4.2 Timer Input Capture Registers

When an edge has been detected and synchronized, the 16-bitfree-running counter value is transferred into the input capture registerpair as a single 16-bit parallel transfer. Timer counter value captures andtimer-

counter incrementing occur on opposite half-cycles of the phase 2clock so that the count value is stable whenever a capture occurs. Thetimer input capture registers are not affected by reset. Input capture-values� can be read from a pair of 8-bit read-only registers. A read of thehigh-order byte of an input capture register pair inhibits a new capturetransfer-

for one bus cycle. If a double-byte read instruction, such as loaddouble accumulator D (LDD), is used to read the captured value,coherency is assured. When a new input capture occurs immediatelyafter a high-order byte read, transfer is delayed for an additional cyclebut the value is not lost.

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HI54J4029 >@? A&B >@? A&C >Ë? A@D >@? A&E >Ë? A@F >Ë? A@G >Ë? A@< >Ë? A@=LM3N? A'529HI54785 AU9 O Q4025 A'5436vc? Q4JRA'5cJRS A'543u3654785 A

Figure 9-4. Timer Input Capture 1 Register Pair (TIC1)

Timing System�

Input Capture



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9.4.3 Timer Input Capture 4/Output Compare 5 Register

Use TI4/O5 as either an input capture register or an output compareregister, depending on the function chosen for the PA3 pin. To enable itas an input capture pin, set the I4/O5 bit in the pulse accumulator controlregister (PACTL) to logic level 1. To use it as an output compare register,set the I4/O5 bit to a logic level 0. Refer to 9.8 Pulse Accumulator .

9.5 Output Compare

Use the output compare (OC) function to program an action to occur ata specific time — when the 16-bit counter reaches a specified value. Foreach of the five output compare functions, there is a separate 16-bitcompare register and a dedicated 16-bit comparator. The value in thecompare register is compared to the value of the free-running counter onevery bus cycle. When the compare register matches the counter value,an output compare status flag is set. The flag can be used to initiate theautomatic actions for that output compare function.

To produce a pulse of a specific duration, write a value to the output.compare register that represents the time the leading edge of the pulseis to occur. The output compare circuit is configured to set the

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1< < < < < < <

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HI54J4029 >@? A&B >@? A&C >Ë? A@D >@? A&E >Ë? A@F >Ë? A@G >Ë? A@< >Ë? A@=LM3N? A'529HI54785 AU9

1< < < < < < <

Figure 9-7. Timer Input Capture 4/OutputCompare 5 Register Pair (TI4/O5)

Timing System�

Output CompareÎ



appropriate output either high or low, depending on the polarity of thepulse being produced. After a match occurs, the output compare registeris reprogrammed to change the output pin back to its inactive level at thenext match. A value representing the width of the pulse is added to theoriginal value, and then written to the output compare register. Becausethe pin state changes occur at specific values of the free-running-counter, the pulse width can be controlled accurately at the resolution ofthe free-running counter, independent of software latencies. To-generate an output signal of a specific frequency and duty cycle, repeatthis pulse-generating procedure.-The five 16-bit read/write output compare registers are: TOC1, TOC2,.TOC3, and TOC4, and the TI4/O5. TI4/O5 functions under softwarecontrol as either IC4 or OC5. Each of the OC registers is set to $FFFFon reset. A value written to an OC register is compared to thefree-running counter value during each E-clock cycle. If a match is�found, the particular output compare flag is set in timer interrupt flagregister 1 (TFLG1). If that particular interrupt is enabled in the timerinterrupt mask register 1 (TMSK1), an interrupt is generated. In additionto an interrupt, a specified action can be initiated at one or more timer-output pins. For OC[5:2], the pin action is controlled by pairs of bits (OMxand OLx) in the TCTL1 register. The output action is taken on eachsuccessful compare, regardless of whether or not the OCxF flag in theTFLG1 register was previously cleared.

OC1 is different from the other output compares in that a successful OC1compare can affect any or all five of the OC pins. The OC1 output actiontaken when a match is found is controlled by two 8-bit registers with-three-

bits unimplemented: the output compare 1 mask register, OC1M,and the output compare 1 data register, OC1D. OC1M specifies whichport A outputs are to be used, and OC1D specifies what data is placedon these port pins.

9.5.1 Timer Output Compare Registers

All output compare registers are 16-bit read-write. Each is initialized to�$FFFF at reset. If an output compare register is not used for an outputcompare function, it can be used as a storage location. A write to the



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high-order byte of an output compare register pair inhibits the outputcompare function for one bus cycle. This inhibition preventsinappropriate subsequent comparisons. Coherency requires a complete16-bit read or write. However, if coherency is not needed, byte accessescan be used.

For output compare functions, write a comparison value to outputcompare registers TOC1–TOC4 and TI4/O5. When TCNT valuematches the comparison value, specified pin actions occur.

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1< < < < < < <

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1< < < < < < <

Figure 9-8. Timer Output Compare 1 Register Pair (TOC1)

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1< < < < < < <

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1< < < < < < <


Timing System�

Output CompareÎ



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1< < < < < < <

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1< < < < < < <




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9.5.2 Timer Compare Force Register

The CFORC register allows forced early compares. FOC[1:5].correspond to the five output compares. These bits are set for eachoutput compare that is to be forced. The action taken as a result of aforced compare is the same as if there were a match between the OCxregister and the free-running counter, except that the correspondinginterrupt status flag bits are not set. The forced channels trigger theirprogrammed pin actions to occur at the next timer count transition afterthe write to CFORC.-The CFORC bits should not be used on an output compare function thatis programmed to toggle its output on a successful compare because anormal compare that occurs immediately before or after the force canresult in an undesirable operation.

FOC[1:5] — Force Output Comparison Bit

When the FOC bit associated with an output compare circuit is set,the output compare circuit immediately performs the action it is-programmed to do when an output match occurs.

0 = Not affected1 = Output x action occurs


Always read 0�

/10204365478789�:4<2=4=4>>@? A&B C D E F G < >@? A&=

HI54J4029 |#X(YI< |#X(YIG |#X(YIF |#X YhE |#X(YIDLM3N? A'529HI54785RA'9 = = = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 9-12. Timer Compare Force Register (CFORC)

Timing System�

Output CompareÎ



9.5.3 Output Compare Mask Register

Use OC1M with OC1 to specify the bits of port A that are affected by asuccessful OC1 compare. The bits of the OC1M register correspond toPA[7:3].

OC1M[7:3] — Output Compare Masks0 = OC1 disabled1 = OC1 enabled to control the corresponding pin of port A


Always read 0

/10204365478789 :4<4=2=4Y>@? A&B C D E F G < >@? A&=

HI54J4029 X(Yh<2mcB X(Yh<2mcC X(Yh<2mcD X(Yh<2mcE X(Yh<2mcFLM3N? A'529HI54785RA'9 = = = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 9-13. Output Compare 1 Mask Register (OC1M)



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9.5.4 Output Compare Data Register

Use this register with OC1 to specify the data that is to be stored on theaffected pin of port A after a successful OC1 compare. When asuccessful OC1 compare occurs, a data bit in OC1D is stored in thecorresponding bit of port A for each bit that is set in OC1M.

If OC1Mx is set, data in OC1Dx is output to port A bit x on successfulOC1 compares.


Always read 0

/10204365478789 :4<4=2= f>@? A&B C D E F G < >@? A&=

HI54J4029 X(YI< f B X(YI< f C X(YI< f D X(YI< f E X(YI< f FLM3N? A'529HI54785RA'9 = = = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 9-14. Output Compare 1 Data Register (OC1D)

Timing System�

Output CompareÎ



9.5.5 Timer Counter Register

The.

16-bit read-only TCNT register contains the prescaled value of the16-bit timer. A full counter read addresses the most significant byte(MSB) first. A read of this address causes the least significant byte (LSB)to be latched into a buffer for the next CPU cycle so that a double-byte-read returns the full 16-bit state of the counter at the time of the MSBread cycle.

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0� = = = = = = =

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0� = = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 9-15. Timer Counter Register (TCNT)



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9.5.6 Timer Control Register 1

The bits of this register specify the action taken as a result of a.successful OCx compare.

OM[2:5] — Output Mode BitsOL[2:5] — Output Level Bits

These.

control bit pairs are encoded to specify the action taken after asuccessful OCx compare. OC5 functions only if the I4/O5 bit in thePACTL register is clear. Refer to Table 9-3

� for the coding.

/10204365478789;:2<4=4G2=>@? A&B C D E F G < >@? A&=

HI54J4029 X(mcG X({4G X(mcF X({4F X(mcE X({4E X(mcD X({4DLM3N? A'529HI54785 AU9 = = = = = = = =

Figure 9-16. Timer Control Register 1 (TCTL1)

T�

able 9-3. Timer Output Compare Actions

OMx�

OLx Action Taken on Successful Compare

0�

0 Timer disconnected from output pin logic

0�

1 Toggle OCx output line

1 0 Clear OCx output line to 0

1 1 Set OCx output line to 1

Timing System�

Output CompareÎ



9.5.7 Timer Interrupt Mask 1 Register

Use this 8-bit register to enable or inhibit the timer input capture andoutput compare interrupts.

OC1I–OC4I — Output Compare x Interrupt Enable Bits

If the OCxI enable bit is set when the OCxF flag bit is set, a hardwareinterrupt sequence is requested.

I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable Bit

When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interruptenable bit. When I4/O5 in PACTL is 0, I4/O5I is the output compare 5interrupt enable bit.

IC1I–IC3I — Input Capture x Interrupt Enable Bits

If the ICxI enable bit is set when the ICxF flag bit is set, a hardwareinterrupt sequence is requested.

NOTE: Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits inTMSK1 enable the corresponding interrupt sources.

/10204365478789;:2<4=4G2G>@? A&B C D E F G < >@? A&=

HI54J4029 X(YI<4O X(YIG4O X(YIF4O X(YIE4O O E Z'X(D2O O YI<4O O YIG4O O YIF4OLM3N? A'529HI54785 AU9 = = = = = = = =

Figure 9-17. Timer Interrupt Mask 1 Register (TMSK1)



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9.5.8 Timer Interrupt Flag 1 Register

Bits in this register indicate when timer system events have occurred.Coupled with the bits of TMSK1, the bits of TFLG1 allow the timersubsystem to operate in either a polled or interrupt driven system. Eachbit of TFLG1 corresponds to a bit in TMSK1 in the same position.

Clear flags by writing a 1 to the corresponding bit position(s).

OC1F–OC4F — Output Compare x Flag

Set each time the counter matches output compare x value

I4/O5F — Input Capture 4/Output Compare 5 Flag

Set by IC4 or OC5, depending on the function enabled by I4/O5 bit inPACTL

IC1F–IC3F — Input Capture x Flag

Set each time a selected active edge is detected on the ICx input line

9.5.9 Timer Interrupt Mask 2 Register

Use this 8-bit register to enable or inhibit timer overflow and real-timeinterrupts. The timer prescaler control bits are included in this register.

/10204365478789;:2<4=4G2F>@? A&B C D E F G < >@? A&=

HI54J4029 X(Yh<2| X(YhG2| X(YhF2| X(YhE2| O ERZ'X(D4| O Yh<2| O YIG4| O YIF4|LM3N? A'529HI54785 AU9 = = = = = = = =

Figure 9-18. Timer Interrupt Flag 1 Register (TFLG1)

/10204365478789;:2<4=4G2E>@? A&B C D E F G < >@? A&=

HI54J4029 oËX(O H�ohO O K /dXI�@O K /1O O K Hh< K Hh=LM3N? A'529HI54785RA'9 = = = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 9-19. Timer Interrupt Mask 2 Register (TMSK2)

Timing System�

Output CompareÎ



TOI — Timer Overflow Interrupt Enable Bit.

0 = TOF interrupts disabled1 = Interrupt requested when TOF is set to 1

RTII — Real-Time Interrupt Enable Bit

Refer to 9.6 Real-Time Interrupt (RTI) .

PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit

Refer to 9.8.3 Pulse Accumulator Status and Interrupt Bits .

PAII — Pulse Accumulator Input Edge Interrupt Enable Bit

Refer to 9.8.3 Pulse Accumulator Status and Interrupt Bits .


Always read 0�

PR[1:0] — Timer Prescaler Select Bits

These bits are used to select the prescaler divide-by ratio. In normalmodes, PR[1:0] can be written only once, and the write must be within64 cycles after reset. Refer to Table 9-1 and Table 9-4 for specifictiming values.-


Table 9-4. Timer Prescale

PR[1:0] Prescaler

0 0�

1

0 1�

4

1 0 8

1 1 16



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9.5.10 Timer Interrupt Flag Register 2

Bits in this register indicate when certain timer system events haveoccurred. Coupled with the four high-order bits of TMSK2, the bits ofTFLG2 allow the timer subsystem to operate in either a polled or.interrupt driven system. Each bit of TFLG2 corresponds to a bit inTMSK2 in the same position..


TOF — Timer Overflow Interrupt Flag

Set when TCNT changes from $FFFF to $0000

RTIF — Real-Time (Periodic) Interrupt Flag


PAOVF — Pulse Accumulator Overflow Interrupt Flag

Refer to 9.8 Pulse Accumulator .

PAIF — Pulse Accumulator Input Edge Interrupt Flag



Always read 0

/10204365478789;:2<4=4G2D>@? A&B C D E F G < >@? A&=

HI54J4029 o@X(| H�ohO | K /dXI�Ë| K /1O |LM3N? A'529HI54785RA'9 = = = = = = = =

\]~hQ2? v_`4P 54v_54Q A'520Figure 9-20. Timer Interrupt Flag 2 Register (TFLG2)

Timing System�

Real-Time Interrupt (RTI)



9.6 Real-Time Interrupt (RTI)

The real-time interrupt (RTI) feature, used to generate hardwareinterrupts at a fixed periodic rate, is controlled and configured by two bits(RTR1 and RTR0) in the pulse accumulator control (PACTL) register.The.

RTII bit in the TMSK2 register enables the interrupt capability. Thefour different rates available are a product of the MCU oscillatorfrequency and the value of bits RTR[1:0]. Refer to�

Table 9-1�

, whichshows the periodic real-time interrupt rates.

The clock source for the RTI function is a free-running clock that cannotbe stopped or interrupted except by reset. This clock causes the timebetween successive RTI timeouts to be a constant that is independentof the software latencies associated with flag clearing and service. Forthis reason, an RTI period starts from the previous timeout, not from-when RTIF is cleared.

Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set,an interrupt request is generated. After reset, one entire RTI periodelapses before the RTIF is set for the first time. Refer to the 9.5.9 TimerInterrupt Mask 2 Register , 9.6.2 Timer Interrupt Flag Register 2, and9.6.3 Pulse Accumulator Control Register .

Table 9-5. RTI Rates

RTR[1:0] E = 3 MHz E = 2 MHz E = 1 MHz E = X MHz

0 0�

2.731 ms 4.096 ms 8.192 ms (E/213)¯

0 1�

5.461 ms 8.192 ms 16.384 ms (E/214)¯

1 0 10.923 ms 16.384 ms 32.768 ms (E/215)¯

1 1 21.845 ms 32.768 ms 65.536 ms (E/216)¯



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9.6.1 Timer Interrupt Mask Register 2

This register contains the real-time interrupt enable bits..

TOI — Timer Overflow Interrupt Enable Bit0 = TOF interrupts disabled1 = Interrupt requested when TOF is set to 1

RTII — Real-Time Interrupt Enable Bit0 = RTIF interrupts disabled1 = Interrupt requested when RTIF set to 1

PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit


PAII — Pulse Accumulator Input Edge Bit



Always read 0�

PR[1:0] — Timer Prescaler Select Bits

Refer to Table 9-4�

.


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Timing System�

Real-Time Interrupt (RTI)



9.6.2 Timer Interrupt Flag Register 2

Bits of this register indicate the occurrence of timer system events.Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allowthe timer subsystem to operate in either a polled or interrupt driven-system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the sameposition.


TOF — Timer Overflow Interrupt Flag

Set when TCNT changes from $FFFF to $0000

RTIF — Real-Time Interrupt Flag

The RTIF status bit is automatically set to 1 at the end of every RTI.period. To clear RTIF, write a byte to TFLG2 with bit 6 set.

PAOVF — Pulse Accumulator Overflow Interrupt Flag


PAIF — Pulse Accumulator Input Edge Interrupt Flag



Always read 0�

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9.6.3 Pulse Accumulator Control Register

Bits RTR[1:0] of this register select the rate for the RTI system. Theremaining bits control the pulse accumulator and IC4/OC5 functions.


Refer to Section 6. Parallel Input/Output (I/O) Ports .

PAEN — Pulse Accumulator System Enable Bit


PAMOD — Pulse Accumulator Mode Bit






I4/O5 — Input Capture 4/Output Compare Bit



These two bits determine the rate at which the RTI system requests

interrupts. The RTI system is driven by an E divided by 213 rate clockthat-

is compensated so it is independent of the timer prescaler. Thesetwo-

control bits select an additional division factor. Refer to Table�

9-5.

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Figure 9-23. Pulse Accumulator Control Register (PACTL)

Timing System�

Computer Operating Properly (COP) Watchdog Function�



9.7 Computer Operating Properly (COP) Watchdog Function

The clocking chain for the COP function, tapped off of the main timerdivider chain, is only superficially related to the main timer system. TheCR[1:0] bits in the OPTION register and the NOCOP bit in the CONFIGregister determine the status of the COP function. One additionalregister, COPRST, is used to arm and clear the COP watchdog resetsystem. Refer to Section 5. Resets and Interrupts for

�a more detailed

discussion of the COP function.

9.8 Pulse Accumulator

The M68HC11 Family of MCUs has an 8-bit counter that can beconfigured to operate either as a simple event counter or for gated timeaccumulation, depending on the state of the PAMOD bit in the PACTLregister. Refer to the pulse accumulator block diagram, Figure 9-24. Inthe event counting mode, the 8-bit counter is clocked to increasing-values by an external pin. The maximum clocking rate for the externalevent counting mode is the E clock divided by two. In gated timeaccumulation mode, a free-running E-clock divide-by-64 signal drivesthe-

8-bit counter, but only while the external PAI pin is activated. Refer toTable 9-6. The pulse accumulator counter can be read or written at anytime.-



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Figure 9-24. Pulse Accumulator

Pulse accumulator control bits are also located within two timerregisters, TMSK2 and TFLG2, as described in the following paragraphs.

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Table 9-6. Pulse Accum ulator Timing

Crystal�

FrequencyE Clock Cycle Time E ÷ 64

Ó PACNTOverflow�

4.0 MHzW

1 MHz 1000 ns 64 µÔ s� 16.384 ms

8.0 MHzX

2 MHz 500 ns 32 µÔ s� 8.192 ms

12.0 MHz 3 MHz 333 ns 21.33 µÔ s� 5.461 ms

Timing System�

Pulse Accumulator



9.8.1 Pulse Accumulator Control Register

Four of this register’s bits control an 8-bit pulse accumulator system.Another bit enables either the OC5 function or the IC4 function, while twoother bits select the rate for the real-time interrupt system.



PAEN — Pulse Accumulator System Enable Bit0 = Pulse accumulator disabled1 = Pulse accumulator enabled

PAMOD — Pulse Accumulator Mode Bit0 = Event counter1 = Gated time accumulation


This bit has different meanings depending on the state of the PAMODbit, as shown in Table 9-7

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Figure 9-25. Pulse Accumulator Control Register (PACTL)

Table 9-7. Pulse Accum ulator Edg e Contr ol

PAMOD PEDGE Action on Clock

0�

0 PAI falling edge increments the counter.

0�

1 PAI rising edge increments the counter.

1 0 A 0 on PAI inhibits counting.

1 1 A 1 on PAI inhibits counting.



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I4/O5 — Input Capture 4/Output Compare 5 Bit0 = Output compare 5 function enable (no IC4)1 = Input capture 4 function enable (no OC5)



9.8.2 Pulse Accumulator Count Register

This.

8-bit read/write register contains the count of external input eventsat the PAI input or the accumulated count. The PACNT is readable evenif PAI is not active in gated time accumulation mode. The counter is notaffected by reset and can be read or written at any time. Counting issynchronized to the internal PH2 clock so that incrementing and readingoccur during opposite half cycles.

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Indeterminate after reset

Figure 9-26. Pulse Accumulator Count Register (PACNT)

Timing System�

Pulse Accumulator



9.8.3 Pulse Accumulator Status and Interrupt Bits

The.

pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF,are located within timer registers TMSK2 and TFLG2.

PAOVI and PAOVF — Pulse Accumulator Interrupt Enableand Overflow Flag

The PAOVF status bit is set each time the pulse accumulator countrolls over from $FF to $00. To clear this status bit, write a 1 in thecorresponding data bit position (bit 5) of the TFLG2 register. ThePAOVI control bit allows configuring the pulse accumulator overflowfor polled or interrupt-driven operation and does not affect the state ofPAOVF. When PAOVI is 0, pulse accumulator overflow interrupts areinhibited, and the system operates in a polled mode, which requiresthat PAOVF be polled by user software to determine when an-overflow has occurred. When the PAOVI control bit is set, a hardware

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interrupt request is generated each time PAOVF is set. Before leavingthe-

interrupt service routine, software must clear PAOVF by writing tothe TFLG2 register.-

PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable Bitand Flag

The.

PAIF status bit is automatically set each time a selected edge isdetected at the PA7/PAI/OC1 pin. To clear this status bit, write to theTFLG2.

register with a 1 in the corresponding data bit position (bit 4).The PAII control bit allows configuring the pulse accumulator inputedge detect for polled or interrupt-driven operation but does not affectsetting or clearing the PAIF bit. When PAII is 0, pulse accumulatorinput interrupts are inhibited, and the system operates in a polledmode. In this mode, the PAIF bit must be polled by user software todetermine when an edge has occurred. When the PAII control bit isset, a hardware interrupt request is generated each time PAIF is set.Before leaving the interrupt service routine, software must clear PAIFby writing to the TFLG2 register.

section 6. parallel input/output (i/o) ports

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