chapter 7 parallel ports

Chapter 7

Parallel Ports

Basic Concepts of I/O • I/O devices are also called peripheral devices.• I/O devices are pieces of equipment that

exchange data with a computer.– Examples include switches, light-emitting diodes,

cathode-ray tube screens, printers, modems, keyboards, and disk drives.

Interface (Peripheral) Chip (1 of 2)

• A chip whose function is to synchronize data transfer between the CPU and I/O devices

• Consists of control registers, status registers, data direction latches, and control circuitry

• Has pins that are connected to the CPU and I/O port pins that are connected to the I/O devices

• Each interface chip has a chip enable signal input or inputs, when asserted, allow the interface chip to react to the data transfer request.

• Data transfer between an I/O device and the CPU can be proceeded bit-by-bit or in multiple bits (parallel).

AddressDecoder

Microprocessor

Data Bus

Interfacechip 1

Interfacechip 1

frominputdevice

tooutputdeviceI/O pins

Figure 7.1 Interface chip, I/O devices, and microprocessor

CE CE

Interface (Peripheral) Chip (2 of 2)

• Address decoder makes sure that each time one and only one peripheral device responds to the CPU’s I/O request.

I/O Schemes• Isolated I/O scheme

– The microprocessor has dedicated instructions for I/O operations.

– The microprocessor has a separate address space for I/O devices.

• Memory-mapped I/O scheme– The microprocessor uses the same instruction set to

perform memory accesses and I/O operations.– The I/O devices and memory components are

resident in the same memory space.

MicroprocessorControl signals

(such as R/W orinterrupt)

Interface chip

handshake orstrobe signal I/O device

electronics

Data Bus

Dat

a B

us

Figure 7.2 The role of an interface chip

I/O Transfer Synchronization • The role of an interface chip

– Synchronizing data transfer between the CPU and the interface chip

– Synchronizing data transfer between the interface chip and the I/O device

Synchronizing the Microprocessor and the Interface Chip

• The polling method– For input -- The microprocessor checks a status bit of the

interface chip to find out if the interface chip has received new data from the input device.

– For output -- The microprocessor checks a status bit of the interface chip to find out if it can send new data to the interface chip.

• The interrupt-driven method– For input -- The interface chip interrupts the microprocessor

whenever it has received new data from the input device.– For output -- The interface chip interrupts the microprocessor

whenever it can accept new data from the microprocessor.

Synchronizing the Interface Chip and the I/O Devices

• Brute-force method -- useful when the data timing is unimportant– For input -- Nothing special is done. The microprocessor reads the interface chip

and the interface chip returns the voltage levels on the input port pins to the microprocessor.

– For output -- Nothing special is done. The interface chip places the data that it received from the microprocessor directly on the output port pins.

• The strobe method -- a strobe signal used to indicate that data are stable on I/O port pins

– For input -- The interface chip latches the data into its data register using the strobe signal.

– For output -- The interface chip places the data on port pins that it received from the microprocessor and asserts the strobe signal. The output device latches the data using the strobe signal.

• The handshake method -- used when timing is crucial– Two handshake signals used to synchronize the data transfer. One signal, call it

H1, is asserted by the interface chip. The other signal, call it H2, is asserted by the I/O device.

– Two handshake modes available• Pulse mode and interlocked mode

Valid Data

H1

Data

H2

(a) Interlocked

H1

H2

Data Valid Data

(b) Pulse mode

Figure 7.3 Input Handshakes

Input Handshake Protocol• Step 1. The interface chip

asserts (or pulses) H1 to indicate its intention to input data.

• Step 2. The input device puts data on the data port pins and also asserts (or pulses) the handshake signal H2.

• Step 3. The interface chip latches the data and de-asserts H1. After some delay, the input device also de-asserts H2.

Valid Data

(a) Interlocked

H1

H2

Data

Valid Data

(b) Pulse Mode

H1

H2

Data

Figure 7.4 Output Handshaking

Output Handshake Protocol• Step 1. The interface chip

places data on the port pins and asserts (or pulses) H1 to indicate that it has valid data to be output.

• Step 2. The output device latches the data and asserts (or pulses) H2 to acknowledge the receipt of data.

• Step 3. The interface chip de-asserts H1 following the assertion of H2. The output device then de-asserts H2.

Overview of HCS12 Parallel Ports (1 of 3)

• The HCS12 members have from 48 to 144 I/O pins arranged in 3 to 12 ports and packaged in a quad flat pack (QFP) or low profile quad flat pack (LQFP).

• All I/O pins serve multiple functions.• When a peripheral function is enabled, its associated

pins cannot be used as I/O pins.• Each I/O port has several registers to support its

operation.• Registers related to I/O ports have been assigned a

mnemonic name and the user can use these names to refer to them:movb #$FF,PTA ; output $FF to Port A


• All I/O ports (except PAD0 and PAD1) have an associated data direction register and a data register.

• The name of the data direction register is formed by adding the letters “DDR” as the prefix to the port name. For example, DDRA, DDRB, and DDRT.

• To configure a pin for output, write a ‘1’ to the associated bit in the data direction register.

• To configure a pin for input, write a ‘0’ to the associated bit in the data direction register.

movb #$FF,DDRA ; configure port A for outputmovb #0,DDRA ; configure port A for inputbset DDRA,$81 ; configure Port A pin 7 and 1 for output


• The name of port data register is formed by adding letters “PT” as the prefix to the port name. For example, PTA, PTB, PTP, and PTT.

• We can also use “PORT” as the prefix to the port name for port A, B, E, and K.

• Output a value to a port is done by storing that value to the port data register.

movb #$FF,DDRH ; configure Port H for outputmovb #$37,PTH; output the hex value 37 to port H

• Input a value from an input port is done by loading from the port data register.

movb #0,DDRH ; configure Port H for inputldaa PTH ; read data from port H into A

• An I/O port may have up to eight associated registers.

Port A and Port B• In expanded mode, Port A carries the time-

multiplexed higher address/data signals A15/D15…A8/D8.

• In expanded mode, Port B carries the time-multiplexed lower address/data signals A7/D7…A0/D0.

• In single chip mode, these two ports are used as general I/O ports.

PE0/ XIRQ

PE1/ IRQ

PE2/ R/ W

PE3/ LSTRB/ TAGLO

PE4/ ECLK

PE5/ MODA/ IPIPE0

PE6/ MODB/ IPIPE1

Figure 7.5 Port E pins and their alternate functions

PE7/ NOACC/ XCLKS

Port E• Port E pins are used

for bus control and interrupt service request signals.

• When a Port E pin is not used as control or interrupt signal, it can be used as general I/O pin.

Port E Registers• Port E assignment register (PEAR)

– In expanded mode, the PEAR register assigns the function of each port E pin.• MODE register

– This register establishes the operation mode and other miscellaneous functions.• Pull-up control register (PUCR)

– This register selects the pull-up resistors for the pins associated with the core ports.

– Port A, B, E, and K are in the core part.• Reduced drive register (RDRIV)

– This register selects reduced drive for the pins associated with the core ports.– This gives reduced power consumption and reduced RFI with a slight increase in

transition time.• External bus interface control register (EBICTL)

– Only bit 0 is implemented (ESTR).– The ESTR bit enables/disables the E clock stretching.

NOACCE 0 PIPOE NECLK LSTRE RDWE 0 0

7 6 5 4 3 2 1 0

Figure 7.6 PEAR register

$000A

NOACCE: No Access output enable. Can be read/written any time. 0 = PE7 is used as general-purpose I/O pin 1 = PE7 is output and indicates whether the cycle is a CPU free cyclePIPOE: Pipe signal output enable. In normal modes: write once. Special modes: write anytime except the first time. This bit has no effect in single chip modes. 0 = PE[6:5] are general-purpose I/O 1 = PE[6:5] are outputs and indicate the state of the instruction queue.NECLK: No external E clock. Can be read anytime. In expanded modes, writes to this bit has no effect. E clock is required for de-multiplexing the external address. NECLK can be written once in normal single chip mode and can be written anytime in special single chip mode. 0 = PE4 is the external E-clock. 1 = PE4 is a general-purpose I/O pin.LSTRE: Low strobe (LSTRB) enable. Can be read anytime. In normal modes: write once; special modes: write anytime. This bit has no effect in single-chip modes or normal expanded narrow mode. 0 = PE3 is a general-purpose I/O pin. 1 = PE3 is configured as the LSTRB bus-control output, provided the HCS12 is not in single chip or normal expanded narrow modes.RDWE: Read/write enable. Can be read anytime. In normal modes: write once; special modes: write anytime except the first time. This bit has no effect in single-chip modes. 0 = PE2 is a general-purpose I/O pin 1 = PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a general-purpose I/O pin. R/W is used for external writes. After reset in normal expanded mode, it is disabled. If needed it should be enabled before any external writes.

MODC MODB MODA 0 IVIS EMK EME

7 6 5 4 3 2 1

0

0

MODC, MODB, MODA: mode select bits 000 = special single chip mode 001 = emulation narrow mode 010 = special test mode 011 = emulation wide mode 100 = normal single chip mode 101 = normal expanded narrow mode (external memory data bus is 8-bit) 110 = special peripheral mode 111 = normal expanded wide mode (external memory data bus is 16-bit)IVIS: internal visibility 0 = No visibility of internal bus operations on external bus 1 = Internal bus operations are visible on external busEMK: emulate Port K 0 = PTK and DDRK are in memory map and port K can be used in general I/ O 1 = If in any expanded mode, PTK and DDRK are removed from memory mapEME: emulate Port E 0 = PTE and DDRE are in the memory map so Port E can be used for general I/ O 1 = If in any expanded mode or special peripheral mode, PORTE and DDRE are removed from memory map and hence allows the user to emulate the function of these registers externally.

Figure 7.7 The MODE register

PUPKE 0 0 PUPEE 0 PUPBE PUPAE

7 6 5 4 3 2 1

0

0

PUPKE: pull-up Port K enable 0 = Port K pull-up resistors are disabled 1 = Port K pull-up resistors are enabledPUPEE: pull-up Port E enable 0 = Port E input pins 7 and 4-0, pull-up resistors are disabled 1 = Port E input pins 7 and 4-0, pull-up resistors are enabledPUPBE: pull-up Port B enable 0 = Port B pull-up resistors are disabled 1 = Port B pull-up resistors are enabledPUPAE: pull-up Port A enable 0 = Port A pull-up resistors are disabled 1 = Port A pull-up resistors are enabled

reset: 1 10 0 0 0 0 0

Figure 7.8 Pull-Up control register

RDPK 0 0 RDPE 0 RDPB RDPA

7 6 5 4 3 2 1

0

0

RDPK: reduced drive of Port K 0 = All Port K pins have full drive enabled 1 = All Port K pins have reduced drive enabledRDPE: reduced drive of Port E 0 = All Port E pins have full drive enabled 1 = All Port E pins have reduced drive enabledRDPB: reduced drive of Port B 0 = All Port B pins have full drive enabled 1 = All Port B pins have reduced drive enabledRDPA: reduced drive of Port A 0 = All Port A pins have full drive enabled 1 = All Port A pins have reduced drive enabled

reset: 1 10 0 0 0 0 0

Figure 7.9 Reduced Drive Register (RDRIV)

Figure 7.10 Port K pins and their alternate functions

PK0/ X14

PK1/ X15

PK2/ X16

PK3/ X17

PK4/ X18

PK5/ X19

PK6/ XCS

PK7/ ECS/ ROMONE

(only available in H sub-family)

Port K• Has PTK and DDRK

registers• Carries expanded address

XADDR14…XADDR19 in expanded mode

• On the rising edge of the RESET signal, the value of the PK7 pin is latched into the ROMON bit of the MISC register in expanded mode. If it is 1, the on-chip flash memory is enabled.– ROMON is forced to 1 in

single chip mode.

Figure 7.14 Port T pins and their alternate functions

PT0/ IOC0

PT1/ IOC1

PT2/ IOC2

PT3/ IOC3

PT4/ IOC4

PT5/ IOC5

PT6/ IOC6

PT7/ IOC7

Port T• Has Port T data register (PTT), Port T

data direction register (DDRT), Port input register (PTIT), reduced drive register (RDRT), pull device enable register (PERT), and port polarity select register (PPST)

– The PTIT register allows the user to read back the status of Port T pins.

– The RDRT register can configure the drive strength (current output) of each port pin as either full or reduced load.

– The PERT register is used to enable an input Port T pin pull-up or pull-down device.

– The PPST register selects whether a pull-down or pull-down device is connected to the pin.

• Port T pins are also used as timer input capture/output compare pin.

RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT1 RDRT0

7 6 5 4 3 2 1

RDRT2

0

RDRT[7:0]: Reduced drive Port T 0 = full drive strength at output 1 = associated pin drives at about 1/ 3 of the full drive strength

reset: 0 00 0 0 0 0 0

Figure 7.11 Port T Reduced Drive register (RDRT)

PERT7 PERT6 PERT5 PERT4 PERT3 PERT1 PERT0

7 6 5 4 3 2 1

PERT2

0

PERT[7:0]: pull device enable Port T 0 = pull-up or pull-down is disabled 1 = either pull-up or pull-down is enabled

reset: 0 00 0 0 0 0 0

Figure 7.12 Port T Pull Device Enable register (PERT)

PPST7 PPST6 PPST5 PPST4 PPST3 PPST1 PPST0

7 6 5 4 3 2 1

PPST2

0

PPST[7:0]: pull device enable Port T 0 = A pull-up device is connected to the associated ort T pin , if enabled by the associated bit in register PERT and if the port is used as input or as wired-or output 1 = A pull-down device is connected to the associated Port T pin, if enabled by the associated bit in register PERT and if the port is used as input

reset: 0 00 0 0 0 0 0

Figure 7.13 Port T Polarity Select register (PPST)

WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS1 WOMS0

7 6 5 4 3 2 1

WOMS2

0

WOMS[7:0]: Wired-or mode Port S 0 = Output buffers operate as push-pull outputs 1 = Output buffers operate as open-drain outputs

reset: 0 00 0 0 0 0 0

Figure 7.15 Port S Wired-Or Mode register (WOMS)

Figure 7.16 Port S pins and their alternate functions

PS0/ RXD0

PS1/ TXD0

PS2/ RXD1

PS3/ TXD1

PS4/ MISO0

PS5/ MOSI0

PS6/ SCK0

PS7/ SS0

Port S• Port S pins are used as general I/O, serial communication interface,

and serial peripheral interface pins.• Port S has a Port S wired-or mode register (WOMS) in addition to all

registers associated with Port T.

Figure 7.18 Port M pins and their alternate functions

PM0/ RXCAN0/ RXB

PM1/ TXCAN0/ TXB

PM2/ RXCAN1/ RXCAN0/ MISO0

PM3/ TXCAN1/ TXCAN0/ SS0

PM4/ RXCAN2/ RXCAN0/ RXCAN4/ MOSI0

PM5/ TXCAN2/ TXCAN0/ TXCAN4/ SCK0

PM6/ RXCAN3/ RXCAN4

PM7/ TXCAN3/ TXCAN4

Port M• Port M has all the

equivalent registers that Port S has and also a module routing register (MODRR). – The MODRR configures

the rerouting of CAN0, CAN4, SPI0, SPI1, and SPI2 on defined port pins.

0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR1 MODRR0

7 6 5 4 3 2 1

MODRR2

0

reset: 0 00 0 0 0 0 0

Figure 7.17 Module Routing register (MODRR)

MODRR1 MODRR0 RXCAN0 TXCAN0

CAN0 routing

0011

0101

PM0PM21

PM42

PM1PM31

PM52

reserved

MODRR3 MODRR2 RXCAN4 TXCAN4

CAN4 routing

0011

0101

PJ6PM43

PM64

PJ7PM53

PM74

reserved

MODRR4 MISO0 SS0

SPI0 routing

01

MOSI0 SCK0

PS4PM25

PS5PM46

PS6PM56

PS7PM35

MODRR5 MISO1 SS1

SPI1 routing

01

MOSI1 SCK1

PP0PH0

PP1PH1

PP2PH2

PP3PH3

MODRR6 MISO2 SS2

SPI2 routing

01

MOSI2 SCK2

PP4PH4

PP5PH5

PP7PH6

PP6PH7

Note: 1. Routing to this pin takes effect only if CAN1 is disabled. 2. Routing to this pin takes effect only if CAN2 is disabled. 3. Routing to this pin takes effect only if CAN2 disabled and CAN0 disabled if routed here. 4. Routing to this pin takes effect only if CAN3 is disabled. 5. Routing to this pin takes effect only if CAN1 disabled and CAN0 disabled if routed here. 6. Routing to this pin takes effect only if CAN2 is disabled and CAN0 disabled if routed here and CAN4 disabled if routed here

• Example 7.1 Give an instruction to configure the MODRR register to achieve the following port routing:

1. CAN0: use pins PM1 and PM02. CAN1: use pins PM3 and PM23. CAN2: use pins PM5 and PM44. CAN3: use pins PM7 and PM65. I2C: use PJ7 and PJ66. SPI0: use pins PS7~PS47. SPI1: use pins PH3~PH08. SPI2: use pins PH7~PH4

• Solution: This routing requirement can be achieved by preventing CAN4 from using any port pins and keep the default routing after reset.

-The following instruction will satisfy the requirement:

movb #$60,MODRR ; CAN4 must be disabled

• Example 7.2 Give an instruction to configure the MODRR register to achieve the following port routing:

1. CAN0: use pins PM1 and PM02. CAN1: use pins PM3 and PM23. CAN2: disabled4. CAN3: disabled5. I2C: use PJ7 and PJ66. SPI0: use pins PS7~PS47. SPI1: use pins PP3~PP08. SPI2: use pins PH7~PH4

• Solution: This routing requirement can be satisfied by the following instruction:

movb #$40,MODRR ; CAN2~CAN4 must be disabled

Port H, J, and P• These three I/O ports have the same set of registers:

– Port I/O register (PTH, PTJ, PTP)– Port Input Register (PTIH, PTIJ, PTIP)– Port Data Direction Register (DDRH, DDRJ, DDRP)– Port Reduced Drive Register (RDRH, RDRJ, RDRP)– Port Pull Device Enable Register (PERH, PERJ, PERP)– Port Polarity Select Register (PPSH, PPSJ, PPSP)– Port Interrupt Enable Register (PIEH, PIEJ, PIEP)– Port Interrupt Flag Register (PIFH, PIFJ, PIFP)

• These ports have edge-triggered interrupt capability in the wired-OR fashion.

• The SPI function pins can be rerouted to Port H and P.• The interrupt edges can be rising or falling and are programmed through

Port Device Enable Register and Port Polarity Select Register.• The Port Interrupt Register allows the user to enable interrupts on these

three ports.

PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH1 PIEH0

7 6 5 4 3 2 1

PIEH2

0

PIEH[7:0]: Interrupt enable Port H 0 = interrupt is disabled 1 = interrupt is enabled

reset: 0 00 0 0 0 0 0

Figure 7.19 Port H Interrupt Enable Register (PIEH)

PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH1 PIFH0

7 6 5 4 3 2 1

PIFH2

0

PIFH[7:0]: Interrupt flag Port H 0 = no active edge pending 1 = active edge has occurred (writing a '1' clears the associated flag)

reset: 0 00 0 0 0 0 0

Figure 7.20 Port P Interrupt Flag Register (PIFH)

Figure 7.21 Port H pins and their alternate functions

PH0/ MISO1/ KWH0

PH1/ MOSI1/ KWH1

PH2/ SCK1/ KWH2

PH3/ SS1/ KWH3

PH4/ MISO2/ KWH4

PH5/ MOSI2/ KWH5

PH6/ SCK2/ KWH6

PH7/ SS2/ KWH7

Figure 7.22 Port J pins and their alternate functions

PJ0/ KWJ0

PJ1/ KWJ1

PJ6/ KWJ6/ RXCAN4/ SDA/ RXCAN0

PJ7/ KWJ7/ TXCAN4/ SCL/ TXCAN0

Figure 7.23 Port P pins and their alternate functions

PP0/ MISO1/ PWM0/ KWP0

PP1/ MOSI1/ PWM1/ KWP1

PP2/ SCK1/ PWM2/ KWP2

PP3/ SS1/ PWM3/ KWP3

PP4/ MISO2/ PWM4/ KWP4

PP5/ MOSI2/ PWM5/ KWP5

PP6/ SS2/ PWM6/ KWP6

PP7/ SCK2/ PWM7/ KWP7

IEN7 IEN6 IEN5 IEN4 IEN3 IEN1 IEN0

7 6 5 4 3 2 1

IEN2

0

IENx: ATD digital input enable on channel x 0 = disable digital input buffer to PTADx pin 1 = enable digital input buffer to PTADx pin

reset: 0 00 0 0 0 0 0

Figure 7.24 ATD Input enable register (ATD0DIEN and ATD1DIEN)

Port AD0 and AD1• Many HCS12 devices have two 8-channel A/D converters (AD0 and

AD1).• Device that has only one 8-channel module is referred to as AD.• When A/D functions are disabled, these two ports can be used as

general input port.• These two ports do not have data direction registers.• Each module has a Digital Input Enable Register. In order to use an

A/D pin as a digital input, one needs to set its associated bit in this register.

Electrical Characteristic Consideration for I/O Interfacing

• When interfacing I/O device to the MCU, one needs to consider electrical compatibility issues.– There are two electrical compatibility issues:

• Voltage level compatibility• Current drive capability

• There are many IC technologies in use. Some are bipolar, whereas others are unipolar (mainly CMOS and BICMOS).

• Voltage parameters related to electrical compatibility– Input high voltage (VIH)– Input low voltage (VIL)– Output high voltage (VOH)– Output low voltage (VOL)

For Device X to Drive Device Y Correctly• The output high voltage of device X (VOHX) must be

higher than the input high voltage of device Y (VIHY). • The output low voltage of device X (VOLX) must be

lower than the input low voltage of device Y (VILY). • The input and output voltage levels of several popular

logic families are shown in Table 7.3. • At the same power supply level, the CMOS device has

no problem in driving the bipolar and CMOS devices.• Bipolar devices have problem in driving CMOS devices.• HCS12 cannot be driven by bipolar devices.• Bipolar devices have problems driving CMOS devices

(including HCS12).

Logic family VCC VIH VOH VIL VOL

HCS123

S4

LS4

AS4

F4

HC3

HCT3

ACT3

ABT5

BCT5

FCT5

5 V5 V5 V5 V5 V5 V5 V5 V5 V5 V5 V

3.25 V2 V2 V2 V2 V

3.5 V3.5 V2 V2 V2 V2 V

4.2 V3.0~3.4 V1

3.0~3.4 V1

3.0~3.4 V1

3.4 V4.9 V4.9 V4.9 V3 V

3.3 V2.4 V

1.75 V0.8 V0.8 V0.8 V0.8 V 1.5 V1.5 V0.8 V0.8 V0.8 V0.8 V

0.8 V0.4~0.5 V2

0.4~0.5 V2

0.35 V0.3 V0.1 V0.1 V0.1 V0.55 V0.42 V0.55 V

Notes. 1. VOH value will get lower when output current is larger. 2. VOL value will get higher when output current is larger. The VOL values of different logic gates are slightly different. 3. HCS12, HC, HCT, ACT are based on the CMOS technology. 4. S, LS, AS and F logic families are based on the bipolar technology. 5. ABT, BCT, and FCT are using the Bi-CMOS technology.

Table 7.3 Input and output voltage levels of common logic families

Current Drive Capability• The device that drives other devices must have enough sourcing

(supply current) and sinking (absorb current) capability.• Current flows out from the driving device when the driving voltage is

high.• Current flows into the driving device when the driving voltage is low.• The driving device must be able to supply (or sink) enough current

needed by those devices being driven for proper operation.• If a device cannot source or sink enough current, then using buffer

device is a common solution. • The current capabilities of a logic device are determined by the

following currents:– Input high current (IIH)– Input low current (IIL)– Output high current (IOH)– Output low current (IOL)

• The current capability of several logic chip families are shown in Table 7.4.

Logic family VCC

HCS1223

SLSASF

HC3

HCT3

ACT3

ABT3

BCTFCT3

IIH IIL IOH IOL

5 V5 V5 V5 V5 V5 V5 V5 V5 V5 V5 V

2.5 A50 A20 A20 A20 A1 A1 A1 A1 A20 A1 A

2.5 A1.0 mA0.2 mA0.5 mA0.5 mA1 A1 A1 A1 A1 mA1 A

25 mA1 mA15 mA15 mA1 mA25 mA25 mA24 mA32 mA15 mA15 mA

25 mA20 mA24 mA64 mA20 mA25 mA25 mA24 mA64 MA64 mA64 mA

Notes. 1. Values are based on the 74xx244 of Texas Instrument (xx is the technology name) 2. The total HCS12 supply current is 65 mA. 3. The values for IIH and IIL are input leakage currents.

Table 7.4 Current capabilities of common logic families1

1. The IOH of an output pin must be equal to or larger than the total current flowing into all the peripheral pins that are connected to this pin.2. The IOL of an output pin must be equal to or larger than the total current flowing out from all the peripheral pins that are connected to this pin.

D

CLK

Q

Q

Figure 7.28 D flip-flop and its latching timing requirement

(a)

D

CLK

tsu

thd

(b)

Timing Compatibility• There is no timing problem when driving a peripheral pin that does

not contain latches or flip-flops.• When driving a latch or flip-flop device, one needs to make sure that

the data set up time (tSU) and data hold time (tHD) are both satisfied.• The data setup time and data hold time requirements are illustrated

in Figure 7.28.

74HC04

VCC

Figure 7.29 An LED connected to a CMOS inverter through a current- limiting resistor.

Portpin

(a) positive direct drive(c) buffered drive

R1

R2

R3

VCC

Portpin

Portpin(b) inverse direct

drive

Interfacing with LED Devices• Figure 7.29 suggests three methods for interfacing with LEDs.• Circuit (a) and (b) are recommended for LEDs that need only small

current to light.• Circuit (c) is recommended for LEDs that need larger current to

light.

• Example 7.3 Use Port B to drive eight LEDs using the circuit shown in Figure 7.30. Light each LED for half a second in turn and repeat assuming the HCS12 has a 24-MHz E clock.

Figure 7.30 Circuit connection for example 7.3

PB3

PB2

PB1

PB0

HCS12

PB7

PB6

PB5

PB4

1.5K

- To turn on one LED at a time for half a second in turn, one should output the value $80, $40, $20, $10, $08,$04,$02, and $01 and stay for half a second in each value.

The assembly program that performs the operation is as follows:

#include "C:\miniide\hcs12.inc"org $1500movb #$FF,DDRB ; configure port B for outputbset DDRJ,$02 ; configure PJ1 pin for outputbclr PTJ,$02 ; enable LEDs to light

forever ldaa #16 ; initialize loop count to 8ldx #led_tab ; use X as the pointer to LED pattern table

led_lp movb 1,x+,PTB ; turn on one LEDldy #5 ; wait for half a secondjsr delayby100ms ; "dbne a,led_lp ; reach the end of the table yet?bra forever ; start from beginning

led_tab dc.b $80,$40,$20,$10,$08,$04,$02,$01dc.b $01,$02,$04,$08,$10,$20,$40,$80#include "C:\miniide\delay.asm"end

The C language version of the program is as follows:

#include "c:\egnu091\include\hcs12.h"#include "c:\egnu091\include\delay.c"main (void){ char led_tab[8] = {0x80,0x40,0x20,0x10,0x08,0x04,0x02,0x01,

0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80}; char i; DDRB = 0xFF; /* configure port B for output */

DDRJ |= 0x02; /* configure PJ1 pin for output (needed for DRAGON12 board only) */PTJ &= 0xFD; /* enable LEDs to light (needed for DRAGON12 board only)*/

while (1){ for (i = 0; i < 16; i++) { PTB = led_tab[i]; delayby100ms(5); } } return 0;}

BCDdigit a b c d e f g

Segments CorrespondingHex Number

0123456789

1011011111

1111100111

1101111111

1011011011

1010001010

1000111011

0011111011

$7E$30$6D$79$33$5B$5F$70$7F$7B

Table 7.5 BCD to seven-segment decoder

74H

C24

4

PB6

PB5PB4PB3PB2PB1

PB0

a

bc

defgcommon cathode

a

b

c

d

e

fg

HCS12

Figure 7.31 Driving a single seven-segment display

300 each

Driving a Single Seven-Segment Display• A common cathode seven-segment display is driven by the

74HC244 via resistors.• The output high voltage of the 74HC244 is close to 5V with a 5V

power supply.• The segment patterns for 0 to 9 are shown in Table 7.5.

.

.

.

ab

g

PB6 PB5 PB0

Figure 7.32 Port B and Port K together drive six seven-segment displays (MC9S12DP256)

. . .

. . .

. . .74HC244

HCS12

ab

g

.

.

.

commoncathode

commoncathode

commoncathode

ab

g

I MA

X =

70

mA

.

.

.

R

R

R2N2222

2N2222

2N2222

300

PK5

PK4

PK0

300

#5 #4 #0

Driving Multiple Seven-Segment Displays• Time multiplexing

technique is often used to drive multiple displays in order to save I/O pins.

• One parallel port is used to drive the segment pattern and the other port turns on one display at a time. Each display is turned on and then off many times within a second. The persistence of vision make us feel that all displays are turned on simultaneously.

#include <hcs12.inc>four equ $33 ; seven-segment pattern of digit 4

movb #$3F,DDRK ; configure PORT K for outputmovb #$FF,DDRB ; configure PORT B for outputbset PTK,$10 ; turn on seven-segment display #4bclr PTK,$2F ; turn off seven-segment displays #5, #3…#0movb #four,PTB ; output the seven-segment pattern to PORTP

In C language:DDRK = 0x3F;DDRB = 0xFF;PTK = 0x10;PTB = 0x33;

• Example 7.4 Write a sequence of instructions to display 4 on the seven-segment display #4 in Figure 7.32.

• Solution: To display the digit 4 on the display #4, we need to: – Output the hex value $33 to port B– Set the PK4 pin to 1– Clear pins PK5 and PK3...P0 to 0

- The program logic is shown in Figure 7.33.

seven-segmentdisplay

displayedBCD digit Port B Port K

#5#4#3#2#1#0

123456

$30$6D$79$33$5B$5F

$20$10$08$04$02$01

Table 7.6 Table of display patterns for Example 7.5

• Example 7.5 Write a program to display 123456 on the six seven-segment displays shown in Figure 7.32.

• Solution: Display 123456 on display #5, #4, #3, #2, #1, and #0, respectively.

• The values to be output to Port B and Port K to display one digit at a time is shown in Table 7.6.

Start

X address of display table

Output the byte at [X] to port BOutput the byte at [X]+1 to Port K

Increment X by 2Wait for 1 ms

X = display + 12?no

yes

Figure 7.33 Time-multiplexed seven-segment display algorithm

#include "c:\miniide\hcs12.inc"pat_port equ PTB ; Port that drives the segment patternpat_dir equ DDRB ; direction register of the segment patternsel_port equ PTK ; Port that selects the digitsel_dir equ DDRK ; data direction register of the digit select port

org $1500movb #$FF,pat_dir ; configure pattern port for outputmovb #$3F,sel_dir ; configure digit select port for output

forever ldx #disp_tab ; use X as the pointerloop movb 1,x+,pat_port ; output digit pattern and move the pointer

movb 1,x+,sel_port ; output digit select value and move the pointerldy #1 ; wait for 1 msjsr delayby1ms ; “ cpx #disp_tab+12 ; reach the end of the tablebne loopbra forever#include "c:\miniide\delay.asm"

disp_tab dc.b $30,$20 ; seven-segment display tabledc.b $6D,$10dc.b $79,$08dc.b $33,$04dc.b $5B,$02dc.b $5F,$01end

#include “c:\egnu091\include\hcs12.h”#include “c:\egnu091\include\delay.c”#define pat_port PTB /* segment pattern port */#define pat_dir DDRB /* pattern port data direction register */#define sel_port PTK /* digit select port */#define sel_dir DDRK /* digit select port direction register */main (void){ char disp_tab[6][2] = {{0x30,0x20},{0x6D,0x10},{0x79,0x08}, {0x33,0x04},{0x5B,0x02},{0x5F,0x01}}; char i; pat_dir = 0xFF; /* configure pat_port for output */ sel_dir = 0x3F; /* configure sel_port for output */ while (1) { for (i = 0; i < 6; i++) { pat_port = disp_tab[i][0]; /* output the segment pattern */ sel_port = disp_tab[i][1]; /* turn on the display */ delaybyms(1); /* wait for 1 ms */ } } return 0;}

Liquid Crystal Display (LCD) (1 of 2)

• The basic construction of an LCD is illustrated in Figure 7.34.

• The most common type of LCD allows the light to pass through when activated.

• An LCD segment is activated when a low frequency bipolar signal in the range of 30 Hz to 1KHz is applied to it.

• LCD can display characters and graphics.• LCDs are often sold in a module with LCDs and

controller unit built in.• The Hitachi HD44780 is the most popular LCD controller

being used today.

Segment Frontplane

Backplane

Black cardboard backingLiquid crystal

Glass

Figure 7.34 A liquid crystal display (LCD)

Liquid Crystal Display (LCD) (2 of 2)

DB7

DB0

ER/W

RSVEE

VCC

VSS

COM 16

LCDP (FRD7069)

SEG 160SEG 40

4 SEGMENT DRIVER x 4

CONTROLLERLSI

HD44780

Figure 7.35 Block diagram of a HD44780-based LCD kit

A HD44780-Based LCD Kit (1 of 3)• Display capability: 4 x 20• Uses the HD44780 as the controller as shown in Figure 7.35.• Pins DB7~DB0 are used to exchange data with the CPU.• E input should be connected to one of the address decoder output or I/O pin.• The RS signal selects instruction register (0) or data register (1).• The VEE signal allows the user to adjust the LCD contrast.• The HD44780 can be configured to display 1-line, 2-line, and 4-line information.• The pin assignment for character-based LCD module with less than and more than 80 characters

are shown in Table 7.7 and 7.8.

Table 7.7 Pin assignment for displays with less than 80 characters

Pin No. symbol I/ O Function

1234567891011121314

VSSVCCVEERS

R/ WE

DB0DB1DB2DB3DB4DB5DB6DB7

---III

I/ OI/ OI/ OI/ OI/ OI/ OI/ OI/ O

Power supply (GND)Power supply (+5V)Contrast adjust0 = instruction input, 1 = data input0 = write to LCD, 1 = read from LCDenable signaldata bus line 0data bus line 1data bus line 2data bus line 3data bus line 4data bus line 5data bus line 6data bus line 7

A HD44780-Based LCD Kit (2 of 3)

Table 7.8 Pin assignment for displays with more than 80 characters

Pin No. symbol I/ O Function

12345678910111213141516

DB7DB6DB5DB4DB3DB2DB1DB0E1

R/ WRS

VEEVSSVCCE2

N.C

I/ OI/ OI/ OI/ OI/ OI/ OI/ OI/ O

III---I-

data bus line 7data bus line 6data bus line 5data bus line 4data bus line 3data bus line 2data bus line 1data bus line 0enable signal row 0 & 10 = write to LCD, 1 = read from LCD0 = instruction input, 1 = data inputContrast adjustPower supply (GND)Power supply (+5V)Enable signal row 2 & 3

A HD44780-Based LCD Kit (3 of 3)

Table 7.9 HD44780U instruction set

InstructionCode

RS R/ W B7 B6B5 B4 B3 B2 B1B0Description Execution

time

Clear display

Cursor home

Entry mode set

Display on/ offcontrol

Cursor / displayshift

Function set

Set CGRAMaddressSet DDRAMaddressRead busy flagand addresscounter

Write CGRAMor DDRAMRead fromCGRAM orDDRAM

Clears display and returns cursor to thehome position (address 0).Returns cursor to home position (address0). Also returns display being shifted to theoriginal position. DDRAM contents remainunchanged.Set cursor move direction (I/ D), specifiesto shift the display (S). These operationsare performed during data read/ write.Sets on/ off of all display (D), cursor on/off (C) and blink of cursor positioncharacter (B).Sets cursor-move or display-(S/ C), shiftdirection (R/ L). DDRAM contents remainsunchanged.Sets interface data length (DL), number ofdisplay line (N) and character font (F).Sets the CGRAM address. CGRAM data issent and received after this setting.Sets the DDRAM address. DDRAM data issent and received after this setting.Reads busy flag (BF) indicating internaloperation is being performed and readsCGRAM or DDRAM address countercontents (depending on previousinstruction).Writes data to CGRAM or DDRAM.

Reads data from CGRAM or DDRAM.

1.64 ms

1.64 ms

40 s

40 s

40 s

40 s

40 s

40 s

0 s

40 s

40 s

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

1

BF

0

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

DL

0

0

0

1

S/ C

N

0

0

1

D

R/ L

F

0

1

I/ D

C

*

*

1

*

S

B

*

*

CGRAM address

DDRAM address

CGRAM/ DDRAMaddress

write data

read data

HD44780 Commands (1 of 4)

Bit name Settings

I/ DSDCB

S/ CR/ LDLNFBF

0 = decrement cursor position.0 = no display shift.0 = display off0 = cursor off0 = cursor blink off0 = move cursor0 = shift left0 = 4-bit interface0 = 1/ 8 or 1/ 11 duty (1 line)0 = 5x8 dots0 = can accept instruction

1 = increment cursor position1 = display shift1 = display on1 = cursor on1 = cursor blink on1 = shift display1 = shift right1 = 8-bit interface1 = 1/ 16 duty (2 lines)1 = 5 x 10 dots1 = internal operation in progress

Table 7.10 LCD instruction bit names


Table 7.11a DDRAM address usage for a 1-line LCD

Display sizeVisible

character positions DDRAM addresses

1 * 81 * 161 * 201 * 241 * 321 * 40

00..0700..1500..1900..2300..3100..39

0x00..0x070x00..0x0F0x00..0x130x00..0x170x00..0x1F0x00..0x27

• The HD44780 has a display data RAM (DDRAM) to store data to be displayed on the LCD.

• The address range of DDRAM for 1-line, 2-line, and 4-line LCDs are shown in Table 7.11a, 7.11b, and 7.11c.

• The HD44780 has a character generator ROM that can generates 5 8 or 5 10 character patterns from a 8-bit code.

• The user can rewrite character patterns into the character generator RAM (CGRAM).

• Up to eight 5 8 patterns or four 5 10 patterns can be programmed.


Table 7.11b DDRAM address usage for a 2-line LCD

Display sizeVisible


2 * 162 * 202 * 242 * 322 * 40

00..1500..1900..2300..3100..39

0x00..0x0F + 0x40..0x4F0x00..0x13 + 0x40..0x530x00..0x17 + 0x40..0x570x00..0x1F + 0x40..0x5F0x00..0x27 + 0x40..0x67

Table 7.11c DDRAM address usage for a 4-line LCD

Display sizeVisible


4 * 164 * 204 * 40

00..1500..19

00..39 on 1st controllerand 00..39 on 2nd

controller

0x00..0x0F + 0x40..0x4F + 0x14..0x23 + 0x54..0x630x00..0x13 + 0x40..0x53 + 0x14..0x27 + 0x54..0x670x00..0x27 + 0x40..0x67 on 1st controller and0x00..0x27 + 0x40..0x67 on 2nd controller


Table 7.12 Register selection

RS R/ W Operation

0011

0101

IR write as an internal operation (display clear, etc)Read busy flag (DB7) and address counter (DB0 to DB6)DR write as an internal operation (DR to DDRAM or CGRAM)DR read as an internal operation (DDRAM or CGRAM to DR)

Registers of HD44780• The HD44780 has two 8-bit user accessible registers: instruction register

(IR) and data register (DR).• To write data into display data RAM or character generator RAM, the MCU

writes into the DR register. • The address of the data RAM should be set up with a previous instruction.• The DR register is also used for data storage when reading data from

DDRAM or CGRAM.• The register selection is shown in Table 7.12.• The HD44780 has a busy flag that is output from the DB7 pin.• The HD44780 uses a 7-bit address counter to keep track of the address of

the next DDRAM or CGRAM location to be accessed.

HD44780 Instructions (1 of 3)

• Clear display– Writes 0x20 (space character) to all DDRAM locations– Sets 0 to the address counter (return cursor to upper left corner of the

LCD)– Sets increment mode

• Return home– Sets address counter to 0– DDRAM contents not changed

• Entry mode set– Sets incrementing or decrementing of the DDRAM address– Controls the shifting (shifts if S bit = 1) of the display

• Display on/off control– Turns on/off display– Turns on/off cursor– Turns on/off cursor blinking

Table 7.13 LCD Shift function

S/ C R/ L Operation

0011

0101

Shifts the cursor position to the left. (AC is decremented by 1)Shifts the cursor position to the right. (AC is incremented by 1)Shifts the entire display to the left. The cursor follows the display shift.Shifts the entire display to the right. The cursor follows the display shift.

HD44780 Instructions (2 of 3)• Cursor or display shift

– This function shifts the cursor position to the right or left without writing or reading display data.

– The shifting is controlled by two bits as shown in Table 7.13.

• Function set– Sets the interface length (DL bit) to be 4- or 8-bit– Selects the number of lines (N bit) to be one or two lines– Selects character font (F bit) to be 5 8 or 5 10

HD44780 Instructions (3 of 3)

• Set CGRAM address– This command contains the address to be written into the

address counter.

• Set DDRAM address– This command allows the user to set the starting address to

display information.

• Read busy flag and address– This command reads the busy flag and the address counter.– User can use this command to determine the LCD controller is

ready to accept another command.– User can use this command to control where to start displaying

information.

PK4

PK6

PK5

PH7...PH0 DB7..DB0

E

RS

R/ W

HD44780U-basedLCD ModuleHCS12 MCU

Figure 7.36a LCD interface example (8-bit bus, used in SSE256)

5V

VCC

VEE

GND

5V

PK0

PK1

PK5...PK2 DB7..DB4

RS

E

R/ W

HD44780U-basedLCD ModuleHCS12 MCU

Figure 7.36b LCD interface example (4-bit bus, used in Dragon12)

5V

VCC

VEE

GND

5V

Interfacing the HD44780 with the HCS12• One can treat the LCD kit as an I/O device and use an I/O port and

several other I/O pins as control signals.• The interface can be 4 bits or 8 bits. • To read or write the LCD successfully, one must satisfy the timing

requirements of the LCD. The timing diagrams for read and write are shown in Figure 7.37 and 7.38.

tAS

R/W

RS

E

DB0-DB7 Valid data

tEr

PWEH

tAH

tDDR

tCYCLE

tDHR

tEf

Figure 7.37 HD44780U LCD controller read timing diagram

tAS

R/W

RS

E

DB0-DB7 Valid data

tEr

PWEH

tAH

tDSW

tCYCLE

tH

tEf

Figure 7.38 HD44780U LCD controller write timing diagram

Table 7.15 HD44780U bus timing parameters (2 MHz operation)

MeaningSymbol

Enable cycle timeEnable pulse width (high level)Enable rise and decay timeAddress setup time, RS, R/W, EData delay timeData setup timeData hold time (write)Data hold time (read)Address hold time

tCYCLEPWEHtEr, tEftAStDDRtDSWtHtDHRtAH

Min Typ Max. Unit

500230

-40-

80105

10

---------

--

20-

160----

nsnsnsnsnsnsnsnsns

• Procedure to send a command to the IR register– Step 1

• Pull the RS and the E signals to low.– Step 2

• Pull the R/W signal to low.– Step 3

• Pull the E signal to high.– Step 4

• Output data to the output port attached to the LCD data bus. One needs to configure the I/O Port for output before writing data to the LCD kit.

– Step 5• Pull the E signal to low and make sure that the internal operation is complete.

• The procedure for writing a byte to the LCD data register

– Step 1• Pull the RS signal to high.

– Step 2• Pull the R/W signal to low.

– Step 3• Pull the E signal to high.

– Step 4• Output data to the I/O port attached to the LCD data bus.

– Step 5• Pull the E signal to low and make sure that the internal operation is

complete.

• These procedures need to be repeated once for an LCD kit with 4-bit interface.

lcdPort equ PTH ; LCD data port lcdCtl equ PTK ; LCD control portlcdE equ $80 ; E signal pin (PK7)lcdRW equ $20 ; R/W signal pin (PK5)lcdRS equ $10 ; RS signal pin (PK4); the command is contained in Acmd2lcd bclr lcdCtl,lcdRS+lcdRW ; select instruction register and Write

bset lcdCtl,lcdE ; pull the E signal highstaa lcdPort ; send the command, along with RS, E signalsnopnopbclr lcdCtl,lcdE ; pull the E signal lowbset lcdCtl,lcdRW ; pull R/W to highldy #1 ; adding this delay will complete the internaljsr delayby50us ; operation for most instructionsrts

• Write a function to send a command to the LCD kit– Most LCD commands are completed in 40 ms.– If the function waits for 40 ms after performing the specified operation,

then most commands will be completed when the function returns.– The assembly code for the 8-bit interface is as follows:

lcdDIR equ DDRHlcdCtlDIR equ DDRKopenlcd movb #$FF,lcdDIR ; configure port H for output

bset lcdCtlDir,$B0 ; configure control pins for outputldy #5 ; wait for LCD to complete internal jsr delayby100ms ; configurationldaa #$38 ; set 8-bit data, 2-line display, 5x8 fontjsr cmd2lcd ; "ldaa #$0F ; turn on display, cursor, and blinkingjsr cmd2lcd ; "ldaa #$06 ; move cursor right (entry mode set instruction)jsr cmd2lcd ; "ldaa #$01 ; clear LCD screen and return to home positionjsr cmd2lcd ; "ldy #2 ; wait until "clear display" command is completejsr delayby1ms ; "rts

• The function to configure LCD sends four commands to the LCD kit– Entry mode set– Display on/off– Function set– Clear display

putc2lcd bset lcdCtl,lcdRS ; select LCD Data registerbclr lcdCtl,lcdRW ; enable write to LCDbset lcdCtl,lcdE ; pull E to highstaa lcdPort ; send data to LCDnop ; provide enough length to E signalnop ; "bclr lcdCtl,lcdE ; pull the E signal lowbset lcdCtl,lcdRW ; pull R/W high to complete the write cycleldy #1 ; wait until the write operation isjsr delayby50us ; completerts

• Function to output a character to the LCD– The character to be output is in accumulator A.

• Function to output a string terminated by a NULL character– The string to be output is pointed to by index register X.

• Example 7.7 Write an assembly program to test the previous four subroutines by displaying the following messages on two lines:

hello world!

I am ready!

puts2lcd ldaa 1,x+ ; get one character from the stringbeq done_puts ; reach NULL character?jsr putc2lcdbra puts2lcd

done_puts rts

#include "hcs12.inc"lcdPort equ PTH ; LCD data pins (PH7~PH0)lcdDIR equ DDRH ; LCD data direction portlcdCtl equ PTK ; LCD control portlcdCtlDir equ DDRK ; LCD control port direction lcdE equ $80 ; E signal pinlcdRW equ $20 ; R/W signal pinlcdRS equ $10 ; RS signal pin

org $1500lds #$1500 ; set up stack pointerjsr openlcd ; initialize the LCDldx #msg1lcdjsr puts2lcdldaa #$C0 ; move to the second rowjsr cmd2lcd ; "ldx #msg2lcdjsr puts2lcdswi

msg1lcd fcc "hello world!"dc.b 0

msg2lcd fcc "I am ready!"dc.b 0

#include “c:\miniide\delay.asm" ; include delay routines here; include the previous four LCD functions

#define lcdPort PTH /* Port H drives LCD data pins */#define lcdDIR DDRH /* Direction of LCD port */#define lcdE 0x80 /* E signal (PK7) */#define lcdRW 0x20 /* R/W signal (PK5) */#define lcdRS 0x10 /* RS signal (PK4) */#define lcdCtlDIR DDRK /* LCD control port direction */void cmd2lcd (char cmd);void openlcd (void);void putc2lcd (char cx);void puts2lcd (char *ptr);void cmd2lcd (char cmd){ char temp; char xa, xb; lcdCtl &= ~(lcdRS+lcdRW); /* select instruction register & pull R/W low */ lcdCtl |= lcdE; /* pull E signal to high */ lcdPort = cmd ; /* output command */ xa = 1; /* dummy statements to lengthen E */ xb = 2; /* " */ lcdCtl &= ~lcdE; /* pull E signal to low */ lcdCtl |= lcdRW; /* pull R/W to high */ delayby50us(1); /* wait until the command is complete */}

void openlcd(void){ lcdDIR = 0xFF; /* configure lcdPort port for output */ lcdCtlDIR = 0xB0; /* configure LCD control pins for output */ delayby100ms(5); /* wait for LCD to become ready */ cmd2lcd (0x38); /* set 8-bit data, 2-line display, 5x8 font */ cmd2lcd (0x0F); /* turn on display, cursor, blinking */ cmd2lcd (0x06); /* move cursor right */ cmd2lcd (0x01); /* clear screen, move cursor to home */ delayby1ms (2); /* wait until "clear display" command is complete */}

void putc2lcd(char cx){ char temp; char xa, xb; lcdCtl |= lcdRS; /* select LCD data register and pull R/W high*/

lcdCtl &= ~lcdRW; /* pull R/W to low */ lcdCtl |= lcdE; /* pull E signal to high */ lcdPort = cx; /* output data byte */ xa = 1; /* create enough width for E */ xb = 2; /* create enough width for E */

lcdCtl &= ~lcdE; /* pull E to low */lcdCtl |= lcdRW; /* pull R/W signal to high */

delayby50us(1);}void puts2lcd (char *ptr){ while (*ptr) { putc2lcd(*ptr); ptr++; }}

• Write a C program to test the SSE256 LCD functions.

#include "c:\egnu091\include\hcs12.h"#include "c:\egnu091\include\delay.c"#include “c:\egnu091\include\lcd_util_SSE256.c”main (void){ char *msg1 = "hello world!"; char *msg2 = "I am ready!"; openlcd();

cmd2lcd(0x80); /* move cursor to the 1st column of row 1 */ puts2lcd(msg1); cmd2lcd(0xC0); /* move cursor to 2nd row, 1st column */ puts2lcd(msg2); return 0;}

VCC

10K

PA0

PA1PA2

PA3

PA4

PA5PA6

PA7

HCS12

Figure 7.39 Connecting a set of eight DIP switches to Port A of the HCS12

SW DIP-8

Interfacing with DIP Switches (1 of 2)

• Switches are often grouped together. It is most common to have four or eight switches in a DIP package.

• DIP switches are often used to provide setup information to the microcontroller. After power is turned on, the microcontroller reads the settings of the DIP switches and performs accordingly.

#include “c:\miniide\hcs12.inc”

movb #0,DDRA ; configure Port A for input

ldaa PTA ; read Port A

In C language:

#include “c:\egnu091\include\hcs12.h”

void main ()

{

char xx;

DDRA = 0;

xx = PTA;

}

Interfacing with DIP Switches (2 of 2)

• Example 7.9 Write a sequence of instructions to read the value from an eight-switch DIP connected to PORTA of the HCS12 into accumulator A.

• Solution

Interfacing to a Keyboard• A keyboard is arranged as an array of switches, which can be

mechanical, membrane, capacitors, or Hall-effect in construction.• Mechanical switches are most popular for keyboards.

– Mechanical switches have a problem called contact bounce. Closing a mechanical switch generates a series of pulses because the switch contacts do not come to rest immediately.

– In addition, a human cannot type more than 50 keys in a second. Reading the keyboard more than 50 times a second will read the same key stroke too many times.

• A keyboard input is divided into three steps:– Scan the keyboard to discover which key has been pressed.– Debounce the keyboard to determine if a key is indeed pressed. Both

hardware and software approaches for key debouncing are available.– Lookup the ASCII table to find out the ASCII code of the pressed key.

VDD

Set

Reset

R

R

Q

Reset Set

Q

(a) Set-reset latch

4050

R

Vout

VDD

(b) CMOS gate debouncer

VDD

Vout

H

L

Threshold level

Switch closed

(c) Integrating RC circuit debouncer

Figure 7.42 Hardware debouncing techniques

R

C

Hardware Debouncing Techniques

• SR latches• Non-inverting CMOS

gates• Integrating debouncer

Software Debouncing Technique• The most popular and simple one has been the

wait and see method.– In this method, the program simply waits for about 10

ms and reexamines the same key again to see if it is still pressed.

ASCII Code Table Lookup• The ASCII code of each key can be stored in a

table for easy look up.

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

10K

VCC

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

HCS12 MCU

Figure 7.41 Sixteen-key keypad connected to the HCS12

PA7 PA6 PA5 PA4 Selected keys

1110

1101

1011

0111

0,4,8,C,

1,5,9,D,

2,6,A,E,

and 3and 7and Band F

Table 7.16 Sixteen-key keypad row selections

Interfacing the HCS12 to a Keypad • A keypad usually consists of 12 to 24 keys and is adequate for many

applications.• Like a keyboard, a keypad also needs debouncing. • A 16-key keypad can be easily interfaced to one of the HCS12 parallel

ports.• A circuit that interfaces a 16-key keypad is shown in Figure 7.41. In this

Figure, pins PA7..PA4 each control four keys.

#include “c:\miniide\hcs12.inc"keyboard equ PTA get_char movb #$F0,DDRA ; set PA7~PA4 for output, PA3~PA0 for inputscan_r0 movb #$EF,keyboard ; scan the row containing keys 0123scan_k0 brclr keyboard,$01,key0 ; is key 0 pressed?scan_k1 brclr keyboard,$02,key1 ; is key 1 pressed?scan_k2 brclr keyboard,$04,key2 ; is key 2 pressed?scan_k3 brclr keyboard,$08,key3 ; is key 3 pressed?

bra scan_r1key0 jmp db_key0key1 jmp db_key1

• Example 7.10 Write a program to perform keypad scanning, debouncing, and returns the ASCII code in accumulator A to the caller.

• Solution– Pins PA4..PA7 each control one row of four keys.– Scanning is performed by setting one of the PA7..PA4 pins to low, the

other three pins to high and testing one key at a time.

key2 jmp db_key2key3 jmp db_key3scan_r1 movb #$DF,keyboard ; scan the row containing keys 4567scan_k4 brclr keyboard,$01,key4 ; is key 4 pressed?scan_k5 brclr keyboard,$02,key5 ; is key 5 pressed?scan_k6 brclr keyboard,$04,key6 ; is key 6 pressed?scan_k7 brclr keyboard,$08,key7 ; is key 7 pressed?

bra scan_r2key4 jmp db_key4key5 jmp db_key5key6 jmp db_key6key7 jmp db_key7scan_r2 movb #$BF,keyboard ; scan the row containing keys 89AB

bclr keyboard,$40 ; “scan_k8 brclr keyboard,$01,key8 ; is key 8 pressed?scan_k9 brclr keyboard,$02,key9 ; is key 9 pressed?scan_kA brclr keyboard,$04,keyA ; is key A pressed?scan_kB brclr keyboard,$08,keyB ; is key B pressed?

bra scan_r3key8 jmp db_key8key9 jmp db_key9

keyA jmp db_keyAkeyB jmp db_keyBscan_r3 movb #$7F,keyboard ; scan the row containing keys CDEFscan_kC brclr keyboard,$01,keyC ; is key C pressed?scan_kD brclr keyboard,$02,keyD ; is key D pressed?scan_kE brclr keyboard,$04,keyE ; is key E pressed?scan_kF brclr keyboard,$08,keyF ; is key F pressed?

jmp scan_r0keyC jmp db_keyCkeyD jmp db_keyDkeyE jmp db_keyEkeyF jmp db_keyF; debounce key 0db_key0 jsr delay10ms

brclr keyboard,$01,getc0jmp scan_k1

getc0 ldaa #$30 ; return the ASCII code of 0rts

; debounce key 1

db_key1 jsr delay10msbrclr keyboard,$02,getc1jmp scan_k2




db_key3 jsr delay10msbrclr keyboard,$08,getc3jmp scan_r1


db_key4 jsr delay10msbrclr keyboard,$01,getc4

jmp scan_k5getc4 ldaa #$34 ; return the ASCII code of 4

rtsdb_key5 jsr delay10ms

brclr keyboard,$02,getc5jmp scan_k6




db_key7 jsr delay10msbrclr keyboard,$08,getc7jmp scan_r2




db_key9 jsr delay10msbrclr keyboard,$02,getc9jmp scan_kA


db_keyA jsr delay10msbrclr keyboard,$04,getcAjmp scan_kB

getcA ldaa #$41 ; get the ASCII code of Arts

db_keyB jsr delay10msbrclr keyboard,$08,getcBjmp scan_r3

getcB ldaa #$42 ; get the ASCII code of Brts

db_keyC jsr delay10msbrclr keyboard,$01,getcCjmp scan_kD

getcC ldaa #$43 ; get the ASCII code of Crts

db_keyD jsr delay10msbrclr keyboard,$02,getcDjmp scan_kE

getcD ldaa #$44 ; get the ASCII code of Drts

db_keyE jsr delay10msbrclr keyboard,$04,getcEjmp scan_kF

getcE ldaa #$45 ; get the ASCII code of Erts

db_keyF jsr delay10msbrclr keyboard,$08,getcFjmp scan_r0

getcF ldaa #$46 ; get the ASCII code of Frts

delay10ms movb #$90,TSCR1 ; enable TCNT & fast flags clearmovb #$06,TSCR2 ; configure prescale factor to 64movb #$01,TIOS ; enable OC0ldd TCNTaddd #3750 ; start an output compare operationstd TC0 ; with 10 ms time delay

wait_lp2 brclr TFLG1,$01,wait_lp2rts

The AD7302 D/A Converter (1 of 2)

• A dual-channel 8-bit D/A converter made by Analog Devices

• The AD7302 converts an 8-bit digital value into an analog voltage.

• The block diagram is shown in Figure 7.43. The AD7302 is designed to be a memory-mapped device. The CS signal must be low for this chip to work.

• The AD7302 needs a reference voltage to operate. The reference voltage could be external one (from the REFIN pin) or the internal VDD.

• Each conversion takes about 2 ms to complete.

InputRegister

DACRegister I DAC A I/V

InputRegister

DACRegister

I DAC B I/VD7D0

A/BWRCS

PD CLR LDAC REFIN VDD DGND

AGND

VOUTA

VOUTB

AD7302

Figure 7.24 Functional block diagram of the AD7302

ControlLogic

MUX

÷2

Power OnReset

- The output from either DAC is given by

VOUTA/B = 2 × VREF × (N/256)

where, N is the digital value to be converted.

The AD7302 D/A Converter (2 of 2)

HCS12

PB7~PB0 D7..D0

WR

PDCLR

VDD

AD7302

CS

LDAC

AGND

DGND

VDD

REFIN

5V

A/B

VOUTA

VOUTB

PJ0

PJ1

Figure 7.44 Circuit connection between the AD7302 and the HCS12

Using the AD7302 to Generate Sawtooth Waveform

• Configure PB7…PB0, PJ0…PJ1 for output.• Output the digital value from 0 to 255 and repeat. For each value,

pull the PJ0 to low and then to high so that the value on pins PB7..PB0 can be transferred to the AD7302.

• Pull the signal PJ1 to low during the process.

Example 7.10 Write a program to generate a sawtooth waveform from VOUTA pin.

The assembly program is as follows:#include "c:\miniide\hcs12.inc"

org $1500movb #$FF,DDRB ; configure PORTB for outputbset DDRJ,$03 ; configure PJ1~PJ0 for outputbclr PTJ,$02 ; select VOUTA output

loop inc PORTB ; increase the output by one stepbclr PTJ,$01 ; generate a rising edge on PJ0 pinbset PTJ,$01 ; "bset PTJ,$01 ; add 9 more “bset” instructions to provide 2 msbset PTJ,$01 ; for D/A conversion to completebset PTJ,$01 ; "bset PTJ,$01 ; “bset PTJ,$01 ; “bset PTJ,$01 ; "bset PTJ,$01 ; “bset PTJ,$01 ; “bset PTJ,$01 ; “bra loop ; to complete the D/A conversionend

The C language version of the program is on next page.

#include “c:\egnu091\include\hcs12.h”void main(void){

DDRB = 0xFF; /* configure PORTB for output */DDRJ |= 0x03; /* configure pins PJ1~PJ0 for output */PTJ &= 0xFD; /* pull the signal A/B to low too select channel A */while (1) {

PTB += 1;PTJ &= 0xFE; /* generate a rising edge */PTJ |= 0x01; /* “ */PTJ |= 0x01; /* use dummy statements to provide 2 ms */PTJ |= 0x01; /* time for D/A conversion to complete */PTJ |= 0x01;PTJ |= 0x01;PTJ |= 0x01;PTJ |= 0x01;PTJ |= 0x01;PTJ |= 0x01;PTJ |= 0x01;

}}

Stepper Motor Control (1 of 7)

• It is digital in nature and provides high degree of control.• In its simplest form, a stepper motor has a permanent

magnet rotor and a stator consisting of two coils. The rotor aligns with the stator coil that is energized.

• By changing the coil that is energized, the rotor is turned.• Figure 7.45a to 7.45d illustrate how the rotor rotates

clockwise in full step.• By changing the energizing order as shown in Figure

7.46, the stepper will rotate counterclockwise in full step.

1st

2nd

C1C2

C3

C4

N S SNN S

Figure 7.45a Stepper motor full step 1

currentflow

1st

2nd

C1C2

C3

C4

S

N

N

S

Figure 7.45b Stepper motor full step 2

currentflow

N

S


1st

2nd

C1C2

C3

C4

NS S NNS

Figure 7.45c Stepper motor full step 3

currentflow

1st

2nd

C1C2

C3

C4

S

N

Figure 7.44d Stepper motor full step 4

currentflow

N

S

N

S


N

S

rotor

Step 1 Step 2

Figure 7.46 Full-step counterclockwise operation of step motor

C1C2

C3

S

NC4

S

N

rotor

C1C2

C3

SN

C4

SNN S

N

S

rotor

Step 3

C1C2

C3

S

NC4

S

N Step 4

rotor

C1C2

C3

S N

C4

S NNS


Stepper Motor Control (5 of 7)• In a four-pole stepper motor shown in Figure 7.45 & 7.46, a full step

is 90 degrees.• The stepper motor may also operate with half step. A half step

occurs when the rotor (in a four-pole step) is moved to eight discrete positions (45º).

• To operate the stepper motor in half steps, sometimes both coils may have to be on at the same time. When two coils in close proximity are energized, there is a resultant magnetic field whose center will depend on the relative strengths of the two magnetic fields.

• Figure 7.47 illustrates the half-stepping sequence. • The step sizes of the stepper motors may vary from approximately

0.72º to 90º. The most common step sizes are 1.8º, 7.5º, and 15º. • The actual stator of a real motor has more segments than previously

indicated. One example is shown in Figure 7.48.

NS

roto

r

Step

1

roto

r

Step

2

roto

r

Step

3

roto

r

Step

4

Figu

re 7

.47

Hal

f-st

ep o

pera

tion

of th

e st

eppe

r mot

or

N S

roto

r

Step

5

roto

r

Step

6

roto

r

Step

7

roto

r

Step

8

SN

NS N

S

C1

C2

C3C4

S N S N

S NC

4 C3

S N

SN

C1

C2

SN

C4 C3

SC

2N

SC

1N

NS

C1

C3

N S

SC

2N

C4

SN

C2

C1

C3

N SSNC

4

SN

C1

C3

N SNC

4S

C2

C3

C1

SN

C2

NS

C4

C3

S N

NS

SN

C1

C2

C4

NS

NS


N

SNN

SS

C1

C3

C4

C5

C6

C7

C8

S

S

N

N

Figure 7.48 Actual internal construction of step motor

rotor

C2


Stepper Motor Drivers (1 of 6)• Driving a step motor involves applying a series of voltages to the coils of the

motor. • A subset of coils is energized at a time to cause the motor to rotate one

step. The pattern of coils energized must be followed exactly for the motor to work correctly.

• A microcontroller can easily time the duration that the coil is energized, and control the speed of the stepper motor in a precise manner.

• The circuit in Figure 7.49 shows how the transistors are used to switch the current to each of the four coils of the stepper motor.

• The diodes in Figure 7.49 are called fly back diodes and are used to protect the transistors from reverse bias.

• The transistor loads are the windings in the stepper motor. The windings are inductors, storing energy in a magnetic field.

• When the current is cut off, the inductor dispenses its stored energy in the form of an electric current.

• This current attempts to flow through the transistor, reversely biasing its collector-emitter pair. The diodes are placed to prevent this current from going through the transistors.

VCC

VCC

VCC

VCC VCC

VCC

Step Motor

PP3

PP2

PP1

PP0

Figure 7.49 Driving a step motor

Q1

Q2

Q3

Q4

RR

RR

RR

RR

Stepper Motor Drivers (2 of 6)


• The normal full-step sequence shown in Table 7.17 should be used for high-torque applications.

• For lower-torque applications the half-step mode is used and its sequence is shown in Table 7.18.

• The microcontroller outputs the voltage pattern in the sequence shown in Table 7.17 or 7.18.

• Table 7.17 & 7.18 are circular. The values may be output in the order as shown in the table, which will rotate the motor clockwise; or in the reverse order, which will rotate the motor counterclockwise.

• A delay of about 5 to 15 ms is required between two steps to prevent motor from missing steps.

Table 7.17 Full-step sequence for clockwise rotation

Step

12341

Q1PP0

Q2PP1

Q3PP2

Q4PP3 value

ononoffoffon

offoffononoff

onoffoffonon

offononoffoff

10101001010101101010

Table 7.18 Half-step sequence for clockwise rotation

Step

123456781

Q1PP0

Q2PP1

Q3PP2

Q4PP3 value

onononoffoffoffoffoffon

offoffoffoffonononoffoff

onoffoffoffoffoffononon

offoffonononoffoffoffoff

101010001001000101010100011000101010


#include "c:\miniide\hcs12.inc"step1 equ $0Astep2 equ $08step3 equ $09step4 equ $01step5 equ $05step6 equ $04step7 equ $06step8 equ $02half_step movb #$FF,DDRP ; configure PTP for output

movb #step1,PTPbsr delay10msmovb #step2,PTPbsr delay10msmovb #step3,PTPbsr delay10msmovb #step4,PTP

Stepper Motor Drivers (5 of 6)• Example 7.11 Assuming that pins PP3...PP0 are used to drive the four

transistor in Figure 7.30, write a subroutine to rotate the stepper motor clockwise one cycle using the half-step sequence.

• Solution:

movb #step5,PTPbsr delay10msmovb #step6,PTPbsr delay10msmovb #step7,PTPbsr delay10msmovb #step8,PTPbsr delay10msmovb #step1,PTPbsr delay10msrts

; the following subroutine waits for 10 msdelay10ms movb #$90,TSCR1 ; enable TCNT & fast flags clear

movb #$06,TSCR2 ; configure prescale factor to 64bset TIOS,IOS0 ; enable OC0ldd TCNTaddd #3750 ; start an output compare operationstd TC0 ; with 10 ms time delay10ms

wait_lp2 brclr TFLG1,$01,wait_lp2rtsend


Key Wakeups• Many embedded products are powered by battery. To lengthen the

battery life, most microcontrollers have incorporated power-saving modes such as the WAIT, STOP modes.

• All HCS12 members have incorporated the key wakeup feature which would wake up the CPU when keys connected to certain input ports are pressed.

• After entering the wait or stop mode, the MCU will be interrupted when one of these pins is pressed.

• The port H, J, and P of the HCS12 have implemented the key-wakeup function.

• The user selects the active edge for wakeup by programming the port device enable register and the port polarity select register.

• The port interrupt enable register and the interrupt flag register together allow the user to wake up the MCU.

Key Wakeup Initialization• Step 1

– Set the direction of the key wakeup bits to input by writing zeros to the data direction register.

• Step 2– Select the rising edge or the falling edge of the wake up pin to interrupt the MCU

by programming the related registers.• Step 4

– Write the service routine for the key wakeup interrupt and initialize the key wakeup interrupt vector.

• Step 5– Clear any flags that have been set in the key wakeup flag register.

• Step 6– Enable the key wakeup function by setting the appropriate bits in the wakeup

interrupt enable register.• Step 7

– Clear the global interrupt mask (the I bit of the CCR register).

Considerations of the Key Wakeup Application

• Many applications are designed to be a wait loop that waits for the user to request for service.

– When a request is entered, the application calls an appropriate routine to provide the service. After the service is done, the routine returns to the wait loop.

• After the completion of a service to a user request, the application software starts a timer.

• If the user enters another command before the timer times out, the application software resets the timer and responds to the user request.

• If the timer times out before the user makes another service request, the application software puts the microcontroller in low power mode to save power.

• Whenever the user presses a key, an interrupt is generated to wake up the microcontroller.

• The service routine for the key interrupt simply clears the key wakeup flag and returns to the wait loop.

• Since we can choose either the rising or the falling edge to interrupt the CPU, the choice is based on whether there is pull-down or pull-up device inside the chip.

• If the MCU has internal pull down device, then choose the rising edge as the active edge. Otherwise, choose the falling edge as the active edge.

Start

Perform reset initialization

Perform key wakeup initialization

Enable key wakeup interrupt

Start a timer

User service request? Service the requestyes

no

Timer times out?no

yes

Enter low power mode(execute STOP or WAI instruction)

Key wakeup interrupt?

no

yes

Figure 7.51 Logic flow of embedded applications that incorporate key wakeup feature

Stay in low power mode

implemented inhardware

after servicing the interrupt

#include “c:\miniide\hcs12.inc”…bclr DDRP,$F0 ; configure PP<7:4> pins for inputbset PERP,$F0 ; enable PP7~PP4 pins’ pull devicebclr PPSP,$F0 ; choose pull-up devicemovb #$FF,PIFP ; clear the Port P key wakeup flagsbset PIEP,$F0 ; enable Port P interruptcli ; enable key wakeup interrupt globally

• Example 7.13 Write an instruction sequence to configure Port P upper four pins for wakeup feature. Program the Port P so that pins PP7...PP4 generate interrupt whenever there is a falling edge applied to any one of these four pins.

• Solution:

chapter 7 parallel ports

Documents

interface peripheral

io deviceseach interface

interface chip latches

interface chip places

interface chip interrupts

new data

data timing

data register