chapter 7: parallel i/o ports

H. Huang Transparency No.7-1

The 68HC11 Microcontroller

Chapter 7: Parallel I/O Ports


Han-Way Huang

Minnesota State University, Mankato



Basic I/O Concepts

Peripheral devices

Pieces of equipment that exchange data with a computer. Examples include switches, light-emitting diodes, cathode-ray tube screens, printers, modems, keyboards, and disk drives.

Interface (peripheral) chip

- A chip whose function is to synchronize data transfer between the CPU and I/O devices.

- An interface may consist of control registers, status registers, data directionlatches, and control circuitry.

- An interface chip has pins that are connected to the CPU and I/O port pins thatare connected to the I/O devices.

- Each interface chip has a chip enable signal input or inputs, when asserted, allowthe interface chip to react to the data transfer request.

- Data transfer between an I/O device and the CPU can be proceeded bit-by-bit or in multiple bits.



Microprocessor

Addressdecoder

Data Bus

R/W CE

Address Bus

To outputdevice

From inputdevice

CE CE CEinterface

chip 2interface

chip 1ROMRAM

Figure 7.1 A simple computer with RAM, ROM, and input and output ports



I/O Schemes

1. Isolated I/O scheme

- The microprocessor has dedicated instructions for I/O operations- The microprocessor has a separate address space for I/O devices

2. Memory-mapped I/O scheme

- The microprocessor uses the same instruction set for I/O operations- The I/O devices and memory components are resident in the same memory space



I/O Transfer Synchronization

The role of an interface chip

1.Synchronizing data transfer between CPU and interface chip.2. Synchronizing data transfer between interface chip and I/O device.

MicroprocessorControl signals

(such as R/W orinterrupt)

Interface chip

handshake orstrobe signal I/O device

electronics

Data Bus

Dat

a B

us

Figure 7.2 The role of an interface chip



Synchronizing the Microprocessor and the Interface Chip

The polling method

1. for input -- the microprocessor checks a status bit of the interface chip to find out if the interface chip has received new data from the input device.

2. for output -- the microprocessor checks a status bit of the interface chip to find out if it can send new data to the interface chip.

The interrupt-driven method

1. for input -- the interface chip interrupts the microprocessor whenever it has received newdata from the input device.

2. for output -- the interface chip interrupts the microprocessor whenever it can accept new data from the microprocessor.



Synchronizing the Interface Chip and the I/O Devices

Brute-force method -- useful when the data timing is unimportant

1. for input -- nothing special is done. The microprocessor reads the interface chip and theinterface chip returns the voltage levels on the input port pins to the microprocessor.

2. for output -- nothing special is done. The interface chip places the data that it receivedfrom the microprocessor directly on the output port pins.

The strobe method -- a strobe signal is used to indicate that data are stable on I/O port pins

1. for input -- the interface chip latches the data into its data register using the strobe signal.2. for output -- the interface chip places the data on port pins that it received from the

microprocessor and asserts the strobe signal. The output device latches the data using the strobe signal.

The handshake method -- used when timing is crucial

- two handshake signals are used to synchronize the data transfer. One signal, call it H1,is asserted by the interface chip. The other signal, call it H2, is asserted by the I/O device.

- two handshake modes are available -- pulse mode and interlocked mode.



Input Handshake Protocol

Step 1. The interface chip asserts (or pulses) H1 to indicate its intention to input data.Step 2. The input device puts data on the data port pins and also asserts (or pulses) the

handshake signal H2.Step 3. The interface chip latches the data and de-asserts H1. After some delay, the input

device also de-asserts H2.

Valid Data

H1

Data

H2

(a) Interlocked

H1

H2

Data Valid Data

(b) Pulse mode

Figure 7.3 Input Handshakes



Output Handshake Protocol

Step 1. The interface chip places data on the port pins and asserts (or pulses) H1 to indicatethat it has valid data to be output.

Step 2. The output device latches the data and asserts (or pulses) H2 to acknowledge thereceipt of data.

Step 3. The interface chip de-asserts H1 following the assertion of H2. The output devicethen de-asserts H2.

Valid Data

(a) Interlocked

H1

H2

Data

Valid Data

(b) Pulse Mode

H1

H2

Data

Figure 7.4 Output Handshaking



68HC11 Parallel I/O Overview

- The 68HC11A8 has 40 I/O pins that are arranged in five I/O ports.- All I/O pins serve multiple functions.- Ports A, B, and E with the exception of port A pin 7 are fixed-direction inputs or outputs.- Ports C and D are bi-directional I/O pins under the control of their associated data

direction registers. - Port C, port B, the STRA pin, and the STRB pin are used for strobed and handshake

parallel I/O, as well as for general-purpose I/O.

Port Registers

- To input, the 68HC11 reads from the port data register- To output, the 68HC11 writes into the port data register- All except port C have one data register:

PORTA (at $1000)PORTB (at $1004)PORTC (at $1003)PORTCL (at $1005)PORTD (at $1008)PORTE (at $100A)



Fixed Direction I/O (ports A, B, and E)

To input from an input port, execute a load instruction with the port data register as the source operand. For example, the following instruction sequence reads a byte from port E:

REGBAS equ $1000 ; I/O register block base addressPORTE equ $0A ; offset of port E data register from REGBAS

ldx #REGBASldaa PORTE,X

To output a byte to an output port, write to the port data register directly. Forexample, the following instruction sequence outputs the value #$38 to port B:

REGBAS equ $1000 ; I/O register block base addressPORTB equ $04 ; offset of port B data register from REGBAS

ldx #REGBASldaa #$38staa PORTB,X



Bi-directional I/O (Ports C and D)

- Each pin of ports C and D has an associated bit in a specific data register and another in adata direction register.

- The primary direction of a pin is set by its associated bit in the data direction register.- When an output pin is read, the value at the input to the pin driver is returned.- The data direction registers are cleared by reset to configure all bi-directional I/O pins for

input.- Before performing I/O operation to these two ports, the software should set up the

data direction registers of these two ports.



Example 7.1 Write an instruction sequence to output the value $CD to port D.Solution:

REGBAS equ $1000PORTD equ $08DDRD equ $09

ldx #REGBASldaa #$3F ; set up the directions of port D pinsstaa DDRD,X ; “ldaa #$CD ; output $CD to port Dstaa PORTD,X ; “

In C language,

DDRD = 0x3F; /* configure port D for output */PORTD = 0xCD; /* output data to port D */



Parallel I/O Control Register (PIOC)

- All strobed mode I/O and handshake I/O are controlled by this register

7 6 5 4 3 2 1 0

STAF STAI CWOM HNDS OIN PLS EGA INVB

value afterreset

0 0 0 0 0 U 1 1

STAF: Strobe A flag . This bit is set when a selected edge occurs on theSTRA signal.

STAI: Strobe A interrupt enable . When the STAF and STAI bits areboth equal to 1, a hardware interrupt request will be made to theCPU.

CWOM: Port C wired-or mode .0: All port C outputs are normal CMOS outputs.1: All port C outputs act as open-drain outputs.

HNDS: Handshake/simple strobe mode select0: simple strobe mode1: handshake mode

OIN: Output/input handshake0: input handahske1: output handshake

PLS: Pulse/interlocked handshake operation0: interlocked handshake selected1: pulse handshake selected

EGA: Active edge for STRA0: falling edge1: rising edge

INVB: Invert STRB0: STRB active low1: STRB active high

Figure 7. 5 PIOC register

PIOCat $1002



Strobe Input Port C

- Strobe mode I/O is selected when the bit 4 of the PIOC register is set to 0 and portC becomes a strobe input port.

- The bit 1 of the PIOC register selects the active edge of the STRA pin.- The active edge of the STRA signal latches the values of the port C pins into the

PORTCL register.- Reading the PORTC register returns the current values on the port C pins.- Reading the PORTCL register returns the contents of the latched PORTCL.- When enabled, the active edge of the STRA signal will generate an interrupt to the

68HC11.

t IHt IS

STRA

PORTC

t IS : input setup time (60 ns at 2 MHz)t IH : input hold time (100 ns at 2 MHz)

Figure 7.7 Port C strobed input timing (Redrawn with permission of Motorola)



Strobed Output Port B

The strobe signal STRB is pulsed for two E clock cycles each time there is a write to port B.

tPWD : peripheral data write delay time

tDEB

MCU write to PORT B

E

PORT B

STRB

previous port data new port data

for 2 E cycles

tDEB : E fall to STRB valid delay time

Figure 7.8 Port B strobe output timing (Redrawn with permission of Motorola)

tPWD



Port C Input Handshake Protocol

- STRA is a latch command asserted by an input device (active edge is rising in the figure).- STRB is a ready output driven by the 68HC11 (active high in the figure).- When ready for accepting new data, the 68HC11 asserts (or pulses) STRB pin.- The input device places data on input port pins and asserts the STRA signal. The active

edge of STRA latches data into the PORTCL register, sets the STAF flag in PIOCregister and de-asserts the STRB signal. The de-assertion of STRB inhibits external devicefrom strobing new data into port C.

- Not until the 68HC11 reads PORTCL, new data cannot be applied on port C pins.

t IS

t IH

tAES

tDEB

ReadPORTCL

tDEB : E fall to STRB delaytAES : STRA asserted to E fallt IS : port C data setup timet IH : port C data hold time

Figure 7.9 Port C Interlocked input handshaking (Redarwn with permission of Motorola)

E

STRB

STRA

PORTC

"READY"



Port C Output Handshake Protocol

- STRA is an acknowledge input (driven by the external device)- STRB is a ready output (driven by the 68HC11)- In this figure, the active edge of STRA is rising and the active level of STRB is high.- The 68HC11 writes data into PORTCL and then asserts STRB to indicates there are valid

data on port C pins- The external device then asserts STRA to acknowledge the receipt of data which will then

cause STRB to be de-asserted and the STAF flag to be set.- After the de-assertion of STRB, STRA is also de-asserted.

tPWD

tDEB

tAES

tDEB"READY"

WRITEPORTCL

E

PORT C

STRB

STRA

tPWD: Peripheral data write delay time, 150 ns max (at 2 MHz)tDEB : E fall to STRB delay, 225 ns (at 2 MHz)tAES : STRA asserted to E fall setup time, 0 ns (at 2 MHz)

Figure 7.10 Port C interlocked output handshake timing (Redrawn with permission of Motorola)



Simple Input Devices: switches, analog-to-digital converter, keyboards, etc.

Example 6.2 Connect an 8-DIP switch to port E of the 68HC11 and read a byte from it.

Solution:

REGBAS equ $1000PORTE equ $0A

LDX #REGBASLDAA PORTE,X...

In C#include <stdio.h>main (){

char xx;…xx = PORTE;…

}

V CC

10K

PE0PE1PE2PE3

PE4PE5PE6PE7

68HC11

Figure 7.11 Connecting a set of eight DIP switches to port E of the 68HC11

SW DIP-8



Interfacing Parallel Ports to the Keyboard

- A keyboard is arranged as an array of switches, which can be mechanical, membrane, capacitive, or Hall-effect in construction.

- In mechanical switches, two metal contacts are brought together to complete a circuit.- Mechanical switches have a problem called contact bounce. A series of pulses are

generated because the switch contacts do not come to rest immediately.- The response time of the switch is several orders of magnitude slower than that of a

computer.- A debouncing process is needed to solve the contact bounce problem.

Keyboard input procedure

Step 1. Keyboard scanning to find out which key has been pressed.Step 2. Key debouncing to make sure a key was pressed.Step 3. Table lookup to find the ASCII code of the key that has been pressed.

V CC5 to 20 ms

H

L

Active low outputFigure 7.12 Contact bounce

to computer



Keyboard Scanning Techniques- A keyboard with more than a few keys is often arranged as a matrix of switches that

uses two decoding and selecting devices to determine which key was pressed.- An example of 64-key keyboard is shown in Figure 7.13.- The MC14051 is an analog multiplexor and is used to select the row. - The 74LS138 selects the column.- PC5-PC3 select the row and PC2-PC0 select the column to be scanned.- X7-X0 are pulled up to 5 V by the pull-up resistors.- The decoder 74LS138 outputs are asserted low.- A pressed key will send a low to the X output to the port C pin 7 and hence can be detected.

MC14051

inhibit

X

CBA

PC0

PC1

PC2

PC3PC4PC5

PC7

68HC11

X7X6X5X4X3X2X1X0

Figure 7.13 Keyboard structure

5V

10K each

74LS138

A

B

C



Keyboard Scanning Algorithm

- The basic algorithm is shown in Figure 7.14.

- Since we use port C pin 0 to 2 to select the column and pin3 to 5 to select the row, we can use the INC PORTC,Xinstruction to move to the next key. This is done in theprogram on next page.

Start

i = 0j = 0

Is key(i,j) pressed?yes Keyboard

debouncing

no

yes

i = 0j = 0

j = 7?

i = 7?

yes

j = j + 1

i = i + 1j = 0

Figure 7.14 Flowchart for keyboard scanning for the circuit in Figure 7.13

no

no



The program to scan the keyboard in Figure 7.13

Pins PC7 should be configured for input while PC5-PC0 should be configured for output.

REGBAS equ $1000 ; base address of I/O register blockDDRC equ $07 ; offset of port C data direction register from REGBASKEYBD equ $03 ; port C is used as keyboard

ldaa #$3F ; set up port C pin directionsstaa DDRC,X ; “

resetc clr KEYBD,X ; start from row 0 and column 0scan brclr KEYBD,X $80 debnce ; detect a pressed key

brset KEYBD,X $3F resetc ; need to reset the row and column countinc KEYBD,X ; check the next row or columnbra scanend



Keyboard Debouncing

- The signal output from the key switch fallsand rises a few times within a period of5 ms as the contact bounces.

- A human being cannot press and release akey in less than 20 ms, a debouncer will recognize that the switch is closed/openafter the voltage is low/high for 10 ms.

- Both hardware and software debouncing techniques are available.

Hardware debouncing techniques

1. Set-reset flip-flops2. Non-inverting CMOS gates

with high-input impedance3. Integrating debouncers

V DD

Set

Reset

R

R

Q

Reset

Set

Q

(a) Set-reset latch

4050

R

V out

V DD

(b) CMOS gate debouncer

V DD

V out

H

L

Threshold level

Switch closed

(c) Integrating RC circuit debouncer

Figure 7.15 Hardware debouncing techniques

R

C



Software Debouncing Techniques

The easiest software debouncing technique is the wait-and-see technique. After detecting a key switch has been pressed, this technique simply wait for 10 ms and recheck the samekey.

REGBAS equ $1000 ; base address of the I/O register blockKEYBD equ $03 ; offset of PORTC from REGBASTEN_MS equ 2000 ; loop count for creating 10 ms delay

debnce ldy #REGBASldx #TEN_MS

wait10ms nop ; wait for 10 msnop ; “dex ; “bne wait10ms ; “ldaa KEYBD,X ; recheck the pressed keybmi scan ; rescan the keyboard if the key is not pressedjmp getcode ; the key switch is indeed pressedend



ASCII Code Table Lookup

After the key has been debounced, the keyboard should look up the ASCII table and sendthe corresponding ASCII code to the CPU.

keytab FCC “0123456789”FCC ......FCC …

getcode LDX #REGBASLDAB KEYBD,XCLRAANDB #$3f ; compute the address of the ASCII code of the pressedADDD #keytab ; key and leave it in XXGDX ; “LDAA 0,X ; get the ASCII codeEND



Example 7.3 Write a C routine to read a character from the keyboard. This routine will perform keyboard scanning, debouncing, and ASCII code lookup and return the ASCII codeto the caller.Solution:

char get_ascii ();void delay10ms ();char tab[64] = {….}; /* ASCII code table */

char read_kb (){

char scanned, pressed;scanned = 0;PORTC = 0;while (1) {

while (!scanned) {if (PORTC & 0X80) {/* If key is not pressed */

if ((PORTC & 0x3F) == 0x3F) /* read row 7 and column 7 */PORTC = 0x00; /* reset to row 0 column 0 */

elsePORTC ++; /* scan the next key */

}



elsescanned = 1; /* detect a pressed key */

}delay10ms (); /* wait for 10 ms to recheck the same key */if (!(PORTC &0x80))

return (get_ascii ()); /* the key is really pressed */else {

scanned = 0;}

}}/* the following subroutine use OC2 function to create a 10 ms delay */void delay10ms (){

TFLG1 = 0x40; /* clear OC2F */TOC2 = TCNT + 20000; /* start an OC2 operation to create 10 ms delay */while (!(TFLG1 & 0x40));/* wait until 10 ms is over */

}char get_ascii (){

char i;i = PORTC & 0x3F; /* obtain the row and column number for table lookup */return tab[i];

}



Interfacing 68HC11 with a Keypad

- People are using 12- to 24-key keypad for many applications.- An example of 16-key membrane keypad is shown in Figure 7.16. The row selection is

shown in Table 7.4.

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

10K

V CC

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

68HC11

Figure 7.16 Sixteen-key keypad connected to 68HC11

PC7 PC6 PC5 PC4 Selected keys

1110

1101

1011

0111

0,4,8,C,

1,5,9,D,

2,6,A,E,

and 3and 7and Band F

Table 7.4 Sixteen-key keypad row selections



Example 7.4 Write a C program to read a character from the keypad shown in Figure 7.16.This program will perform keypad scanning, debouncing, and ASCII code lookup.Solution:void wait_10ms ( );char get_key ( ){

DDRC = 0xF0; /* configure PC7-PC4 for output and PC3-PC0 for input */while (1){

PORTC = 0xE0; /* prepare to scan the row controlled by PC4 */if (!(PORTC & 0x01)) {

wait_10ms ( ):if (!(PORTC & 0x01))

return 0x30; /* return ASCII code of 0 */}if (!(PORTC & 0X02)) {


return 0x31; /* return ASCII code of 1 */}



if (!(PORTC & 0X04)) {wait_10ms ( ):if (!(PORTC & 0x04))



return 0x33; /* return ASCII code of 3 */}PORTC = 0xD0; /* set PC5 to low to scan second row */if (!(PORTC & 0X01)) {










return 0x37; /* return ASCII code of 7 */}PORTC = 0xB0; /* set PC6 to low to scan the third row */if (!(PORTC & 0X01)) {








return 0x41; /* return ASCII code of A */}if (!(PORTC & 0X08)) {


return 0x42; /* return ASCII code of B */}PORTC = 0x70; /* set PC7 to low to scan the fourth row */if (!(PORTC & 0X01)) {


return 0x43; /* return ASCII code of C */}if (!(PORTC & 0X02)) {


return 0x44; /* return ASCII code of D */}




return 0x45; /* return ASCII code of E */}if (!(PORTC & 0X08)) {


return 0x46; /* return ASCII code of F */}

}}



Simple Output Devices

A Single Light-Emitting Diode (LED)

- An LED will illuminate when it is forwardbiased and has enough current flowing through it.

- The current required to light an LED brightlyranges from a few mA to more than ten mA.

- The voltage drop across a forward-biased LED ranges from 1.7V to more than 2 V.

- The voltage drop across the LED with 10 mAcurrent flowing through it is assumed to be 1.7V in this chapter.

- In Figure 7.17, the 74HC04 has an high output4.9V and a low output 0.1V. A high applied tothe input of 74HC04 will light the LED.

- The 68HC11 does not have the current capabilityto drive the LED. A chip like the 74HC04 is neededto provide the required current capability.

74HC04 300

5V

Figure 7.17 A simple LED connected to a CMOS inverterthrough a current-limiting resistor



Example 7.5 Use the 68HC11 port B pins PB3, PB2, PB1, and PB0 to drive blue, green, red,and yellow LEDs. Light the blue LED for 2 s, then the green LED for 4 s, then the red LEDfor 8 s, and finally the yellow LED for 16 seconds. Repeat this operation forever.Solution:The circuit is shown in Figure 7.18.

5V 5V 5V 5V68HC11

PB3

PB2

PB1

PB0

300 300 300 300 74HC04

74HC04

74HC04

74HC04

Figure 7.18 LEDs circuit connection

blue green red yellow

- To light the blue LED, output $08 to port B.

- To light the green LED,output $04 to port B.

- To light the red LED,output $02 to port B.

- To light the yellow LED,output $01 to port B.

- The required time can be created byrepeating the following delay loopfor 20, 40, 80, and 160 times:

ldx #20000tenth_s nop

nopdexbne tenth_s



regbas equ $1000portb equ $04

org $00lt_tab fcb 20,$08,40,$04,80,$02,160,$01

org $C000loop ldy #lt_tabnext ldab 0,Y ; get the repetition count

ldaa 1,Y ; get the light patterninyinyldx #regbasstaa portb,X

pt_lp ldx #20000tenth_s nop

nopdexbne tenth_sdecbbne pt_lpcpy #lt_tab+8 ; reach the table end?bne nextbra loopend

The Program:



The Seven-Segment Display

- A seven-segment display consists of seven LED segments (a, b, c, d, e, f, and g).- A seven-segment display can be found in common-cathode or common-anode type.

a

b

c

d

e

fg

h

common cathode

a b c d e f g h

(b) Common-cathode seven-segment display

Common anode

a b c d e f g h

(c) Common-anode seven-segment display

Figure 7.19 Seven-segment displays

(a) seven-segment display



Driving the seven-segment displays with the 68HC11 parallel ports

- A segment requires 10 mA to belighted brightly.

- A buffer chip like 74ALS244 canbe used to boost the 68HC11’s current capability.

- The 74ALS244 has a 3V output when it is high and a 0.2V output when it is low.

- For the circuit shown in Figure 7.20, asegment will have a current of 13 mA whenit is lighted.

- To display a BCD digit, an appropriatevalue must be written to the port register.The value is listed in Table 7.6.

- When multiple digits are to be displayed,the multiplexing technique is often used toreduce the number of port pins required.

74A

LS2

44

PB6PB5PB4PB3PB2PB1

PB0

a

bc

defg

common cathode

a

b

c

d

e

fg

68HC11

Figure 7.20 Driving a single seven-segment display

100 each

BCDdigit a b c d e f g

Segments CorrespondingHex Number

0123456789

1011011111

1111100111

1101111111

1011011011

1010001010

1000111011

0011111011

$7E$30$6D$79$33$5B$5F$70$7F$7B

Table 7.6 BCD to seven-segment decoder



Using Multiplexing Method to Display Multiple BCD Digits

- The 2N2222 can sink 100-300 mA of current and can handle the maximum current (91 mA)flowing into the collector from the common cathode.

- To light seven-segment display #5, send out the segment pattern to port B and output thevalue $20 to port D.

- To light display #4, send out the segment pattern to port B and output the value $10 to port D.- etc.

.

.

.

ab

g

PB6 PB5 PB0

Figure 7.21 Port B and port D together drive six seven-segment displays

. . .

. . .

. . .74ALS244

68HC11

ab

g

.

.

.

commoncathode

commoncathode

commoncathode

ab

g

I MA

X =

70

mA

.

.

.

R

R

R 2N2222

2N2222

2N2222

100

PD5

PD4

PD0

100

#5 #4 #0



How the Multiplexing Method Works

- To light the display #5,…,#0, the corresponding value to be written into port D are $20, $10, $08, $04, $02, and $01 respectively. For example, the following instruction sequence will display the digit 6 on the display #3:

REGBAS equ $1000 ; base address of I/O register blockPORTB equ $04 ; offset of PORTB from REGBASPORTD equ $08 ; offset of PORTD from REGBASDDRD equ $09 ; offset of DDRD from REGBASsix equ $7D ; segment pattern of 6third equ $08 ; value to allow display #3 to lightoutput equ $3F

org $C000ldx #REGBASldaa #output ; configure port D for output staa ddrd,X ; “ldaa #six ; send the segment pattern of 6 to port Bstaa PORTB,X ; “ldaa #third ; select display #3 to be lightedstaa PORTD,X ; “end



In C language,

DDRD = 0x3F;PORTB = 0x5F;PORTD = 0x08;

Principle of Multiplexing multiple displays: Persistence of vision.

As long as one and only one display is lighted and then turned off for a short period of time within one second all digits will appear to be lighted simultaneously.



Example 7.6 Display 123456 on the six seven-segment displays shown in Figure 7.21.Solution: The first step is to build a table of segment patterns (to port B) and display selection values (to port D).

This Table can be set up by the following assembler directives:

org $00display FCB $06,$20

FCB $5B,$10FCB $4F,$08FCB $66,$04FCB $6D,$02FCB $7D,$01

Seven-segmentdisplay

DisplayedBCD digit

Port B Port D

#5#4#3#2#1#0

123456

$30$6D$79$33$5B$5F

$20$10$08$04$02$01

Table 7.7 Table of display patterns for example 7.6



Start

Y address of display

Write the byte at Y to port BWrite the byte at Y+1 to port D

Increment Y by 2Wait for 1 ms

Y = display + 12?no

yes

Note: display is the label of the display tableFigure 7.22 Time-multiplexed seven-segment display algorithm

Algorithm for Displaying Multiple Digits Using Time Multiplexing Technique



regbas equ $1000PORTB equ $04PORTD equ $08DDRD equ $09output equ $3F

org $00display fcb $06,$20

fcb $5B,$10fcb $4F,$08fcb $66,$04fcb $6D,$02fcb $7D,$01

org $C000ldx #regbasldaa #outputstaa ddrd,X

forever ldy #displaynext ldaa 0,Y

ldx #regbasstaa PORTB,X

ldaa 1,Ystaa PORTD,Xinyinyldx #200 ; loop to delay for 1 ms

again nop ; “nop ; “dex ; “bne again ; “cpy #display+12 ; end of table?beq foreverbra next ; light the next displayend



C language version

#include <hc11.h>char display [6][2] = {{0x30, 0x20}, {0x6D, 0x10}, {0x79, 0x08}, {0x33, 0x04},

{0x5B, 0x02}, {0x5F, 0x01}};void delay_1ms ( );main ( ){

int i;while (1) {

for (i = 0; i < 6; i++) {PORTB = display[i][0];PORTD = display[i][1];delay_1ms ( );

}}

void delay_1ms ( ){

TFLG1 = 0x40; /* clear OC2F flag */TOC2 = TCNT + 2000;while (!(TFLG1 & 0x40));

}



Liquid Crystal Displays (LCD)

- An LCD must be activated in orderto be lighted.

- The LCD type of display that is most common today allows light topass through it when it is activated.

- The LCD displays are organized as segments for displaying digits or characters.

- Activation of a segment requires a low-frequency bipolar excitationvoltage of 30-1000 Hz.

- When a voltage is placed acrossthe segment, an electric field isset up which aligns the crystals inthe liquid. This alignment allowsthe light to pass through.

- A segment which is not alignedwill reflect the light.

- The LCD has very high contrast andcan be seen extremely well in very bright light.

Segment Frontplane

Backplane

Black cardboard backingLiquid crystal

Glass

Figure 7.23 A liquid crystal display (LCD)

- The main problem of LCD is that it requireslight source in dim or dark area because itproduces no light of its own.



Optrex DMC-20434 LCD Kit

- 4 20 LCD kit that uses Hitachi HD44780 as its display controller.- Can be used with all demo boards manufactured by Axiom Manufacturing.- DB7-DB0 are used to exchange data with the microcontroller.- E pin is the enable signal to the LCD.- RS selects the signal to be accessed.- In CMD-11A8, the address $B5F0 is assigned to the control register and the address $B5F1 is

assigned to data register.

DB7

DB0

ER/W

RSV EE

V CC

V SS

COM 16

LCDP (FRD7069)

SEG 160SEG 40

4 SEGMENT DRIVER x 4

CONTROLLERLSI

HD44780

Figure 7.24 Block diagram of the DMC-20434 LCD kit



The Setup of the DMC-20434 LCD kit

- All LCD kits need to be set up before they can be used.- To set up the LCD kit, we need to write appropriate commands into the command register.- Commands for the LCD kit are listed in table 7.8.

Command

Clear display, set cursor to homeSet cursor to homeEntry mode:

cursor decrement, shift offcursor decrement, shift oncursor increment, shift offcursor increment, shift on

Display control:display, cursor, and cursor blink offdisplay on, cursor and cursor blink offdisplay and cursor on, cursor blink offdisplay, cursor, and cursor blink on

Cursor/Display shift:cursor shift leftcursor shift rightdisplay shift leftdisplay shift left

Display function (default 4x20)Character generator RAM address setDisplay RAM address set

(4 x 20 display = $80-$CF)

Data Time delay

$01$02

$04$05$06$07

$08$0C$0E$0F

$10$14$18$1C$3C

$40-$7F$80-$FF

1.65 ms1.65 ms

40 s40 s40 s40 s

40 s40 s40 s40 s

40 s40 s40 s40 s40 s40 s40 s

Table 7.8 Commands for DMC-20434 LCD Kit



Program to initialize the DMC-20434 LCD kit

lcd_cmd EQU $B5F0lcd_init PSHX

LDX #lcd_cmdBRSET0,X $80 *LDAA #$3CSTAA 0,X ; set 4 20 displayBRSET0,X $80 * ; wait until LCD is readyLDAA #$01STAA 0,X ; clear display and move cursor to homeBRSET0,X $80 *LDAA #$0FSTAA 0,X ; turn on displayBRSET0,X $80 *LDAA #$06STAA 0,X ; set cursor increment, shift offBRSET0,X $80 *LDAA #$14STAA 0,X ; set cursor shift rightBRSET0,X $80 *



LDAA #$02STAA 0,XBRSET 0,X $80 *PULXRTS

In C language, we need to add the following two lines to the hc11.h file in the ImageCraftC compiler so that we can use LCD_CMD and LCD_DAT to access the registers of theLCD kit:

#define LCD_CMD *(unsigned char volatile *)(0xB5F0)#define LCD_DAT *(unsigned char volatile *)(0xB5F1)



The C language version of the LCD kit initialization function:

void lcd_init ( ){

while (LCD_CMD & 0x80); /* wait while LCD is busy */LCD_CMD = 0x3C; /* set 4 20 display */while (LCD_CMD & 0x80);LCD_CMD = 0x01; /* clear display and set cursor to home */while (LCD_CMD & 0x80);LCD_CMD = 0x0F; /* display cursor, and cursor blink on */while (LCD_CMD & 0x80);LCD_CMD = 0x06; /* set cursor increment, shift off */while (LCD_CMD & 0x80);LCD_CMD = 0x14; /* set cursor shift right */while (LCD_CMD & 0x80);LCD_CMD = 0x02; /* move cursor to home */while (LCD_CMD & 0x80);

}



Output Data on the DMC-20434 LCD Kit

- The DMC-20434 does not display alphanumeric data in sequential order due to its internalline wrapping.

- Without line adjustment, the LCD kit will display the first 20 characters in the first line,the second 20 characters in the third line, the third 20 characters in the second line, and thefourth 20 characters in the fourth line.

- The following subroutine outputs one character to the LCD kit and performs line adjustment:

LCD_CMD EQU $B5F0 ; LCD command register addressLCD_DAT EQU $B5F1 ; LCD data register address

lcdputch2lcd STAA LCD_DAT ; output 1 character to the LCD kitlcdlp LDAA LCD_CMD ; read next character position

BMI lcdlp ; test if busy and wait if trueCMPA #$13 ; test for line 1 wrapBEQ lcd1 ; if match, correct line wrapCMPA #$53 ; test for line 2 wrapBEQ lcd2 ; if match, correct line wrapCMPA #$27 ; test for line 3 wrapBEQ lcd3 ; if match , correct line wrapRTS



* correct line 1 wrap from line 3 to line 2lcd1 LDAA #$40 ; load line 2 start position

ORAA #$80 ; set command bitSTAA LCD_CMD ; write to displayRTS





* this is the program to output a string pointed by Y and terminated by a NULL characterputstr2lcd LDAA 0,Y

BEQ doneJSR putch2lcdINYBRA putstr2lcd

done RTS



C Language Version of LCD Output Functions

void putch2lcd (char ch){

LCD_DAT = ch;while (LCD_CMD & 0x80);if (LCD_CMD == 0x13) {

LCD_CMD = 0x40 || 0x80; /* correct line 1 wrap from line 3 to line 2 */while (LCD_CMD & 0x80);

}if (LCD_CMD == 0x53) { /* correct line 2 wrap from line 4 to line 3 */

LCD_CMD = 0x14 || 0x80;while (LCD_CMD & 0x80);

}if (LCD_CMD == 0x27) { /* correct line 3 wrap from line 2 to line 4 */

LCD_CMD = 0x54 || 0x80;while (LCD_CMD & 0x80);

}}



void putstr2lcd (char *ptr){

while (*ptr) {putch2lcd (*ptr);ptr++;

}}



Digital to Analog Converter

- D/A conversion is required when a digital code must be converted to an analog signal.- A general D/A converter consists of a network of precision resistors, input switches, and

level shifters that activate the switches that convert a digital code to an analog voltage orcurrent.

- D/A converters have a fixed or variable reference voltage , which can be generated eitherinternally or externally.

- The reference voltage determines the switching threshold of the precision switches that formthe impedance network that controls the value of the output signal.

- Fixed reference D/A converts have current or voltage output values that are proportionallyto the digital input.

- Multiplying D/A converters produce an output signal that is proportional to the product ofa varying reference level and a digital code.



Interfacing to the D/A Converter Using the 68HC11 Output Ports

- The AD557 is an 8-bit D/A converter that produces an output voltage proportional tothe digital input code.

- The AD557 can operate with a +5V supply.- Output range is 0V to +2.55V when operated as shown in Figure 6.23.- Vout = (decimal equivalent of input code) × 0.01 V

1 16

15

14

13

12

11

10

98

7

6

5

4

3

2

Bit 8 (LSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 (MSB)

V OUT

V OUT SENSE A

V OUT SENSE B

GND

GND

+V CC

CS

CE

AD557

Figure 7.26 AD557 Pin Layout

1 2 3 4 5 6 7 8

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Analog output+5 V

0.1 F

16 15 14 13 12 11 10 9

(LSB) (MSB)

V OUT GND GND V CC CS CE

Figure 7.27 AD557 unipolar output configuration, 0 V to 2.55 V operation



AD557 Input latch operation

- Data input can be latched or transparent without being latched.- The CS and CE signals together control the latching of input data.

The AD557 can be used to generate analog waveforms as illustrated in the next example. It takes 1 s to complete the conversion of one sample.

Table 7.9 AD557 input latch operation

Inputdata CE CS

D/A converterdata

Latchcondition

010101xx

00

001x

0001

x1

010101

previous dataprevious data

"transparent""transparent"

latchinglatchinglatchinglatchinglatchinglatching



Example 7.8 Use the 68HC11 port B and an AD557 to generate a sawtooth waveform. Solution: The circuit connection is shown in Figure 7.28.

The program is in the following:

regbas equ $1000PORTB equ $04

org $C000ldx #regbasclr PORTB,X

again inc PORTB,Xbra againend

In C language,

#include <hc11.h>main ( ){

PORTB = 0;while (1) {

POTB ++;}

}

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

V OUTV OUT

GND

GND

V CC

CS

CE

V OUT Sence A

V OUT Sence B

Figure 7.28 Using an AD557 to generate a sawtooth waveform

68HC11 AD557



Example 7.9 Using the circuit in Figure 7.28 to generate the waveform shown in Figure 7.29.

2 V

1 V

Figure 7.29 Another periodic waveform

1 ms 1 ms 1 ms 1 ms 1 ms 1 ms

Solution:REGBAS EQU $1000PORTB EQU $04

ORG $C000LDY #REGBAS

start CLR PORTB,Y ; output 0VJSR delay_1ms ; wait for 1 msLDAA #100 ; output 1 VJSR delay_1msLDAA #200 ; output 2 VJSR delay_1msBRA start

delay_1ms LDX #200again NOP

NOPDEXBNE againRTS



The C Program to Generate the waveform shown in Figure 7.29.

#include <hc11.h>void delay_1ms ( );main ( ){

while (1) {PORTB = 0; /* output 0 V */delay_1ms ( ); /* wait for 1 ms */PORTB = 100; /* output 1 V */delay_1ms ( );PORTB = 200; /* output 2 V */delay_1ms ( );

}return 0;

}void delay_1ms ( ){

TFLG1 = 0x40; /* clear OC2F flag */TOC2 = TCNT + 2000; /* start an OC2 operation with 1 ms delay */While (!(TFLG1 & 0x40)); /* wait for 1 ms */

}



Centronics Printer Interface

Signals:• D7-D1: data pins.• BUSY: printer busy signal (output from printer)• PE: printer error (asserted high). • SLCT: printer on-line (output from printer)• DATA STROBE: An input to the printer. Data is latched into the printer by this signal.• ACKNLG: Printer acknowledges the receipt of data using this signal.

Centronics printer timing requirements

PE

SLCT

D7 - D1

DATA STROBE

Busy

ACKNLG

Figure 7.31 Centronics printer interface timing requirements

50 ns (minimum)

100 ns (minimum)

4 s



Interface a Centronics printer to the 68HC11 port C

Configure port C as follows:

1. Set port C for output, i.e., write the value $FFinto DDRC.

2. Program PIOC to set the following parameters:• pulse mode handshake output• no STRA interrupt• falling edge of STRA as the active edge• STRB is active low• normal port C pins

Write the value $1C into PIOC.

Data setup time isperiod of E ÷ 2 - tPWD + tDEB

= 325 ns > 50 ns (required)

Data hold time (with respect to DATA STROBE)is at least 2 E clock cycles (= 1 s at 2 MHz). Thisis greater than the 100 ns requirement.

The timing requirements are satisfied :

PC6PC5PC4PC3

PC2PC1PC0

STRB

PE6

PE7

STRADATA STROBE

ACKNLG

SLCT

PE

D6

D5D4D3

D2

D1D0

68HC11Centronics

interface

Figure 7.32 Interfacing a Centronics printer to port C



For the following subroutines, use these constant declarations:

regbas equ $1000 ; base address of I/O register blockDDRC equ $07 ; offset of DDRC from regbasPIOC equ $02 ; offset of PIOC from regbasPORTCL equ $05 ; offset of PORTCL from regbasPORTE equ $0A ; offset of PORTE from regbasoutput equ $FF ; value to set port C as an output port

Write a routine to initialize the Centronics printer in Figure 7.32.

prt_init pshapshxldx #regbasbrset PORTE,X $40 * ; don’t go if printer errorbrclr PORTE,X $80 * ; don’t go if printer not on-lineldaa #output ; configure port C for outputstaa DDRC,X ; “ldaa #$1C ; initialize PIOCstaa PIOC,X ; “pulxpularts



Write subroutines to print a character and a string using polling method

The subroutine prt_char outputs the character in A.

prt_char BRCLR PIOC,X $80 * ; wait until the STAF bit is set to 1STAA PORTCL,X ; print the character in ARTS

The subroutine prt_str outputs the string pointed to by index register Y. The index register Xcontains the base address of the I/O register block. The string is terminated by a NULLcharacter.

prt_str PSHAnext LDAA 0,Y ; get the next character

BEQ quit ; is this the end of the string?JSR prt_char ; print the current characterINY ; move the string pointerBRA next

quit PULARTS



Write subroutines to print a character and a string using interrupt-driven method

prt_str1: enable the interrupt and then wait for the printer interrupt until the whole string is printed.

prt_char1: print the character in A and also move the string pointer Y.

Set up the interrupt vector table:ORG $FFF2FDB prt_char1

prt_str1 BSET PIOC,X $40 ; enable STRA interruptCLI ; “

again LDAA 0,Y ; wait for printer interruptBNE again ; is this end of the stringBCLR PIOC,X $40 ; disable STRA interruptSEI ; disable all interruptRTS

prt_char1 STAA PORTCL,X ; print the characterINY ; move the string pointerTSXSTY 5,X ; also update the saved version of YRTI



C Language Version of the Printer Routines

void prt_init ( ){

while ((PORTE & 0x40) || (!(PORTE & 0x80)));DDRC = 0xFF;PIOC = 0x1C;

}/* polling method version */void prt_char (char ch){

while (!(PIOC & 0x80)));PORTCL = ch;

}/* polling method version */void prt_str (char *ptr){

while(*ptr) {prt_char (*ptr);ptr++;

}}



Interrupt-Driven Method Printer Routines

- The subroutine prti_str enable printer interrupt and then stay in a wait loop to wait for printerinterrupt.

- The printer interrupt service routine (prti_char) outputs the character pointed by Y.- The base address of I/O register block is passed in X.- Interrupt vector table entry for STRA interrupt must be set up properly.

prti_str BSET PIOC,X $40 ; enable STRA interruptCLI

again LDAA 0,Y ; wait for interruptBNE again ; reach the end of the string?BCLR PIOC,X $40 ; disable STRA interruptSEIRTS

prti_charSTAA PORTCL,XINYTSXSTY 5,X ; update the Y value in the stackRTI



C Language Version of the Interrupt-Driven Printer Functions

- The pointer to the string to be output is defined as a global variable

char *ptr;

void prti_str ( ){

PIOC |= 0x40; /* enable STRA interrupt */INTR_ON ( );while (*ptr); /* wait for interrupt */PIOC &= 0xBF; /* disable STRA interrupt */INTR_OFF ( );

}

/* STRA interrupt service routine */#pragma interrupt_handler prti_char ( )void prti_char (){

PORTCL = *ptr++;}



The i8255 Programmable Peripheral Interface (PPI)

- In expanded mode, both port B and port C are not available for I/O functions.- A possible solution to this problem is to add an parallel interface chip such as i8255 to the

68HC11.- The Intel i8255 has three 8-bit ports: port A, B, and C.- Signals A1-A0 select the registers within the PPI as follows:

Group AControl

Group BControl

DataRegister A

DataRegister B

DataReg. C

(8)

(8)

(4)

(4)

Port A

Port B

Port CD7-D0

RD WR A1 A0 RESET CS

Figure 7.33 Intel i8255 programmable peripheral interface

A1 A0 port selected

0011

0101

port Aport Bport Ccontrol (write only)



Operation of the i8255

- When the msb is 1, the control register defines the operation mode. Otherwise it sets or clears a selected bit.

- i8255 has three modes:mode 0, mode 1, andmode 2.

Control Word

D7 D6 D5 D4 D3 D2 D1 D0

Port C (lower): 1 = input, 0 = outputPort B: 1 = input; 0 = outputMode selection: 0 = mode 0; 1 = mode 1

Group B

Port C (upper): 1 = input, 0 = outputPort A: 1 = input, 0 = outputMode selection: 00 = mode 0, 01 = mode 1, 1x = mode 2

Mode select flag: 1 = active

Group A

Figure 7.34 i8255 control register mode definition format

Control Word

D7 D6 D5 D4 D3 D2 D1 D0

Figure 7.35 i8255 control register bit set/reset format

Bit set/reset: 1 = set, 0 = resetx x x

Don't care Bit Select

0 1 2 3 4 5 6 70 1 0 1 0 1 0 1 B 00 0 1 1 0 0 1 1 B 10 0 0 0 1 1 1 1 B 2

Bit Set/Reset Flag: 0 = active



Mode 0 (basic input and output)

- There are two 8-bit ports and two 4-bit ports.- Any port can be input or output.- Outputs are latched.- Inputs are not latched.- 16 different input/output configurations are possible in this mode.- No handshake is required.- Data are simply written into or read from a specified port.



Mode 1 (Strobed Input/Output)

- Port A and B use the lines of port C to generate or accept “handshake” signals requiredin this mode.

- Port A, B, and C are divided into two groups. Each group consists of one 8-bit port andone 4-bit control/data port. The 8-bit data port can be input or output. The 4-bit port is used for control and status of the 8-bit data port.

- Port C pin functions are shown in Table 7.10

PinPort A as input Port A as output Port B as input Port B as output

Pin Function

Table 7.10 Port C pin functions in mode 1

Note: OBF X (X = A or B): Output buffer full flip-flop. The OBF will go low to indicate that the CPU has written data out to the specified port. ACK X : Acknowledge input. A low on this pin informs the i8255 that the data from port A or B have been accepted. INTR X : Interrupt request. A high on this pin can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. STB X : Strobe Input. A low on this input loads data into the input latch. IBF X : Input buffer full. A high on this pin indicates that data have been loaded into the input latch.

OBF AACK A

I/OI/O

INTR ANANANA

PC7PC6PC5PC4PC3PC2PC1PC0

I/OI/O

IBF ASTB AINTR

ANANANA

NANANANANA

STB BIBF B

INTR B

NANANANANA

ACK BOBF BINTR B



Mode 1 Input Timing

- When the input buffer is not full, the input device places data on input port pins and pulsesthe STB signal.

- The falling edge of STB latches data into the input port data register and sets the input bufferfull flip-flop.

- The PPI asserts the interrupt request signal INTR and the CPU reads the data in the interruptservice routine. After the data is read, the input buffer full flag is cleared.

tSIB

tPS

tPH

tSI

T

tRIT

tRIB

STB

IBF

INTR

RD

Input fromperipheral

Figure 7.36 Mode 1 input timing diagram



Mode 1 Output Timing

- When the output buffer is not full and the CPU is interrupted, the CPU writes data to the i8255. For a delay of tWB after the rising edge of the WR signal, data appears on i8255port pins.

- The OBF signal is asserted by the write operation. The falling edge of the OBF latches datainto the output device and the output device asserts the ACK signal to acknowledge the receipt of data.

tWIT

tWB

tWOB

tAOB

tA

K

tAI

T

Figure 7.37 Mode 1 output timing diagram

WR

OBF

INTR

ACK

Output data



Mode 2 (Strobed bi-directional bus I/O)

- This mode provides a means for communication with peripheral device or structure on asingle 8-bit bus for both transmitting and receiving data.

- Only port A is used. Port A becomes an 8-bit bi-directional bus port whereas 5 bits (PC3-PC7) of port C are used as control port.

- Functions of port C pins are shown in Table 7.11.

PinPC7 OBF A

Pin Function

Table 7.12 Port C pin functions in mode 2

PC6 ACK A

PC5 IBF A

I/O

PC4 STB A

I/O

PC3 INTR APC2PC1

PC0

Note . OBF A : Output buffer full. The OBF will go low to indicate that the CPU has written data out to port A. ACK A : Acknowledge input. A low on this pin enables the tri-state output buffer of port A to send out data. INTR A : Interrupt request. A high on this pin can be used to interrupt the CPU for both input or output. STB A : Strobe Input. A low on this pin loads data into the input latch. IBF A : Input buffer full. A high on this pin indicates that data have been loaded into the input latch.

I/O



Mode 2 Signal Transactions

tWOB

tST

tSIB

tPS

tPH tADtKD

tAOB

tA

K

tRIB

data from peripheral to i8255

Data from i8255 to peripheral

data fromi8255 to CPU

WR

OBF

INTR

ACK

STB

IBF

Peripheral bus

RD

Figure 7.38 i8255 Mode 2 signal transactions

Data fromCPU to i8255



Mode 2 Data Output

Polling approach

- The software tests the OBF signal to determine whether the output buffer is empty. If it is,the data is written out.

- The external circuitry also monitors OBF signal to decide if the microprocessor has sent new data to the i8255. As soon as OBF is detected to be low, the output device sends backthe ACK signal to remove data from the output buffer.

- The low level of the ACK signal causes the OBF signal to go high and enables the three-state output buffer so that data can be read.

Interrupt-driven approach

- The software first enables the i8255 interrupt. When the output buffer is empty, it generates an interrupt to the CPU. The CPU outputs a byte to the i8255 in the interrupt service routine.

- The byte written to the i8255 causes the OBF signal to go low, which informs the outputdevice to latch data.

- The output device asserts the ACK signal to acknowledge the receipt of data, which causesthe OBF signal to become inactive.



Mode 2 Data Input

Polling approach

- The software tests the IBF signal to determine if data have been strobed into the buffer.- If IBF is low, the input device places data on port A pins and asserts the STB signal to strobe

data into the input buffer. After this, the IBF signal goes high.- When the user program detects that the IBF signal is high, it reads the data from the input

buffer. The IBF signal goes low after the data is read.

Interrupt-driven approach

- The software first enables the i8255 to interrupt the CPU.- When the IBF is low, the input device places data on the port pins and asserts the STB signal

to strobe data into the input buffer.- After data are strobed into the input buffer, the IBF signal is asserted and an interrupt is

generated.- The CPU reads the data from the input buffer when executing the interrupt service routine.- Reading data brings the IBF signal to low, which further causes the STB signal to go high.



The i8255 on the CMD-11A8 Demo board

- Four bytes are assigned to the i8255 on the CMD-11A8 demo board:

1. $B5F4: port A register2. $B5F5: port B register3. $B5F6: port C register4. $B5F7: control register

Example 7.12 Configure the i8255 on the CMD-11A8 to operate in mode 0:• Port A for input• Port B for output• Upper port C for input• Lower port C for outputSolution:

Bit 7: set to 1 to choose mode select LDX $B5F4Bit 6 & 5: set to 0 to configure port A to mode 0 LDAA #$98Bit 4: set to 1 to configure port A for input STAA 3,XBit 3: set to 1 to configure upper port C for inputBit 2: set to 0 to configure port B to mode 0Bit 1: set to 0 to configure port B for outputBit 0: set to 0 to configure lower port C for output



Example 7.14 Use the auxiliary port of the CMD-11A8 demo board to drive 4 seven-segmentdisplays. Use port A of the i8255 to drive the segment pattern and use the upper four bits of port B of the i8255 to drive the display select signals. Write a program to display 1999.Solution: - The circuit is shown in Figure7.39.- Configure i8255 to mode 0.- Configure port A and B for output.- Write the value $80 into the register.

74ALS244

ab...g

PA6 PA5 PA0

100

100

100

ab...g

ab...g

ab...g

PC3

PC2

PC1

PC0

common cathode

#3 #2 #1 #0

Imax

= 7

0 m

A

2N2222

2N2222

2N2222

2N2222

Figure 7.39 Use port A and C of i8255 to drive four seven-segment displays

i8255

R

R

R

R

D7-D0, RD,CS, A1-A0



PPI_BAS EQU $B5F4 ; i8255 port A data register addressINIT_VAL EQU $80 ; value to initialize i8255PA EQU 0 ; offset of port A from PPI_BASPB EQU 1 ; offset of port B from PPI_BAS

ORG $2000LDAA #INIT_VAL

forever LDY #distabnext LDX #PPI_BAS

LDAA 0,YSTAA PA,X ; send out the digit patternLDAB 1,YSTAA PB,X ; send out the select valueINYINYLDX #200 ; 1 ms delay

again NOP ; “NOP ; “DEX ; “BNE again ; “CPY #distab+8BEQ foreverBRA next



distab FCB $30,$08FCB $7B,$04FCB $7B,$02FCB $7B,$01

In C language, we need to add the following statements to the hc11.h file so that we can uselabels to reference i8255 registers:

#define PPI_PA *(unsigned char volatile *)(0xB5F4)#define PPI_PB *(unsigned char volatile *)(0xB5F5)#define PPI_PC *(unsigned char volatile *)(0xB5F6)#define PPI_CMD*(unsigned char volatile *)(0xB5F7)



#include <hc11.h>char distab [4][2] = {{0x30, 0x08}, {0x7B, 0x04}, {ox7B, 0x02}, {0x7B, 0x01}};void wait_1ms ( );main ( ){

PPI_CMD = 0x80; /* initialize the i8255 control register */while (1) {

for (i = 0; i < 4; i++) {PPI_PA = distab[i][0]; /* output segment pattern */PPI_PB = distab[i][1]; /* send out digit select */wait_1ms ( );

}}return 0;

}/* create 1 ms delay */void wait_1ms ( ){

TFLG1 = 0x40; /* clear OC2F flag */TOC2 = TCNT + 2000;while (!(TFLG1 & 0x40));

}



The 68HC24 Port Replacement Unit

- In the early years of the 68HC11, the amount of on-chip EPROM or EEPROM that can beimplemented onto the microcontroller chip is very limited.

- The software of the target embedded product was to be placed in the on-chip ROM.- During the product development stage, software need to be modified many times. The

expanded mode must be chosen and external EPROM must be used so that software can bemodified and tested.

- Ports B and C, which were needed in the final product, were lost in the expanded modeduring the product development phase.

- The port replacement unit 68HC24 was designed to regain ports B and C so that the productscan be evaluated and tested.

- After the design had been tested and evaluated to be satisfactory, the software in the external EPROM could be moved into the internal ROM without modification as long as the external EPROM and internal ROM occupied the same memory space.

- The signals and an example of the 68HC24 application is shown in Figure 7.38.



68HC11 68HC24

from reset circuit

PB0-PB7

STRASTRB

PC0-PC7

VDD

IRQAS

AD0-AD7

CS

A12-A15

ER/WRESETRESET

R/WE

PB4-PB7

PB3

PC0-PC7

AS

IRQ

Figure 7.38 Circuit connecting the 68HC11 and the 68HC24

chapter 7: parallel i/o ports

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