XI ICFA SCHOOL ON INSTRUMENTATION IN ELEMENTARY PARTICLE PHYSICS

SAN CARLOS DE BARILOCHE, 11-22 JANUARY 2010

CCD laboratory

Hardware:

Leach system:

Video card,

Timing card

Master board

Power supplies:

±15volts for CCD preamplifier.

40 volts for CCD substrate bias.

-12.5 volts for Vref (for Reset)

-22 volts for CCD video transistor amplifier drain (VDD)

15 volts (2Amp) for the thermoelectric cooling.

Chiller : -10C but could go down to -150C, the lower the better.

CCD temperature: Chiller + thermoelectric cooling ~-25C.

Picoscope. 100 Ms/s, 8 bits.

Software:

PC login: Username: desdaq Pass: desdaq

Voodoo:

Setup

1. load bariloche_2010.setup (configures all Leach voltages, clock timings, etc)

2. apply

Exposure to take images: If we want to modify clock or voltages:

1. debug

2. development

A window with clocks and voltages pops up.

Preferences:

Checkbox: check Disable read elapsed exposure time.

Checkbox: Save to disk

Image viewer: VS9

Dynamic range:

Use the right button of your mouse to adjust the dynamic range of the image within the dynamic range of the

computer’s video.

The image dynamic range is 16 bits (i.e 216 numbers from 0 to 65535), much larger than the dynamic range of the video

(i.e. 8 bits, from 0 to 255). The video dynamic range is a window of amplitude A within a larger window of amplitude B.

Pushing down and holding the right button while scanning horizontally moves the video dynamic range from lower to

higher and vice versa.

Pushing down and the right button while scanning vertically changes the width of the smaller window A with respect to

B. NOTE that a larger A implies a lower resolution of the image on the video screen.

PicoScope

PicoScope is a stand alone DAQ box that allows digitization and display of signals. PicoScope has a full bandwidth of 100

Ms/s and a maximum resolution of 12 bits.

We will use PicoScope to look at CCD voltages, clocks and video signals on the PC.

To start PicoScope doble click PicoScope on the PC desktop. To use PicoScope just follow the menus, which are intuitive.

Things we want to do:

1) Look at CCD signals using PicoScope and the setup without a CCD: Look at clock and bias voltages. Get familiar

with the clock sequence and what they do to shift the CCD charge towards the output. Understand how the 2

channels operate. Use Vodoo to change clock and bias parameters.

2) Acquire an only noise video image using a short circuit in the video output. Understand the measurement noise.

Look at the spectrum of the noise making an FFT. Using an external signal source obtain the system’s gain.

3) Using PicoScope on the system with a CCD. Connect PicoScope to the Leach video output. Get familiar with

video output signals. Understand what each part represents. Observe CCD video lines, the overscan, reset and

SW clocks, pedestal and pixel signal.

4) Calculate the CDS for several integration times.

5) If we can connect a trigger to PicoScope we can do the PTC using the CCD data. Otherwise use images provided.

____________________________________________

CCD Transfer Curves

CCD Operational phases:

1) Charge generation.

2) Charge collection.

3) Charge transfer.

4) Charge measurement.

The CCD photon transfer curve allows calibration, characterization and optimization of the CCD readout system in

absolute terms. These parameters include readout noise, dark current, quantum yield, full well, linearity, pixel

nonuniformity, sensitivity, signal-to-noise, offset, and dynamic range.

A schematic representation of a CCD camera has five transfer functions:

Figure 1

S(DN)=P.QEI.ηi.SV.ACCD.A1.A2 (1) where

P is the number of incident photons.

QEI is the quantum efficiency (i.e. number of interacting photons/ number of incident photons).

ηi is the quantum yield (i.e. the number of collected electrons e- per interacting photons).

SV is the sensitivity of the sense node in V/ e- .

ACCD Is the gain of the CCD output amplifier (V/V).

A1 is preamplifier gain (V/V).

A2 is the gain of the ADC (DN/V).

We also define two constants K and J. K gives the number of electrons per DN (e-/DN), and J the number of photons per

DN. K=J when the quantum yield ηi=1, that is for wavelengths λ>4000Å (including the visible and close infrared

spectrum).

ηi(λ)=K/J

Assuming unity quantum yield

S(DN)=PI/K (2)

we can calculate the variance of the signal by

(3)

Using and equation (2) we can write equation (3) as:

(4)

Equation (4) converts noise and signal measurements in DN directly in units of e-.

Figure 2 shows the four main regimes of a photon transfer curve: read noise, shot noise, fixed pattern noise and full

well. Due to the large CCD dynamic range the plot is done on a log-log scale. The first regime represents the read noise

floor σ2R(DN) measured under totally dark conditions. The noise is limited by the output amplifier and readout noise. As

we put signal in the CCD the noise becomes dominated by the shot noise of the signal. Some pixels intercept more

photons than other pixels. This noise follows a Poisson statistics. The sigma of the charge collected by any given pixel is

proportional to the square root of the signal (i.e. number of photons collected). Since the plot is done in a log scale this

noise is represented by a straight line with slope ½. The third regime is associated with pixel nonuniformity. This is a

CCD problem due to limitations in the fabrication process such as variations in the photomask alignment. The pixel

nonuniformity noise is proportional to the signal level and hence has a slope of 1 in the plot. The last regime is the full

well, at this point the charge is spread between pixels which makes the noise suddenly decrease.

Figure 2

Method to plot a photon transfer curve (PTC)

The photon transfer curve allows among other things to calibrate the readout system. The nonuniformity noise can be

eliminated taking two images and subtracting them pixel by pixel. In the PTC the abscissa S(DN) is proportional to the

light exposure time (i.e. number of incident photons). To eliminate large statistical errors a certain number of pixels

values are averaged (e.g. 400 pixels in a 20x20 pixel array). That is:

(5)

Where Npix is the number of pixels in the subarray and SOFF(DN) is the average offset level. The offset level is the camera

output DN level is absence of light. The offset is usually calculated from a dark exposure or using the CCD overscan. The

overscan area is part of the CCD horizontal register found at the beginning of each readout line. The overscan is

generated on purpose with the purpose of measuring the offset noise.

Noise data for the ordinate of the PTC are found by calculating the standard deviation of the subarray after the pixel

nonuniformity has been removed. The variance is calculated by:

(6)

The factor of 2 is included because the subtraction of the 2 images increases the variance by the same factor of 2. Also

the uncertainty in measuring the noise σ2S(DN) can be improved using a larger pixel subarray or averaging the σ2

S(DN) of

several measurements (the latest requires more images).

How to obtain the camera gain constants K and J

K and J can be found using equation (4). In log form equation (4) becomes:

(7)

For the region where σ2S(DN)>> σ2

R(DN) the slope is ½. Extending the ½ slope to the point where σ2S(DN)=1 we obtain K

in e-/DN.

The same approach can be used in determining J when the quantum yield is greater than 1. Since the other gains are

constants, changing the photon wavelength we obtain a different PTC. Shorter wavelengths will generate more e—h

(electron-hole) pairs per interacting photon, increasing the quantum yield ηi. For instance, a photon with λ=1216Å gives

ηi=2.99 e—/interacting photon, and a X-ray photon with λ=2.1Å gives ηi=1420 e—/interacting photon. The J constants can

be calculated using the log plot at the point where σ2S(DN)=1. The quantum yield can be calculated as follow: 1st find the

intercept of the PTC for the corresponding wavelength photon at σ2S(DN)=1 and the intercept of the PTC at σ2

S(DN)=1 for

a photon with a wavelength that produces 1 e—/interacting photon. Then ηi(λ) is equal to the quotient of the last one

over the first one (i.e. ηi(λ)=K/J).

Figure 3

Calculating K and J using histograms

The graphical method of determining K and J is accurate to about 10%. A more precise measurement can be obtained

constructing a histogram of K values. To calculate the σ2S(DN) it is convenient to work with the subtraction of 2 images,

as before, to eliminate pixel nonuniformity. Furthermore, the images must have flat field illumination close to full well or

at least with large signal values to assure that the read noise is negligible. The histogram is built calculating K values for

different pixel subarrays of the working image. The distribution of K must be Normal with mean Kµ, the desired value.

The sigma of the distribution gives us the level of precision of the measurement.

Similarly, we can determine J for a given λ. For this case we use 4 image frames, two to determine K (i.e using visible

light) and the other two for the desired λ. In this case the histogram should generate two Gaussian distributions one

centered at K and the other one at J.

Figure 4

CCD architecture

The basic building block for a CCD pixel is the MOS transistor. The MOS can store charge as an analog memory. In CCDs

the charge can be also generated optically. In a three-phase CCD each pixel is connected to the three phases of a clock

via three individual conductive gates. The gates of all (or at least many) pixels with the same phase are connected in

parallel. The clock voltages are manipulated in a way that the pixel charge can be transferred vertically along the CCD

array columns. The row of pixels that is closest to the edge is clocked out of the array into the horizontal shift register

and later read out pixel by pixel. Once a CCD row has been read out the next row is clocked into the horizontal register.

CCDs have evolved over the years and nowadays the charge a pixel looses in every transfer is smaller than 1ppm (i.e.

part per million).

Figure 5 a and 5b

Figure 5a shows the vertical registers were charged is stored. The CCD columns are separated by channel stops. Each

pixel has 3 gates (conductive electrodes). The gates are biased in a way that allows the charge to be accumulated and

stored during charge collection and to shift during the CCD readout. During charge collection or integration 2 clock

phases are biased high and one is biased low. Figure 5b shows a 2 video output CCD where the CCD charge is shifted up

for the upper half of the CCD and down for the lower half of the CCD. The row next to edge is shifted into the horizontal

register and clocked out, pixel by pixel through the output video amplifier. The video amplifier converts charge into a

voltage.

Figure 6 shows the 3 phases of the clock in more detail.

Figure 6

Charge generation:

The charge generation is defined by the CCD quantum efficiency (QE). QE is a function that relates the number of

incident photons to the number of interacting photons. QE is a function of the photon wavelength and decreases deeply

for near infra red (NIR) and blue wavelengths. A photon interacts with the Si body and generates one or more e--h pairs

by a physical process called the photoelectric effect. The interaction only occurs if the photon has enough energy to

overcome the Si energy gap of 1.14eV. The photon energy is related to its wavelength through the equation:

A photon with energy of 1.1 to 3.1 eV (11000 to 4000 Å, NIR and visible spectrums) will generate 1 e--h pair. For photons

with energy > 10eV we define the quantum yield ηi as the number of e--h pairs generated by a photon with energy E(eV).

Using different fabrication, substrate thinning, and coating procedures the CCD can cover a very large spectrum range

from X-ray, UV, visible and NIR.

Charge collection:

Charge collection is defined by three parameters, the area and number of pixels in a CCD, the charge capacity, and the

ability to efficiently collect the generated electrons.

The number of pixels per CCDs is in turn limited by fabrication costs, fabrication yield and readout systems. Today, the

technology allows for CCDs much larger than the ones used in practice due to the reasons mentioned above. Very large

CCDs are also large in size; they are more susceptible to fabrication defects that lower the production yield increasing

the cost more than linearly. Also readout times increase linearly and processing times increase exponentially.

The well capacity (i.e. number of e- a pixel can hold) is usually between 50,000 and 1 million e-. A large well capacity is

desired because increases the dynamic range and S/N. However, the well capacity is associated to the pixel size (i.e.

area). Large pixels reduce the number per Si area, increasing the cost of the CCD/pixel. The well capacity is also

associated to pixel non uniformity due to the tolerances of the masks.

Pixel size is also limited due to the need to maintain high charge transfer efficiency (CTE) at a reasonable speed. 15µ

square pixel CCDs with a well capacity of 500,000 e- can be readout with ~ 2 e- of noise.

Charge diffusion also limits the pixel size. The charge collection is a function of the distance between the generated

electron and the collecting terminal. Photon penetration is a function of the wavelength, hence certain photons will

generate electrons deep inside the CCD, far away from the collector diffusing the charge between pixels. This effect also

happens in back illuminated CCDs and that is the reason why the CCDs need to be thinned out.

Charge transfer

The CTE has been improved up to better than 99.9999% or a charge loss of <1ppm. Since the CCD charge transfer is in

general a “slow” process this good numbers can be achieved. For very high CCD readouts, thermal diffusion and charge

drifts can become a problem. But in general the limiting factor to achieve 100% efficiency is due to small traps in the Si

structure. The traps extract a small amount of charge and release it at a later time diffusing the charge into another

pixel. Si traps can be found even before CCD fabrication. Nowadays a fabricated CCD will have very few traps.

Energetic particles such as protons, electrons, neutrons, heavy ions, and gamma rays can also generate traps. This

problem is more severe for space mission cameras were CCDs are more exposed to radiation.

Charge measurement:

The CCD pixels are made with MOS devices used as reverse biased capacitors. The charge is readout by a MOSFET based

charge to voltage amplifier. The output voltage is inversely proportional to the sense node capacitor (Figure 7). The SN

capacitor is of the order of 50fF which produces a gain of 3.2 µV/ e-. It is also important to minimize the noise of the

output amplifier, typically the largest noise source in the system. In a telescope system the signal level is associated to

the area of the telescope. For a given telescope sensitivity and S/N ratio, the telescope area required is directly

proportional to the readout noise. A large readout noise implies a larger telescope.

Figure 7

Figure 8 shows the typical noise spectrum of an output amplifier.

Figure 8

The MOS device used in the design of CCDs

Figure 9

This is a p-type substrate or p-MOS

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06

Inp

ut-

refe

rre

d n

ois

e [V

/(H

z).

5]

Frequency [Hz]

Single transistor

20C 5/2 0C 5/2

-20C 5/2 -40C 5/2

-60C 5/2 -80C 5/2

-100C 5/2 -120C 5/2

-140C

Solid state equations:

Accumulation:

If we apply a negative voltage to the gate the majority carriers (holes) will be attracted to the Si-SiO2 interface. The

applied voltage drops on the gate capacitance given by

Where εox is the permittivity of the SiO2 and d is its thickness.

Depletion:

A more interesting case happens when we apply a positive voltage to the gate. Then holes are driven away leaving

behind negative charges. The region becomes depleted of mobile charges (holes). The number of holes depleted equals

the number of positive charges on the gate.

Where q=1.6x10-19 is the charge of an electron or hole, NA is the concentration of acceptor atoms in the substrate and xd

is the depletion depth.

The capacitance of the depletion region is given by

This Cdep capacitance is much smaller than Cox and they are in series, so Cdep dominates.

Figure 10

The potential V in the depletion region of the p-MOS (Figure 10) can be obtained solving the Poisson differential

equation. V is given by

Hence, the surface potential is

And the electric field at the surface is

The applied gate voltage VG is split between the oxide voltage VOX and the depletion voltage

VG = VOX + VSI

Hence, the depletion depth increases with the square root of the gate voltage and decreases with the square root of the

doping concentration.

The last one is an important equation because it relates to the well capacity. To maintain charge neutrality any signal

accumulated at the gate will lower the

Buried channel potential well

The basic p-MOS based CCD is also called the surface-channel CCD. The charge is stored and transferred along the surface of the semiconductor. Surface channel CCDs have a low CTE due to charge trapped in the Si_SiO2 interface. To avoid this problem the buried channel CCD was developed. For the buried channel CCD the maximum of the potential well is away from the Si_SiO2 interface and inside the Si body as shown in Figure 11. This is achieved by inserting an n doped layer between the Si_SiO2 and the p-type epitaxial layer.

Figure 11

Figure 11 shows a collecting well for VG=3V and a barrier well for VG=-8V.

The buried channel CCD includes n and n+ doped Si to control the location of the potential well. Figure 12 shows the n epitaxial layer and the n+ implants from where the n-p junction is controlled. Biasing VREF at a positive voltage depletes the n-p junction and

Apendix A

CCD Signal and voltages:

Overview Figure 1 shows generic section of a CCD. There is a rectangular area of pixels where signal is integrated or stored. We will call this the parallel register. Three clock lines, “parallel clocks,” define each pixel line. With two clocks high (barrier phase) and one low (accumulate phase), charge can be collected and stored under the accumulate phase. Charge can be shifted from pixel line to line by sequencing the three clock phases. At the end of the parallel registers region, a line of charge is broadside loaded into a serial pixel register with an additional clock, “transfer gate.” The serial register is a linear array of pixels that accumulates, stores, and shifts charge with its own set of clock lines, “serial clocks.” At the end of the serial register is a clocked structure, “summing well,” analogous to the transfer gate, which places pixel charge on a sense capacitor that coverts charge to volts. This sense capacitor can be reset to a reference voltage with the reset transistor driven by clock signal “reset gate.” Figure 1 shows the serial register being split into two halves. Once broadside loaded, half the shift register can be shift to the left output structure and the other half to right one. This is done to decrease overall readout time. Not shown in Figure 1 is the fact that the parallel register region is subdivided into four regions, each with is own set of three-phase clocks. An example sequence of events is that the parallel clocks are configured to accumulate charge. Then a single cycle of the three clock phases plus transfer gate shifts all lines downwards by one while the bottom line is loaded into to serial register. The serial register clocks are in their accumulate configuration. Each pixel in the serial register is then converted to a voltage on a source follower output transistor via the sequence: 1) sense node is reset to the reference voltage by cycling reset gate, 2) the source follower output voltage is integrated by the DAQ, 3) the serial register three-phase clocks and summing well clock are single cycled adding the end pixel charge on the sense capacitor, 4) the source follower output voltage is integrated by the DAQ, steps 1) through 4) are repeated for the length of the serial register. The difference of each pair of integrations is the pixel charge. The CCD readout can be thought of a fast serial pixel shift do-loop nested within a slow parallel line transfer do-loop.

Signal descriptions Vp_ hc. Parallel registers clocks (a.k.a., vertical clocks) for pixel rows farthest from serial

register. Vp_Uc and Vp_Lc are bussed together.

FSp_hc. Parallel registers clocks (a.k.a., vertical clocks) for pixel rows closest to serial register. FSp_Uc and FSp_Lc are bussed together.

TG_hc. Parallel register to serial register transfer gate clocks. TG_Uc and TG_Lc are bussed together.

Hn_hc. Serial clocks for four quadrants of serial readout register (a.k.a., horizontal clocks).

SW_hc Serial register to summing well transfer clock.

OG_hc. Summing well / floating diffusion Isolation gate (DC).

RG_hc. Floating diffusion capacitor reset gate clock.

VR_hc. Floating diffusion capacitor reset reference voltage (DC)

VDD_hc. Readout source follower transistors drain voltage (DC).

VOUT_hc. Readout source follower transistors sources – output signal.Sensitivity is ~3.5 µV/e for Ids=0.6 mA and Vds=6V and 4 µs signal integration.

P+_hc. p+ guard ring contract (DC). This node is 0V; all other voltages are referenced to this.

N+_h. Imaging area n+ channel stop implant contacts (floating).

N+_hc. Readout corners n+ channel stop implant contacts (floating).

VSUB_hc. Substrate depletion voltage (DC). Nominal operating voltage is +80V.

Apendix B:

DIN IEC 751 Temperature/Resistance Table for Platinum

Sensors Temp. Temp. Res. Temp. Temp. Res. Temp. Temp. Res.

(K) (C) (ohms) (K) (C) (ohms) (K) (C) (ohms)

75 -198.2 19.319 360 86.85 133.51 650 376.85 239.08

80 -193.2 21.473 365 91.85 135.41 655 381.85 240.82

85 -188.2 23.618 370 96.85 137.31 660 386.85 242.55

90 -183.2 25.755 375 101.85 139.21 665 391.85 244.28

95 -178.2 27.883 380 106.85 141.1 670 396.85 246.01

100 -173.2 30.003 385 111.85 142.99 675 401.85 247.73

105 -168.2 32.116 390 116.85 144.88 680 406.85 249.45

110 -163.2 34.221 395 121.85 146.77 685 411.85 251.17

115 -158.2 36.319 400 126.85 148.65 690 416.85 252.88

120 -153.2 38.41 405 131.85 150.53 695 421.85 254.59

125 -148.2 40.494 410 136.85 152.4 700 426.85 256.3

130 -143.2 42.571 415 141.85 154.28 705 431.85 258.01

135 -138.2 44.642 420 146.85 156.15 710 436.85 259.71

140 -133.2 46.707 425 151.85 158.02 715 441.85 261.41

145 -128.2 48.766 430 156.85 159.88 720 446.85 263.11

150 -123.2 50.819 435 161.85 161.74 725 451.85 264.81

155 -118.2 52.867 440 166.85 163.6 730 456.85 266.5

160 -113.2 54.909 445 171.85 165.46 735 461.85 268.19

165 -108.2 56.946 450 176.85 167.31 740 466.85 269.87

170 -103.2 58.978 455 181.85 169.16 745 471.85 271.56

175 -98.15 61.005 460 186.85 171.01 750 476.85 273.24

180 -93.15 63.028 465 191.85 172.86 755 481.85 274.91

185 -88.15 65.046 470 196.85 174.7 760 486.85 276.59

190 -83.15 67.059 475 201.85 176.54 765 491.85 278.26

195 -78.15 69.068 480 206.85 178.37 770 496.85 279.93

200 -73.15 71.073 485 211.85 180.21 775 501.85 281.59

205 -68.15 73.075 490 216.85 182.04 780 506.85 283.26

210 -63.15 75.072 495 221.85 183.86 785 511.85 284.92

215 -58.15 77.065 500 226.85 185.69 790 516.85 286.57

220 -53.15 79.055 505 231.85 187.51 795 521.85 288.23

225 -48.15 81.041 510 236.85 189.33 800 526.85 289.88

230 -43.15 83.023 515 241.85 191.14 805 531.85 291.53

235 -38.15 85.003 520 246.85 192.96 810 536.85 293.17

240 -33.15 86.979 525 251.85 194.77 815 541.85 294.82

245 -28.15 88.951 530 256.85 196.57 820 546.85 296.46

250 -23.15 90.921 535 261.85 198.38 825 551.85 298.09

255 -18.15 92.887 540 266.85 200.18 830 556.85 299.73

260 -13.15 94.851 545 271.85 201.98 835 561.85 301.36

265 -8.15 96.811 550 276.85 203.78 840 566.85 302.99

270 -3.15 98.768 555 281.85 205.57 845 571.85 304.61

273.15 0 100 560 286.85 207.36 850 576.85 306.23

275 1.85 100.72 565 291.85 209.14 855 581.85 307.85

280 6.85 102.67 570 296.85 210.93 860 586.85 309.47

285 11.85 104.62 575 301.85 212.71 865 591.85 311.08

290 16.85 106.57 580 306.85 214.49 870 596.85 312.69

295 21.85 108.51 585 311.85 216.26 875 601.85 314.3

300 26.85 110.45 590 316.85 218.04 880 606.85 315.91

305 31.85 112.39 595 321.85 219.81 885 611.85 317.51

310 36.85 114.32 600 326.85 221.57 890 616.85 319.11

315 41.85 116.26 605 331.85 223.34 895 621.85 320.71

320 46.85 118.18 610 336.85 225.1 900 626.85 322.3