reliability testing and product qualification mark a. burns

© 2002 IBM Corporation

IBM Technology Group: Microelectronics Division

Reliability Testing and Product QualificationMark A. Burns

Reliability Testing & Product Qualification

2003 IBM Corporation

Mark A. Burns, [email protected] Reliability & QualificationMicroelectronics DivisionIBM Technology Group

Mr. Burns has worked as an engineer in Product Reliability and Qualification in the Microelectronics Division of IBM Technology Group since 1989. He joined IBM in its Federal Systems Division in 1987 with an M.S. in Mechanical Engineering from Standford University and B.S. in Mechanical Engineering from the University of Notre Dame. While at IBM Federal Systems, Mr. Burns worked on avionics installation, on simulation development, and in human factors engineering. Since joining IBM Technology Group, he has worked on reliability and qualification of semiconductor products and packaging technologies. Mr. Burns is an IBM representative to JEDEC on reliability testing, qualification methods, and quality systems since 2002. He achieved Certified Reliability Engineer designation by the American Society for Quality in 1994.

Presenter



IBM Microelectronics Quality SystemDevelopment ProcessQualification

Technology FeasibilityTechnology QualificationProduct Qualification

Quality and Customer SatisfactionSummary

Contents



- Customer Surveys- Returns Support- PCN Notification

Technology Qualification Product Qualification Manufacturing Quality

Market Research

Development Manufacturing

Customer

Total Team Effort

Sales Support

- Qualify technology structures - Verify wearout performance- Qualify Design Rules- Identify Critical Controls

- Set/verify product requirements- Functionality verification- Reliability assessment

- Supplier Quality Management- Change Control Management- Nonconforming Product Control- Reliability Monitoring- ISO Compliance Assurance- Customer Returns Support

- Technology Developmentprocess & design rules

- Product DevelopmentdesignprototypeRamp to Production

-Tool/Process/Equipment Controls- Electronic Routings- SPC- Product Traceability- Inspections- Voltage Screens & Burn-in

Continuous Improvement- Corrective and Preventative Actions- Adhere to the Quality Policy

Quality System


2003 IBM CorporationIntegration of Technology Process

Structured Decision Making Process (Go/No-Go funding decisions)

Cross-functionalProjectTeams

Cross-Project Management Process

Functional Organizations

Supporting Measurements and Systems

ConceptDCP

PlanDCP

ResultsDCP

PDT LMT

IPMT

Structured Development ProcessLaunch

ReadinessDCP

TECHNOLOGY DEVELOPMENT

PRODUCT REV. TO RELEASE TO MFGCONCEPT SPEC&PLAN

DESIGN TO FIRSTSAMPLE EVAL.

LAUNCH THROUGHSTABLE MFG

LIFE-CYCLEMGMT

Tech /ProductDevelopment

Product Development




PRODUCT REV. TO RELEASE TO MFGCONCEPT SPEC&PLAN

DESIGN TO FIRSTSAMPLE EVAL.

LAUNCH THROUGHSTABLE MFG

LIFE-CYCLEMGMT

Tech /ProductDevelopment

PQ Level

Qualification Complete

Qual.Activities

CustomerActivities

ProductQualityLevels

TechnologyFeasibility (TO)

Mfg Ramp

Q Level

Product Qualification (T2/SQ)- Reliability- Functionality- Application- Manufacturability

Early Product Evaluation (EPE)

Tech Mfg Readiness (TMR)

SupplementalQualifications- Process EC's- Additional Fabs (LQ)

MFG KeyActivities

P Level

Application Partnering

Samples CustomerShip

FirstDesign

T2Qual

Read.QA/EC

Line

EUHHardware

T1QualRead.QA/EC

Line

TechnologyEvaluation (T1)

Qualification & Sustaining Quality



Qualification: Reliability ManagementQualification Phases cover all reliability characteristics & driver types

Use Hours

Failure

Rate

Useful Life

InfantMortality Wearout



Reliability Components

Component Source Management Strategy

Wearout Technology robustnessDesign groundrules & simulation to remove from useful life regime

SystematicsProcess control issuesMaterial changes

Layout groundrule robustnessProcess controls

Random Defects Cleanliness Defect reductionScreening



Qualification & Sustaining Quality

PRODUCT REV. TO RELEASE TO MFG LAUNCH THROUGH


STABLE MFG

PQ

Qualification Complete

Qual.Activities

ProductQualityLevels

Technology Feasibility (TO)

Q

Product Qualification (T2)- Reliability- Functionality- Application- Manufacturability

Early Product Evaluation (EPE)

Tech Mfg Readiness (TMR)

SupplementalQualifications

- Process EC's- Additional Fabs (LQ)

P

P Level assigned to first pre-T1 lot and any RTAT Processed that skips QA Checks/screens

Technology Evaluation (T1)

Wearout control focus.............Defect control focus



Major Qualification Phases

T0

T1

T2

Technology Feasibility Materials & device viability

Technology Qualification Robust integrated process for designing

Product Qualification Qualification of component in manufacturing



Technology Feasibility (T0)

ProposedTechnology,

Application Space,Product(s)

Test sites: wafer, chip, package Possible material sets Device definitions

to select viable technology definition

Goal:Single Integrated

Process for Validation



Identifies process and design limits of technologyDeviceNew materialsDimensional/lithographic viability

Typically includesDozens of wafersHundreds or thousands of test sitesHundreds of packaged test vehicles

Can include evaluations for Chip device

Hot carriers, NBTI, gate dielectric breakdownChip wiring

Electromigration, stress migration, cycling, moisture resistancePackage compatibility

Flip chip electromigration, cycling, moisture resistance, bondability

Technology Feasibility (T0)



Technology Qualification(T1)

T1

Integrated process robustness, reliability, & manufacturing feasibility

Test site reliability, yield, & parametric performance on pilot manufacturing line

For product designsDevice models & groundrulesReliability models to control wearout & other robustness guidelines

Business commitment to

invest in manufacturing

capacity

Product committed to revenue plan



Technology Qualification (T1)Reliability testing emphasizes

Fully integrated test structuresVerifying design groundrules for reliability

Reliability testing may includeDevices (FEOL)

HCI, NBTI, gate dielectric TDDB, Radiation-Induced Soft Error Rate, ring oscillator characterization

Chip Interconnect (BEOL)EM, Stress Migration, TC, TDDB, THB

Early product life testingPackage

TC, THB, HAST, PCT, EM (C4), Wirebond evaluationsATC at card level

New materialsDimensional/lithographic viability

Typically includesHundreds of wafersThousands of test sitesHundreds of packaged test vehiclesMultiple fabrication lots



Environmental Stress

Robustness

HTS

Component qualificationBased on manufacturing line with full in-line quality control and a qualified tool setConsiderations can include

Product Qualification (T2)

Component Qualification

ApplicationDefinition

Functional Verification

Customer Verification

Manufacturability

I/O Robustness

Defect-Based Reliablity

Assembly Compatibility

Radiation-Induced Soft Error Rate

Characterization

SPQLHTOL

EFR

ESDLatch

Up

T/C THBHAST

StressFunction



Typically includes Accelerated testing on

Hundreds of fully functional componentsHundred of packaging test vehicles3-5 lots to evaluate consistency




Most commercial suppliers use JEDEC methodologies or variations for standard (COTS) productsJEDEC sanctions two principal component qualification methodologies:


Acceptance TestingApplication-Specific

Reliability Assessment

JEDEC-STD-47 JEDEC-STD-94(in approval)



Component qualification at IBM Microelectronics Utilizes some acceptance testingEmphasizes personalized

Stress designResults interpretation

Based on application and lifetime requirementsDepends heavily on developing models to translate accelerated data to application terms

Defect-based component reliability is a prime focus of modeling efforts




Defect-based component reliability is a prime focus for modeling effortsTime distributionAccelerationScreening effectiveness

IBM generally utilizes a Weibull distribution for defectsIBM generally develops a single model to represent the composite of reliability detractors in the absence of a dominant, novel mechanism

Modeling for Components



Typical defect acceleration parameters includeTemperature ~ Arrhenius:

ln AF(T) ~ Delta H / kB ((1/Tuse) - (1/Tstress)), whereDelta H is empircally derived (in eV)kB = the Boltzmann constantT = temperature (in deg K)

Voltage ln AF(V) ~ GammaV(Vstress-Vuse), where

GammaV is empirically derived

Others

Acceleration Modeling

t

Cu

mu

lati

ve F

allo

ut

Condition 2

Condition 1

Condition 3Acceleration



Electron MicroscopyScanning Electron MicroscopeTransmission Electron MicroscopyElectron microprobe analysisDual beam Focused Ion Beam

Surface analysisAuger Electron SpectroscopyLow energy X-ray analysis: XPS and ESCASecondary ionic mass spectroscopy: SIMS and TOF SIMSAtomic Force Microscopy

Chemical analysisFTIRLaser RamanSpectrometryDefraction / X-ray analysis

Full metallography labs

Diagnosis of Fallout



FIB SRAM Electrical Characterization: " Wagon Wheel"

Failure Analysis: Electrical Isolation



Failure Analysis: Cross-Sectional Analysis



Development cycle compression pressuresOpportunities for learning feedbackTest vehicle adequacyChange management

Application definitionsUntapped leverage in definition qualityEmphasis on application distributions (vs. extreme corners only)

New application spacesContinued autonomy of component reliability

Untapped leverage in system reliability partnershipNew supplier models beyond traditional models for Integrated Device Manufacturer (IDM) for finished components

Qualification Challenges



Qualification and Reliability Evaluation are one step in producing a Quality ProductAlso required

Manufacturing Quality ManagementSupplier Quality ManagementOngoing MonitoringContinuous ImprovementClosed Loop Customer Feedback

Net --- A Total Quality Management SystemThese are critical in providing consistent Quality to your customer for achieving Customer Satisfaction

Sustaining Customer Satisfaction



In-line screens and monitors Test site structures, discrete componentsProduct burn-inAccelerated stress on product samples

Next-level assembly feedbackChip-to-carrierComponent-to-cardCard in system test

Field installation feedbackDOA'sEarly life failsExtended life fails

Failure analysis to root cause drives corrective actionImmediately implement screens (a "picket fence")Drive to problem solution (a "brick wall")

Sustained Reliability Learning



Qualification phases synchronized to development phases Accelerated reliability testing is vital to cost-efficient qualifications

Necessitates understanding Materials properties and limitsApplication conditionsCustomer lifetime

Sustained high quality products and customer satisfaction require a complete Quality Management System, not just Qualification

In conclusion



(c) Copyright International Business Machines Corporation 2003

All Rights Reserved

Printed in the United States of America 2004

IBM and PowerPC Architecture are trademarks of International Business Machines Corporation in the United States, or other countries, or both.

All information contained in this document is current as of the initial date of publication and is subject to change without notice at any time. The information contained in this document represents IBM Microelectronics Division goals and objectives only and does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.

THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document.

reliability testing and product qualification mark a. burns

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