1 reliability qualification report pcb

Reliability QualificationReport

XD010-42S-D4F

303 S. Technology Ct, Broomfield CO, 80021 Phone: (800) SMI-MMIC http://www.sirenza.com

Document RQR-104282 Rev A

Initial Qualification 2004

Products Qualified by SimilarityXD010-04S-D4FXD010-12S-D4FXD010-14S-D4FXD010-22S-D2FXD010-24S-D2F

SDM-08060SDM-09060

Figure 1 : Photograph of XD010-42S-D4F

The XD010-42S-D4F has demonstrated reliable operation by passing all qualification testing in our product qualification test plan. It has been subjected to stresses such as High Temperature Operational Life, High Temperature Storage, Temperature Cycling, as well as Mechanical Shock and Vibration.

I. Qualification Overview

The XD010-42S-D4F 10W power module is a 2-stage Class A amplifier designed for use in the driver stages of linear RF power amplifiers for cellular base stations. It operates from a single voltage and has internal temperature compensation.

II. Introduction

This amplifier is manufactured using XeMOS® II, a 0.8µm, metal source contact, aluminum metallization process which utilizes a discrete Laterally Diffused MOSFET (LDMOS) transistor to achieve RF performance capabilities for the wireless communications and networking markets. The XeMOS® II process embodies the conventional NMOS processing techniques with additional features enabling it capable of high voltage, high power and high frequency operation at power levels of up to 60W at frequencies up to 2.5 GHz.

III. Fabrication Technology

The XD010-42S-D4F is a hybrid chip and wire assembly. The printed circuit board is connected to a tin/copper base plate with a eutectic solder attach. The lid is attached to the PCB with a B stage epoxy.

IV. Package Type

XD010-42S-D4F ReliabilityQualification Report

The Sirenza Microdevices qualification process consists of a series of tests designed to stress various potential failure mechanisms. This testing is performed to ensure that Sirenza Microdevices products are robust against potential failure modes that could arise from the various die and package failure mechanisms stressed. The qualification testing is based on JESD test methods common to the semiconductor industry. The manufacturing test specifications are used as the PASS/FAIL criteria for initial and final tests.Qualification tests are performed on the wafer fabrication process to demonstrate semiconductor reliability. In addition, package testing is also performed. These qualification results are detailed in Section XII.

V. Qualification Methodology

Sirenza Microdevices defines operational life testing as a DC biased elevated tempera-ture test performed at or near the maximum channel temperature limit. The purpose of the operational life test is to statistically show that the product operated at its maximum operational ratings will be reliable. The results for this test are expressed in device hours that are calculated by multiplying the total number of devices passing the test by the number of hours tested.

VII. Operational Life Testing

A device can be qualified by similarity to previously qualified products provided that nonew potential failure modes/mechanisms are possible in the new design. The following products are qualified by similarity:

VI. Qualification By Similarity

XD010-04S-D4F XD010-12S-D4F XD010-14S-D4F XD010-22S-D2FXD010-24S-D2F SDM-08060 SDM-09060

15

Quantity

15,000

Device Hours

175°C1000 hours

August 2004

Channel Temperature

Test Duration

HTOL Completion Date


Sirenza Microdevices classifies Human Body Model (HBM) electrostatic discharge (ESD) according to the JESD22-A114 convention. All pin pair combinations were tested. Each pin pair is stressed at one state voltage level using 1 positive and 1 negative pulse polarity to determine the weakest pin pair combination. The weakest pin pair is tested with 3 devices below and above the failure voltage level to classify the part. The Pass Fail status of a part is determined by the manufacturing test specification. The ESD class quoted indicated that the device passed expose to certain voltage, but does not pass the next higher level. The following table indicates the ESD sensitivity classification levels. The XD010-42S-D4F is a class 3B device.

IX. Electrostatic Discharge Classification

Class Passes Fails0 0 V <250 V

1A 250 V 500 V1B 500 V 1000 V1C 1000 V 2000 V2 2000 V 4000 V

3A 4000 V 8000 V3B 8000V

Device ClassXD010-42S-D4F 3B

All others 3B

X. Qualification Test Results for XD010-42S-D4F

Results PASS

Temperature Range -55°C to 125°C, 10 min dwell, 1 minute transition,200 cycles

Test Conditions

JESD22-A104Test Standard

9Number of Devices Under Test

Temperature Cycling Loose Device (Air to Air Thermal Shock)

Group A1

Results PASS

Channel Temperature = 175°C, Test Duration = 1000 hoursTest Conditions



High Temperature Operational LifeGroup A2


Results PASSJESD22-B103JESD22-B104

Test Standard


Vibration + Mechanical ShockGroup E

X. Qualification Test Results for XD010-42S-D4F (con’t)

Results PASS

Temperature = 100°C, Test Duration = 1000 hoursTest Conditions



High Temp StorageGroup D

Results PASS

Dip & Look; Steam Age Condition C, 8hrs; Solder Dip Condition A, 215CTest Conditions

JESD22-B102Test Standard


SolderabilityGroup H


One key issue in performing the qualification testing is to accurately determine the junction temperature of the device. Sirenza Microdevices uses a 3um spot size infraredcamera that allows a device to be measured at its normal operational parameters. The 3um spot size allows for very good resolution compared to the heated area of the transistor, which in this case is approximately 1-2um. The results for the 1st stage, running at maximum operational current of 230mA, a device voltage of 28V, and a base plate lead temperature of 90oC are as follows:

XI. Junction Temperature Determination

Figure 2: Infrared Thermal Image of Stage 1, XD010-42S-D4F


The results for the 2nd stage, running at maximum operational current of 1001 mA, a device voltage of 28V, and a base plate lead temperature of 90 oC are as follows:

XI. Junction Temperature Determination (con’t)

Figure 3: Infrared Thermal Image of Stage 2, XD010-42S-D4F


The XeMOS® II process qualification test vehicle uses a 30W die packaged in a ceramic A191 package using a Au/Si eutectic die attach and wire bonded with aluminum wire. The cumulative qualification results are summarized in the table below. (Reference RQR-104230)

XII. XeMOS® II Process Qualification

PassPassPassPass

87922

87922

372665M3940633A47603C0882

MIL-STD-883, Test Method 1005.8, 175+5, -0C,1000 Hours

High Temperature Operating Life (HTOL)

PassPassPassPass

1313155

1313155

3726653A45553C0882

PLST0810

JESD22-A110Bparagraph 3.1, row 1110C, 85% RHBias=26V264 Hours

Temperature Humidity Bias

PassPassPass

131619

131619

M394063351106372665

JESD22-A110Bparagraph 3.1, row 1500 Hours

Temperature Humidity, Unbiased

PassPassPass

161616

161616

3A4555372665

M394063

MIL-STD-750Method 1042.3Test Cond A,Bias Volt. = 48VTemp = 175CTime = 160hrs

High Temperature Reverse Bias (HTRB)

PassPassPass

181616

181616

3940633A4555372665

MIL-STD-750Method 1042.3Test Cond. BGate Bias = 16VTemp = 175C, Time = 48hrs

High Temperature Gate Bias (HTGB)

Results*QtyOut

QtyIn

Lot # (s)Test Standard/MethodTest Description


XII. XeMOS® II Process Qualification (con’t)

PassPassPass

161718

161718

3726653A4555394063

MIL-STD-883Method 1010.7Test Condition C1000 Cycles

Temperature Cycling

PassPassPassPass

12121212

12121212

281701 281702351106394063

MIL-STD-883E Method 2012.7

Eutectic Die Attach

PassPassPassPass

12121212

12121212

281701281702351106394063

MIL-STD-883 Method 2011.7Bond Pull Strength

Results*QtyOut

QtyIn

Lot # (s)Test Standard/MethodTest Description

*Failure Criteria:Test Description Symbol Pre Stress Post StressGate to Source Threshold Voltage Vgs(th) 2< Vgs <5 +/-50mVDrain Source On Resistance Rdson < 300mO +/-15%Gate Leakage Current Igss <600nA +/-200nADrain Source Leakage Current Idss <=1uA +/-500nA


XII. XeMOS® II Process Qualification (con’t) - Electromigration

880@T=190C

0.1623119.587/

379.506

2/0.7J=5 mA/um2)T=250C

M2EM

Predicted Lifetime

(yrs)0.1%

σT 0.1 (hrs)/

T 50 (hrs)

n/Ea(eV)Stress Conditions

Element/Structure

Item


The graph below is the MTTF due to metal migration for 4 different drain currents on 10W die based on Black’s Equations and measured data. The geometries of the 4W, 30W and 60W die are the same relative to electromigration failures.

XII. XeMOS® II Process Qualification (con’t) - MTTF

MTTF for XeMOS II 10W Die

1.00E+05

1.00E+06

1.00E+07

1.00E+08

1.00E+09

1.00E+10

100 110 120 130 140 150 160 170 180 190 200 210 220

Junction Temp(C)

MTT

F(ho

urs)

0.5A1.0A1.5A2.0A


The package qualification test is a hybrid chip and wire assembly. The printed circuit board is connected to a tin/copper base plate with a eutectic solder attach. The lid is attached to the PCB with a B stage epoxy.

XIII. Package Qualification


Results PASSMIL-STD-883EMethod 2002.4Condition B

Test Standard


Mechanical Shock

Results PASSMIL-STD-883EMethod 1010.7Condition A

Test Standard


Lead Integrity (Tension)

Results PASS

Temperature Range -55°C to 125°C, 10 min dwell, 1 minute transition,100 cycles

Test Conditions

MIL-STD-883EMethod 1010.7

Test Standard


Temperature Cycling

Results PASSMIL-STD-883EMethod 1010.7Condition A

Test Standard


Lead Integrity (Bending Stress)

932371140 °C

1355490 °C

FIT90% CL

FIT60% CL

Tj

High temperature operating life tests was performed on 10W die at Tj= 180°C with a sample size of 108 devices for 6624 hours. Total device hours is 715392 dev-hours withzero failures. An activation energy of 0.5 eV is used.

XII. XeMOS® II Process Qualification (con’t) - FIT

1 reliability qualification report pcb

Technology

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similarity xd010

photograph of xd010

introductionthe xd010

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