Application ReportSCAA077–July 2005

Phase Noise/Phase Jitter Performance of CDCM7005 atVarious UMTS, CDMA-xx, and 802.16 Frequencies

Kal Mustafa/Firoj Kabir .................................................................................................... Clock Drivers

ABSTRACT

This application brief presents phase-noise data taken on Texas InstrumentsCDCM7005 jitter cleaner and synchronizer PLL. The phase noise performance of theCDCM7005 depends on the phase noise of the reference clock, VCXO clock, and theCDC7005 itself. This applications brief shows the phase noise performance of TexasInstruments clock synthesizer CDCM7005 at most popular UMTS, CDMA, and 802.16frequencies. It helps the user in choosing the right clocking solution for their particularapplications. These test results confirm that the CDCM7005 can provide clocks betterthan –145 dBc/Hz phase noises at 1-MHz offset from the carrier frequency. Low phasenoise is required for most base station application such as UMTS, CDMAxx, and802.16 and their derivatives as well as many other jitter stringent applications.

Contents1 Introduction .......................................................................................... 22 Test Equipment and Setup ....................................................................... 33 Summary and Conclusion........................................................................ 164 Acknowledgement................................................................................. 175 References......................................................................................... 17

List of Figures

1 Test Equipment Setup ............................................................................. 42 Passive Loop Filter Circuit......................................................................... 43 Phase Noise Performance of Agilent E8257C 10MHz REF_IN ............................. 44 Phase Noise Performance of CDCM7005 Outputs at 30.72 MHz .......................... 45 Phase Noise Performance of CDCM7005 Outputs at 61.44 MHz .......................... 56 Phase Noise Performance of CDCM7005 Outputs at 76.80 MHz .......................... 67 Phase Noise Performance of CDCM7005 Outputs at 78.6432 MHz ....................... 78 Phase Noise Performance of CDCM7005 Outputs at 92.160 MHz ......................... 89 Phase Noise Performance of CDCM7005 Outputs at 122.88 MHz ......................... 910 Phase Noise Performance of CDCM7005 Outputs at 245.76 MHz ....................... 1011 Phase Noise Performance of CDCM7005 Outputs at 320 MHz ........................... 1112 Phase Noise Performance of CDCM7005 Outputs at 400 MHz ........................... 1213 Phase Noise Performance of CDCM7005 Outputs at 491.52 MHz ........................ 1314 Phase Noise Performance of CDCM7005 Outputs at 500 MHz ........................... 1415 Additive Phase Noise Performance of CDCM7005 LVPECL Output at 245.76 MHz

(Buffer Mode) ...................................................................................... 15

List of Tables

1 Additive Phase Jitter (CDCM7005 Jitter Contribution Without REF and VCXO) ......... 15

2 Summary of Phase Jitter Measurements Across Various Frequencies.................... 15

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 1

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1 Introduction

1.1 Definitions

Introduction

The CDCM7005 is a low phase noise/low jitter clock synthesizer and jitter cleaner with programmableLVPECL and LVCMOS outputs. An external low-pass loop filter in addition to an external VCXO (VCO) isrequired to complete the phase locked loop circuitry. Proper selection of the VCXO and loop bandwidth iscritical to achieve the best performance from the CDCM7005. A loop bandwidth calculator is available onTexas Instruments website (www.ti.com).

This report includes phase noise plots of most common frequencies used in base station and customerpremise equipment (CPE) applications. In addition, the phase noise of the clock source feeding theCDCM7005 is included for completeness.

The phase noise of the 10-MHz reference, the various Toyocom’s VCXOs (TCO-2111), and output phasenoise of the CDCM7005 are included. The peak-to-peak and the RMS jitter were calculated from thephase noise plots over a frequency band of interest using the PN9000 phase noise measurement system.In addition, additive phase jitter of the CDCM7005 is included. The jitter data is taken with a Toyocom’s245.76-MHz VCXO and a divided ratio of this frequency. This data illustrates the jitter performance of theCDCM7005 alone and precludes jitter contributions of external clock reference and the VCXO being used.Additive time/phase jitter plots are shown in Figure 13.

The timing budget is defined by dynamic (jitter) and static errors (skew). Depending on the systemarchitecture, a sub-set of parameters out of the data sheet is only affecting the timing budget. Jitter is atiming distribution of the clock signal and expresses the edge deviation from ideal. Jitter is composed ofboth deterministic and random (Gaussian) content.

Jitter is any edge deviation from the ideal. The causes of jitter include: power supply noise, thermal andmechanical noise from the input signal, reflection, EMI, and random noise. A few suggestions for reducingjitter include: power supply bypassing (10-47 µF) to prevent voltage droop and ripple due to currentsurges, filtering each VCC pin (w/ 0.1 µF) low effective series resistance capacitor, using propertermination, using differential signaling as opposed to single-ended signaling, and minimizing noisecoupling by isolating other high frequency signals from the clock driver.

Phase Noise (PN) is the short-term instability caused by variation of frequency (phase) of a signalreferenced to the carrier level and a function of the carrier offset (i.e., relative noise level within a 1-Hzbandwidth). Integration of PN over a given frequency band yields phase jitter RMS.

Phase jitter or accumulated jitter is the absolute deviation of a clock edge from its ideal position intiming. While period jitter only accounts for the variation between clock periods, phase jitter accumulatesthe error of each period and therefore is always larger. The wider the recording time window is, the morefrequency bandwidth becomes integrated into the total phase jitter. Phase jitter can also be measured byintegrating phase noise over the frequency band of interest. Either way, the system designer must specifythe minimum and maximum frequency for the integration.

For set-up and hold-time budget calculation, the PP value of the phase jitter is important. Note that onlythe added phase noise by the clock driver is of interest to find the worse edge position between themaster clock in the system and the subsystem. The absolute phase jitter of the master clock itself adds toall clock signals in the system, thus canceling its effect.

Period jitter is the deviation in cycle time of a signal with respect to an ideal period over a random sampleof cycles. Period jitter is important since it includes the max/min frequency and it specifics the shortestclock period. It is important for the set-up and hold-time budget. Calculation with period jitter is sufficientfor sub-systems using clock and data signals derived by the same clock source. Use phase jitter tocalculate your jitter budget in case a signal comes into such subsystem from an external clock source(e.g., use of ADC, SerDes) or is generated from the clock source that feeds the clock buffer of interest.Period jitter can be measured with any oscilloscope. The trigger input and signal input both must be drivenfrom the output of the clock driver.

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies2 SCAA077–July 2005

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1.2 ADC and SerDes System

2 Test Equipment and Setup

Test Equipment and Setup

Peak-to-peak (PP) period jitter is the total jitter range from minimum to maximum values of a clocksignal. PP jitter increases indefinitely with recording time. Thus, PP jitter values are only meaningful ifeither the recording length or the relative bit error rate is known.

RMS period jitter is one standard deviation (1 σ) of the PP jitter of a clock signal. RMS jitter is only validfor Gaussian (normal) distribution. RMS jitter is independent of the sampling window, and thus, bettersuited to compare performance of two or more devices where sampling time window differs or is unknown.

Cycle-to-cycle (CC) period jitter, a.k.a. adjacent cycle jitter, is the variation in cycle time of a signalbetween consecutive cycles over a random sample of successive cycle pairs. CC jitter is also a goodvalue to calculate the set-up and hold-time budget since it defines the min/max variation of the timingvariation from ideal for the next clock edge.

Crosstalk, another name for parasitic coupling between signals, is the effect of capacitive coupling tocause a logic transition. Capacitive coupling is the transfer of energy between nearby switching integratedcircuits. The coupling depends on factors such as the distance between the traces, the signal swing, theoperating frequency, and the permittivity of the silicon dioxide. Coupling can be improved by physicallyincreasing the distance between the traces. Power and ground planes can also act as shields to minimizecrosstalk

When using the AD converter and SerDes transceiver, the incoming data is often sourced by a completelyindependent clock source and not synchronized to the main system clock (at least no short-termsynchronization). Thus, the absolute phase jitter becomes important. A lower frequency band limit must beestablished (e.g., 12 kHz to full range). For the AD converter, the limit on the low side relates to thesampling window of the ADC that becomes further processed by digital algorithms (e.g. DSP tap size for aFFT). For a SerDes PLL, low phase jitter is critical around the PLL’s bandwidth. Thus, jitter frequency hasan upper and low limit (e.g., 12 kHz–20 MHz for OC-48).

All measurements were taken at nominal 3.3-V power supply, room temperature, and PLL lock condition.The CDCM7005 evaluation module (EVM) in 1x mode, various Toyocom’s VCXOs, the Agilent E8257Csignal generator and the PN9000 phase noise test system. The below test setup were used for the allphase noise testing. The phase noise can be measured up to 100 MHz from carrier frequency. Althoughsome measurements were taken up to 10 MHz or 1 MHz from the carrier depending upon the desiredclock frequency.

The PN9000 automatic phase noise test system from Aeroflex was used to measure the phase noise andthe phase jitter was calculated from phase noise plots at various bandwidths.

Several CDCM7005 EVMs was used to take the output phase noise measurement.

All LVPECL and LVCMOS outputs were properly terminated. Figure 1 shows the test setup used for allphase noise testing.

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 3

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CDCM7005

VCXO

AgilentE8257CSignal Generator

Power SupplyHP6624A

Phase Noise AnalyzerPN9000

OscilloscopeTDS694C

CDCM7005 EVM

PC

SPI

REF_IN

PassiveFilter

Y0

Y0B

PC

B0065-02

100 nF

S0092-01

22 µF

4700 Ω

100 nF

160 Ω

G001

G002

Test Equipment and Setup

Figure 1. Test Equipment Setup

Figure 2. Passive Loop Filter Circuit

Figure 3. Phase Noise Performance of Agilent Figure 4. Phase Noise Performance of CDCM7005E8257C 10MHz REF_IN Outputs at 30.72 MHz

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies4 SCAA077–July 2005

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G003

Test Equipment and Setup

Figure 5. Phase Noise Performance of CDCM7005 Outputs at 61.44 MHz

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 5

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G004

Test Equipment and Setup

Figure 6. Phase Noise Performance of CDCM7005 Outputs at 76.80 MHz

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies6 SCAA077–July 2005

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G005

Test Equipment and Setup

Figure 7. Phase Noise Performance of CDCM7005 Outputs at 78.6432 MHz

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 7

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G006

Test Equipment and Setup

Figure 8. Phase Noise Performance of CDCM7005 Outputs at 92.160 MHz

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies8 SCAA077–July 2005

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G007

Test Equipment and Setup

Figure 9. Phase Noise Performance of CDCM7005 Outputs at 122.88 MHz

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 9

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G008

Test Equipment and Setup

Figure 10. Phase Noise Performance of CDCM7005 Outputs at 245.76 MHz

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies10 SCAA077–July 2005

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G009

Test Equipment and Setup

Figure 11. Phase Noise Performance of CDCM7005 Outputs at 320 MHz

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 11

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G010

Test Equipment and Setup

Figure 12. Phase Noise Performance of CDCM7005 Outputs at 400 MHz

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies12 SCAA077–July 2005

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G011

Test Equipment and Setup

Figure 13. Phase Noise Performance of CDCM7005 Outputs at 491.52 MHz

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 13

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G012

Test Equipment and Setup

Figure 14. Phase Noise Performance of CDCM7005 Outputs at 500 MHz

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies14 SCAA077–July 2005

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G013

Test Equipment and Setup

Figure 15. Additive Phase Noise Performance of CDCM7005 LVPECL Output at 245.76 MHz (BufferMode)

Table 1. Additive Phase Jitter (CDCM7005 Jitter Contribution Without REF and VCXO)

DUT FREQUENCY PHASE JITTER (ps/fs)(MHz) 200 kHz – 5 MHz 200 kHz – 10 MHz 10 kHz – 20 MHz

PP RMS PP RMS PP RMS

CDCM7005 245.76 136 23 201 34 348 58

CDCM7005 122.88 519 86 694 116 996 166

CDCM7005 61.44 853 142 1.15p 192 x x

CDCM7005 30.72 1.71p 285 2.36p 393 x x

Table 2. Summary of Phase Jitter Measurements Across Various Frequencies

DUT FREQUENCY PHASE JITTER (ps/fs)(MHz) 200 kHz – 5 MHz 200 kHz – 10 MHz 10 kHz – 20 MHz

PP RMS PP RMS PP RMS

Agilent E8257C Sig Gen 10 17.18p (1) 2.68p (1) x x x x

VCXO 30.72 2.19p 364 2.95p 492 x x

CDCM7005/LVPECL 30.72 2.21p 368 3.04p 546 x x

CDCM7005/LVCMOS 30.72 2.26p 377 3.12p 520 x x

(1) This data is taken from 200 kHz to 1 MHz.

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 15

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3 Summary and Conclusion

Summary and Conclusion

Table 2. Summary of Phase Jitter Measurements Across Various Frequencies (continued)

DUT FREQUENCY PHASE JITTER (ps/fs)(MHz) 200 kHz – 5 MHz 200 kHz – 10 MHz 10 kHz – 20 MHz

PP RMS PP RMS PP RMS

VCXO 61.44 2.43p 405 3.32p 553 x x

CDCM7005/LVPECL 61.44 2.81p 468 3.91p 652 x x

CDCM7005/LVCMOS 61.44 2.44p 408 3.38p 564 x x

VCXO 76.8 1.61p 268 2.27p 378 x x

CDCM7005/LVPECL 76.8 1.75p 291 2.49p 414 x x

CDCM7005/LVCMOS 76.8 1.88p 312 2.66p 444 x x

VCXO 78.6432 1.17p 195 1.69p 281 x x

CDCM7005/LVPECL 78.6432 1.19p 199 1.70p 284 x x

CDCM7005/LVCMOS 78.6432 1.23p 204 1.71p 285 x x

VCXO 92.16 1.23p 205 1.72p 287 2.59p 429

CDCM7005/LVPECL 92.16 1.37p 228 1.92p 320 2.79p 466

CDCM7005/LVCMOS 92.16 1.24p 206 1.74p 290 2.59p 432

VCXO 122.88 1.14p 190 1.54p 256 2.07p 345

CDCM7005/LVPECL 122.88 1.18p 196 1.61p 269 2.27p 378

CDCM7005/LVCMOS 122.88 1.18p 197 1.59p 265 2.33p 389

VCXO 245.76 486 81 694 116 1.04p 173

CDCM7005/LVPECL 245.76 515 86 738 123 1.08p 180

CDCM7005/LVCMOS 245.76 621 103 861 144 1.21p 201

VCXO 320 425 71 609 102 950 158

CDCM7005/LVPECL 320 428 71 616 103 951 159

CDCM7005/LVCMOS 320 517 86 706 117 1.04p 174

VCXO 400 286 48 389 65 557 93

CDCM7005/LVPECL 400 298 50 405 68 579 97

VCXO 491.52 354 59 489 82 677 113

CDCM7005/LVPECL 491.52 364 61 502 84 684 140

VCXO 500 262 43 343 57 475 79

CDCM7005/LVPECL 500 263 43 348 57 480 80

The CDC7005 PLL tracks the input reference signal up to the loop bandwidth, while it follows the VCO(here VCXO) phase noise floor at frequencies above the loop bandwidth. The VCXO performance iscritical for achieving good PLL’s phase noise performance and meeting stringent requirements in basestation applications. From the above data it is evident that a low phase noise clock output is easilyattainable from the CDCM7005 with the proper selection of VCXO. These test results confirm that theCDCM7005 can provide clocks better than –145-dBc/Hz phase noises at 1-MHz offset from the carrierfrequency. Low phase noise is required for most base station applications such as UMTS, CDMAxx, and802.16 and their derivatives as well as many other jitter stringent applications.

The additive phase-noise data clearly indicates that as a buffer, the CDCM7005 adds a few femto-secondjitter to its input. The added jitter number may vary over frequency. For more information about theCDCM7005, see the device data sheet.

Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies16 SCAA077–July 2005

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4 Acknowledgement

5 References

Acknowledgement

The authors of this application brief would like to thank the following people for proving the necessarysamples and equipments in conducting these tests:

1. Treisch, Ron, Texas Instruments, RF Wireless Group, r-treisch@ti.com2. Paul Woodley, O&M Sales, Inc., Paul, Woodley@o-m-sales.com3. Kory Moser, Toyocom USA, moser@toyocom.com4. Heather McClendon, Texas Instruments, heather.mcclendon@ti.com

1. CDCM7005 data sheet, Texas Instruments, (SCAS685)2. CDC7005 EVM User’s Guide, Texas Instruments, (SCAU005)

SCAA077–July 2005 Phase Noise/Phase Jitter Performance of CDCM7005 at Various UMTS, CDMA-xx, and 802.16 Frequencies 17

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