pcb layout for - sharif university of technology …ee.sharif.edu/~kaboli/pcb layout for switching...
TRANSCRIPT
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" PCB Layout for Switching Regulators "
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Introduction• Linear series pass regulator
GAIN
VOUTILVIN
REFRL
• Series pass device drops the necessary voltage to maintain VOUT at it’s programmed value
• Power Loss = (VIN – VOUT) * IL– e.g. 12V in, 3.3V/5A out, Power Loss = 43.5W
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Introduction• Switching regulator
• Power ≠ (VIN – VOUT) * IL– When switch is closed V = 0, I = IL– When switch open V = VIN, I = 0– Theoretically zero power loss with ideal switch– e.g. η = 90%, Power loss = 1.83W versus 43.5W
PWM GAIN
REF
FILTERVIN VOUT
IL
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Introduction
• But we now have high slewing currents and voltages
• Switching regulator
PWM GAIN
REF
FILTERVIN VOUT
IL
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DC Resistance• Copper is not a perfect conductor
– Efficiency– Regulation– Thermals
Material μΩ-cm μΩ-inSilver 1.5 0.59
Copper 1.70 0.67
Silver (Plated) 1.8 0.71
Gold 2.2 0.87
Copper (Plated) 6.0 2.36
Palladium 11 4.3
Tin (Plated) 11 4.33
Tin -Lead 15 5.91
Lead 22.0 8.66A
Curre
nt F
low
l
AlR ρ
=
yresistivit=ρ
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DC Resistance• Copper resistivity = 0.67μΩ in. at 25°C.
– At 279°C it doubles• Count squares to estimate trace resistance
t
Current Flowl
lt
R
tR
ρ
ρ
=
=)()(
l
l
R of = R of
• 1.0mΩ(½ oz Cu)• 0.2mΩ(2oz Cu )
=
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Count Squares
• Estimate resistance of input trace
• PSU Spec:– 3.3V to 1.8V/20A– η = 87%– IIN = 12.54A
Cu WeightOz.
Thicknessmm (mils)
mΩ/Square25oC
mΩ/Square100oC
1/2 0.02 (0.7) 1.0 1.3
1 0.04 (1.4) 0.5 0.65
2 0.07 (2.8) 0.2 0.26
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Count Squares
• 6.4 squares
• Using ½ oz Cu– R= 6.4mΩ at 25°C– PDISS = 0.98W = 18% of losses
• Using 2 oz Cu– R = 1.28mΩ at 25°C– PDISS = 0.2W = 3.7% of losses
2.8 squares 3.6 squares
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Vias Have Resistance Too• 1A to 3A per via
– 20mil via with 1 mil plating
AlR ρ
=
Ω=−•××
=−
mR 4.2)001.002.0001.0(
063.01036.22
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π
)( 2tdtlR−•
=π
ρ
0.5 mm(20 mils)
d
0.025 mm(1.0 mil) t
1.6 mm(63 mils)
CurrentFlow
l
A
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Vias Have Resistance Too
171 at 2.4mΩ/via⇒R = 14μΩ
• Second Cu layer => total trace R = 0.64mΩ
• PDISS = 0.1W
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AC Parasitics. Inductance
• Self inductance of PCB trace– Changes in trace width has a small impact on
self inductance.
nHwt
nL
nHwt
nL
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟
⎠⎞
⎜⎝⎛
+=
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟
⎠⎞
⎜⎝⎛
+=
5.05
5.02
ll
ll
Wmm (in)
tmm (in)
Inductance nH/cm (nH/in)
0.25 (0.01) 0.07 (0.0028) 9.7 (24.4)2.5 (0.1) 0.07 (0.0028) 5.6 (13.9)12.5 (0.5) 0.07 (0.0028) 2.4 (6)
• A 10x increase in width only halves the inductance
for inches
for cm
wt
Curre
nt Flo
wl
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AC Parasitics. Inductance• Traces over ground planes reduces self
inductance
nH/cm 2whlL =
nH/in 5whlL =
w
h
CurrentFlow
hmm (in)
wmm (in)
Inductance nH/cm (nH/in)
InductanceNo ground plane
nH/cm (nH/in)
1.6 (0.063) 2.5 (0.1) 1.3 (3.2)
2.0 (5.0)
5.6 (13.9)
2.5 (0.1) 2.5 (0.1) 5.6 (13.9)
• A ground plane can reduce inductance by a factor of 4
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X
Yy
x
T
Time (s)2.00u 3.00u 4.00u 5.00u
Vol
tage
(V)
-2.28
0.00
2.28
Current Loops and Inductance• Keep loop area with high di/dt’s small
X
Y
T
Time (s)2.00u 3.00u 4.00u 5.00u
Vol
tage
(V)
-2.59
0.00
2.59
Loop area A = X * YBAD
Loop area A = (X*Y) - (x*y)GOOD
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AC Parasitics. Capacitance• Two Cu plates with PCB material dielectric
– Two 10 mil traces on a multi layer PCB, 10 mil between layers
tAC OR ××
=εε
( ) ( )3
2312
1025.0100.25109.14
−
−−
×××
=C
pFC 01.0=
Note: 10 mil = 0.25 mm.
A = 0.25 mm x 0.25 mm
Permittivity of FR4 ≈ 4.7εo = 8.84 x 10 -12
( )t1041.9 12 AC
−×=
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AC Parasitics. Capacitance• Five 1.3 x 0.7 mm in summing junction can increase
parasitic capacitance to 1pF.⇒1V/nsec = 1mA through 1pF.
Critical components
CPARASITIC
1
2
3
4
7
7
7
7
12
11
10
9
13
14
16
15
5
6
7
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ILIM/SYNC
VDD
OSNS
FB
COMP
SS/SD
RT
SGND
BOOT1
HDRV
SW
BOOT2
PVDD
LDRV
PGND
PWRGD
TPS40020
PowerPAD
VIN
VOUT12nsec
12V
1mA
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Single Point Grounding
• Simple wiring• Common impedance
causes different potentials
• High impedance at high frequency (>10 kHz)
• Complicated wiring• Low differential potentials
at low frequencies• High impedance at high
frequency (>10 kHz)
1 2 3 1 2 3
Series Parallel
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Multi Point Grounding
• Ground plane provides low impedance between circuits to minimize potential differences
• Also, reduces inductance of circuit traces• Goal is to contain high frequency currents in individual
circuits and keep out of ground plane
1 2 3
Ground Plane
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PSU Layout Guide1. Place power components only
– with regard to thermal, mech., elect. and safety reqs.
2. Place input filter– symmetrical layout, immediately adjacent to input
and away from FET, trafo, inductor, etc.3. Place FET drivers
– star point at FET source pin4. Place control and associated parts
– star point at IC GND pin– star point at IC GND pin– sense points = output terminals
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Q1 L
C2
A
C1 Q2
B
C
D
E
Place Power Components
F
DC
AC
AC
DC
• Typical circulating current when Q1 is ON
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Place Power Components
Q1 L
C2C1 Q2
A
B
C
D
EF
AC
DC
• Typical circulating current when Q2 is ON
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Place Power Components
Q1 L
COUTCIN Q2
A
B
C
D
EF
AC
DCDC
AC
• Circulating currents combine in some traces
High di/dt in these current paths
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Place Power Components• Draw schematic to reflect good layout
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Place Power Components
DC
DC
Q1 ON Current flow• High side FET ON
– Use short and direct paths
– Minimum loop area– Separate dc & ac paths– Separate input &
output paths
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Place Power Components
DC
• Low side FET ON– Use short and direct
paths– Minimum loop area– Separate dc & ac paths– Separate input &
output paths
Q2 ON Current flow
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Place Filter Components
• Filter components placed between input and power train.
• Place close to connector
Input Filter
Output Filter
Keep AC current in small loop
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Scope Probes• Measuring noise
– Use a small ground connector
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Place Filter Components
• Input location A or B?– Input ripple at
C10 versus C12
Input BInput A
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Place Filter Components
• Input A– 40mVpp ripple– 16mVp spike
• Input B– 70mVpp ripple– 110mVp spike
Input BInput A
50mV/div20mV/div
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Place Filter Components
• Output location A or B?– Input ripple at
C10 versus C12
Output A
Output B
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Place Filter Components
• Output A– 12mVpp ripple– 7mVp spike
• Output B– 20mVpp ripple– 17mVp spike
Output A
Output B
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Place FET Drivers
• FET gate charging and discharging.– di/dt greater than 100A/μsec (1.5A/15nsec)– dv/dt greater than 200V/μsec (3V/15nsec)
Q1 L
COUTCINQ2
C1
C3
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Place FET Drivers
• Place with:– Short and direct paths– Minimum loop area– Cross other tracks at
90° reduces capacitive coupling
• Trace from IC to Q1 gate is 0.852”, width is 0.03” on 2oz copper:– LPARA = 6.23nH– VIND = 0.623V
Poor Driver Layout
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Place FET Drivers
• Place with:– Short and direct paths– Minimum loop area– Cross other tracks at
90° reduces capacitive coupling
• Trace from IC to Q1 gate is 0.852”, width is 0.03” on 2oz copper:– LPARA = 6.23nH– VIND = 0.623V
Better Driver Layout
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Place Control and Associated Parts
• Connect resistors close to FB pin
• Remote sense at load, voltage divider at IC
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Layout A
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Layout A
• Input Ripple– 40mVpp ripple– 34mVp spike
• Output Ripple– 12mVpp ripple– 20mVp spike
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Layout B
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Layout B
• Input Ripple– 40mVpp ripple– 16mVp spike
• Output Ripple– 12mVpp ripple– 7mVp spike
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Layout A
• Input Ripple– 40mVpp ripple– 34mVp spike
• Output Ripple– 12mVpp ripple– 20mVp spike
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PSU Layout Guide
• Join components:– Use short and direct paths (minimize inductance)– Minimum loop area
• single sided PCB1. Go and return paths immediately adjacent
• double sided PCB:1. Ground planes top & bottom, no breaks, no floating areas2. One ground plane, no breaks, no floating areas3. Go and return paths over each other4. Go and return paths immediately adjacent, track direction: E-W on
one side, N-S on other– Separate dc & ac paths– Separate input & output paths– Four terminal connections (Kelvin connections)– Star common connections (no daisy chains)
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Appendix
• Discussion of layout rules and differences in lab.
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Place Control and Associated Parts
• Many control IC’s recognize noisy/quiet circuit areas and pin out accordingly
• Some even provide a separate pin for power and analog ground
• Good practice plans layout around pin out, uses a ground plane and keeps high current out of it
Sig
nal c
ircui
ts
Pow
er circuits
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Layout A
• 4 layers• Input GND connected directly to output
GND• High side FET driver return• F/B node
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Layout B
• 2 layer board• Improved high side gate return• Improved input GND and output GND
decoupling• Smaller F/B trace
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PSU Layout Guide
• Join components:– Use short and direct paths (minimize inductance)– Minimum loop area
• single sided PCB1. Go and return paths immediately adjacent
• double sided PCB:1. Ground planes top & bottom, no breaks, no floating areas2. One ground plane, no breaks, no floating areas3. Go and return paths over each other4. Go and return paths immediately adjacent, track direction: E-W on
one side, N-S on other– Separate dc & ac paths– Separate input & output paths– Four terminal connections (Kelvin connections)– Star common connections (no daisy chains)