application note skya21004: pcb layout guidelines · skya21004: pcb layout guidelines introduction...

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 203721A • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • September 22, 2015 1

APPLICATION NOTE

SKYA21004: PCB Layout Guidelines Introduction PCB layout design is essential to better performance, reliability and manufacturability. Malfunctions from noise, which may hurt the system stability, have become an increasing problem, and may therefore generate more failures and reliability malfunctions in production lines.

In this document, several considerations and guidelines for SKYA21004 PCB layout design are presented to improve performance, reliability, and manufacturability.

Guidelines for Land Pattern and Thermal Vias on the SKYA21004 The SKYA21004 is a QFN 36L package with a center ground pad (exposed pad). The PCB center ground pad serves three major functions: electrical ground, thermal heat sink, and mechanical support. Ground pad size and soldering quality (such as the wetting and voids) directly affect the ground pad functions. Dimensions of the center ground pad are shown in Figure 1. The center ground pad should be well connected to the terminal ground pad and the common ground plane of the PCB to optimize its functions.

Figure 1 shows the recommended land pattern for the SKYA21004.

Figure 1. Recommended Land Pattern and Thermal Vias for the SKYA21004 (All dimensions are in millimeters)

APPLICATION NOTE • SKYA21004: PCB LAYOUT GUIDELINES

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 2 September 22, 2015 • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • 203721A

Electrical and Thermal Performance To improve thermal and electrical performance of a mounted SKYA21004, an array of thermal vias placed on the area of the ground pad should be connected to the internal and bottom common ground copper planes of the PCB. In general, there is a direct correlation between the thermal via cross-sectional area and the heat dissipation rate. However, large and excessive thermal vias may introduce more voids in the solder joint and actually reduce overall heat dissipation performance.

Recommended thermal vias are 0.30 mm to 0.33 mm in diameter, and via barrels should be plated with 1 oz. of copper to plug the vias. The thermal via array should be arranged evenly with a pitch of 0.5 mm to 1.0 mm. For the exposed region of the ground pad, if the plating thickness is not sufficient to effectively plug the barrel of the via when plated, solder mask should be used to cap the vias with a minimum dimension equal to the via diameter plus 0.1 mm. This will prevent solder wicking through the thermal via during the soldering process, resulting in voiding.

Another way to plug thermal vias uses solder mask tenting on the bottom of the copper plane. Solder mask tenting must completely cover the vias.

In the SKYA21004 layout, it is recommended to arrange 24ea vias evenly with a pitch 0.6 mm, as shown in Figure 1.

For more detailed information refer to the Skyworks Application Note #101752I.

Guidelines for the Boost Section for LED Backlight Driving and LCD Bias Power The SKYA21004 is divided into two blocks as its operating purpose. One is a LED Backlight Driving Boost Section and the other is an LCD Bias Power Boost Section. To prevent interactive noise between two individual power blocks (LCD Bias Power and LED Driver), use independent planes for PGND (power ground for LCD Bias Power) and WPGND (power ground for LED Driver).

APPLICATION NOTE • SKYA21004 LAYOUT GUIDELINES


Y2380

FB

VDDAVDD

SKYA21004

SGND

1

FOSC32

CS1233

CS3434

CS5635

PWM

3

WPG

ND4

WPG

ND5

WLX

6

WLX

7

GND

2

GND

8

REF

9

FBN

10

DRVN

12

DRVP 14

EN 15

FBP 16

PGND 17

SDA

30

WCO

MP

29

OVP

27

OUT

26

DGND

25

VL23

IN22

AGND

21

FB20

COM

P19

LED1

LED2

LED3

OVP

OUT

FB

AVDD

LCD Supply Input

FBP

EN_LCD

VGH

5 V

FBP

VDD

PWM

OVP

OUT (up to 28 V)

BL Supply Input

SCL

24SC

L

WEN

28BL

_EN

GND

11

NC36

ISET31

VDD 13

LX 18

SDA

VIN

VGL

X

470 nF

0.22 μF 10 μF

8 nF

0.1 μF

2.2 μF

0.22 μF

4.7 μH

4.7 μH

4.7 μF

2.2 μF 2.2 μF

2.2 μF 2.2 μF 2.2 μF

0.22 μF 0.22 μF

1 μF

0.22 μF

0.22 μF

0.1 μF

0.1 μF0.1 μF

0.1 μF

2.2 μF

100 pF

10 kΩ

34.8 kΩ

22 kΩ

11 kΩ

10 kΩ

200 kΩ

226 kΩ

301 kΩ

6.04 kΩ

1 MΩ

45.3 kΩ

37.4 kΩ

NC

NC

NCD1

WPG

ND4

WPG

ND5

OUT (up to 28 V)

Supply Input0

4.7 μH

4.7 μF

D1

V

2.2 μF 2.2 μF 2.2 μF

Figure 2. SKYA21004 LED Driver Boost Section

Layout of LED Driver Boost Section Procedure

1. Connect the inductor and diode as close to the WLX node as possible.

2. Connect CIN capacitor close to the inductor and COUT capacitor(s) close to the diode.

3. Connect the COUT ground return and IC WPGND with direct wide and short trace. If needed, connect the ground return on multiple layers with multiple vias connected.

4. Make the PCB traces between CIN and inductor, inductor and WLX pin, WLX pin and diode, diode and COUT as wide and as short as possible.

5. The trace should be wider than 1.5 mm.

6. Isolate the WPGND return from the AGND, DGND, SGND, and GND. Connect the WPGND to the system ground near the system input.



Y2381

FB

VDDAVDD

SKYA21004

SGND

1

FOSC32

CS1233

CS3434

CS5635

PWM

3

WPG

ND4

WPG

ND5

WLX

6

WLX

7

GND

2

GND

8

REF

9

FBN

10

DRVN

12

DRVP 14

EN 15

FBP 16

PGND 17

SDA

30

WCO

MP

29

OVP

27

OUT

26

DGND

25

VL23

IN22

AGND

21

FB20

COM

P19

LED1

LED2

LED3

OVP

OUT

FB

AVDD

LCD Supply Input

FBP

EN_LCD

VGH

5 V

FBP

VDD

PWM

OVP

OUT (up to 28 V)

BL Supply Input

SCL

24SC

L

WEN

28BL

_EN

GND

11

NC36

ISET31

VDD 13

LX 18

SDA

VIN

VGL

X

470 nF

0.22 μF 10 μF

8 nF

0.1 μF

2.2 μF

0.22 μF

4.7 μH

4.7 μH

4.7 μF

2.2 μF 2.2 μF

2.2 μF 2.2 μF 2.2 μF

0.22 μF 0.22 μF

1 μF

0.22 μF

0.22 μF

0.1 μF

0.1 μF0.1 μF

0.1 μF

2.2 μF

100 pF

10 kΩ

34.8 kΩ

22 kΩ

11 kΩ

10 kΩ

200 kΩ

226 kΩ

301 kΩ

6.04 kΩ

1 MΩ

45.3 kΩ

37.4 kΩ

NC

NC

NCD1

PGND 17

LX 18

2.2 μF4.7 μH 2.2 μF 2.2 μF 2.2 μF

0 kΩ

226 kΩNC

pp y p

10 μF

N

Figure 3. SKYA21004 LCD Bias Power Boost Section and Charge Pump Section

Layout of LCD Driver Boost and Charge Pump Section Procedure

1. Connect the inductor and diode as close to the LX node as possible.

2. Connect CIN and COUT capacitor(s) as close to the IC as possible.

3. Connect the COUT ground return and IC PGND as close as possible.

4. Make the PCB traces between CIN and inductor, inductor and LX pin, LX pin and diode, diode and COUT as wide and as short as possible.

5. Trace should be wider than 1.5 mm. Connect all grounds of the charge pump to PGND.

6. Isolate the PGND return from the AGND, DGND, SGND, and GND.

7. Connect the PGND to the system ground near the system input.



FOSC

CS12

CS34

CS56

SDA

SGND GN

D

GND

PWM

WPG

ND

WPG

ND WLX

WLX REF

FBN

GND

DRVN

WCO

MP

WEN

OVP

OUT

DGND

SCL

VL IN AGND

FB COM

P

EP33

34

35

36

31

32

ISET

NC

PGND

FBP

EN

DRVP

LX

VDD

16

15

14

13

18

17

t0095

28 27 26 25 24 23 22 21 20 1930

3 4 5 6 7 8 9 10 11 121 229

Figure 4. SKYA21004 Pinout

Figure 5. SKYA21004 Layout Example (Boost Section)



Guidelines of Analog and Feedback Section The Analog and Feedback section is an important block for stable system operation. For stable operation, these sections should be

isolated from the noise of the boost and charge pump section. Grounds for the analog and feedback sections should be connected to the plane of AGND, DGND, SGND, and GND.

Y2382

FB

VDDAVDD

SKYA21004

SGND

1

FOSC32

CS1233

CS3434

CS5635

PWM

3

WPG

ND4

WPG

ND5

WLX

6

WLX

7

GND

2

GND

8

REF

9

FBN

10

DRVN

12

DRVP 14

EN 15

FBP 16

PGND 17

SDA

30

WCO

MP

29

OVP

27

OUT

26

DGND

25

VL23

IN22

AGND

21

FB20

COM

P19

LED1

LED2

LED3

OVP

OUT

FB

AVDD

LCD Supply Input

FBP

EN_LCD

VGH

5 V

FBP

VDD

PWM

OVP

OUT (up to 28 V)

BL Supply Input

SCL

24SC

L

WEN

28BL

_EN

GND

11

NC36

ISET31

VDD 13

LX 18

SDA

VIN

VGL

X

470 nF

0.22 μF 10 μF

8 nF

0.1 μF

2.2 μF

0.22 μF

4.7 μH

4.7 μH

4.7 μF

2.2 μF 2.2 μF

2.2 μF 2.2 μF 2.2 μF

0.22 μF 0.22 μF

1 μF

0.22 μF

0.22 μF

0.1 μF

0.1 μF0.1 μF

0.1 μF

2.2 μF

100 pF

10 kΩ

34.8 kΩ

22 kΩ

11 kΩ

10 kΩ

200 kΩ

226 kΩ

301 kΩ

6.04 kΩ

1 MΩ

45.3 kΩ

37.4 kΩ

NC

NC

NCD1

LE

LE

LE

34.8 kΩ

22 kΩ

OVP

OUT

FBSCLBL

_EN

SDA

VIN

470 nF

0.22 μF

8 nF

0.1 μF

100 pF

10 kΩ200 kΩ

Figure 6. SKYA21004 Analog Section

Layout of Analog Section Procedure

1. Connect the resistors and capacitors for IN, OUT, VL, COMP, WCOMP, ISET, FOSC, and OVP as close to the IC as possible.

2. Connect to DGND ground plane for ground return.

3. Use the same ground plane for AGND, DGND, SGND, and GND.

Feedback Layout Design Considerations

Feedback sensing points – All feedback points including FB, FBP, FBN, and OVP should be sensed from the output capacitor for stable and precise output feedback.

Routing of the feedback line – To avoid coupling effects, sensitive lines should not be routed on top of the digital or switching signal. Sensitive lines also should not be placed in parallel with a digital or switching signal.



Y2383

FB

VDDAVDD

SKYA21004

SGND

1

FOSC32

CS1233

CS3434

CS5635

PWM

3

WPG

ND4

WPG

ND5

WLX

6

WLX

7

GND

2

GND

8

REF

9

FBN

10

DRVN

12

DRVP 14

EN 15

FBP 16

PGND 17

SDA

30

WCO

MP

29

OVP

27

OUT

26

DGND

25

VL23

IN22

AGND

21

FB20

COM

P19

LED1

LED2

LED3

OVP

OUT

FB

AVDD

LCD Supply Input

FBP

EN_LCD

VGH

5 V

FBP

VDD

PWM

OVP

OUT (up to 28 V)

BL Supply Input

SCL

24SC

L

WEN

28BL

_EN

GND

11

NC36

ISET31

VDD 13

LX 18

SDA

VIN

VGL

X

470 nF

0.22 μF 10 μF

8 nF

0.1 μF

2.2 μF

0.22 μF

4.7 μH

4.7 μH

4.7 μF

2.2 μF 2.2 μF

2.2 μF 2.2 μF 2.2 μF

0.22 μF 0.22 μF

1 μF

0.22 μF

0.22 μF

0.1 μF

0.1 μF0.1 μF

0.1 μF

2.2 μF

100 pF

10 kΩ

34.8 kΩ

22 kΩ

11 kΩ

10 kΩ

200 kΩ

226 kΩ

301 kΩ

6.04 kΩ

1 MΩ

45.3 kΩ

37.4 kΩ

NC

NC

NCD1

OVP2

1 MΩ

45.3 kΩ

o 28 V)

9 10

F

6.04 0

3NC

FBP

10 kΩ

301 kΩNC

FB

AVAA DD

11 kΩ

226 kΩC

Figure 7. SKYA21004 Feedback Section

Layout of Feedback Section Procedure

1. Connect the OVP resistors to the OUT capacitors with a dedicated ground shielded trace to avoid interference from other signals. This trace is used as a feedback for the WLED boost regulator.

2. Connect the AVDD/VGH/VGL feedback resistors to the OUT capacitors with a dedicated ground shielded trace.

3. To avoid coupling effects, sensitive lines should not be routed on top of the digital or switching signal.

4. When connecting nodes from the other layer, use at least four 0.4 mm hole diameter, 0.7mm pad diameter vias (conductive filled via is preferred).

Figure 8. Example of Routing the Sensitive Line



FOSC

CS12

CS34

CS56

SDA

SGND GN

D

GND

PWM

WPG

ND

WPG

ND WLX

WLX REF

FBN

GND

DRVN

WCO

MP

WEN

OVP

OUT

DGND

SCL

VL IN AGND

FB COM

P

EP33

34

35

36

31

32

ISET

NC

PGND

FBP

EN

DRVP

LX

VDD

16

15

14

13

18

17

t0095

28 27 26 25 24 23 22 21 20 1930

3 4 5 6 7 8 9 10 11 121 229

Figure 9. SKA21004 Pinout

Figure 10. SKYA21004 Layout Example (Analog and Feedback Section)



Copyright © 2015 Skyworks Solutions, Inc. All Rights Reserved.

Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.

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application note skya21004: pcb layout guidelines · skya21004: pcb layout guidelines introduction...

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