o inner tracker upgradeg. darbo – infn / genova milano, 10 february 2015 inner tracker upgrade x...

oInner Tracker UpgradeG. Darbo – INFN / Genova Milano, 10 February 2015

Inner Tracker Upgrade

X Workshop ATLAS Italia10 – 12 February 2015

G. Darbo – INFN / Genova

Indico: https://agenda.infn.it/conferenceDisplay.py?confId=8955

https://agenda.infn.it/conferenceDisplay.py?confId=8955

https://agenda.infn.it/conferenceDisplay.py?confId=8955

Inner Tracker UpgradeG.Darbo – INFN / Genova Milano, 10 February 20152

Inner Tracker Project

ATLAS ITk project taking off:• Project kick-off meeting (4 Nov ‘14) chaired by Leo;• 93 Institutes and 21 countries joined ITk;• 6 Italian Institutes already in ATLAS (BO, CS,GE, LE,

MI, UD) – Trento asked to join ATLAS and then ITk.

ITk Institute Board (IB)• Under Leo, the search committee to find the first

chair of the ITk-IB has been formed: C Buttar, Marina Cobal, Abe Seiden (chair), Nobu Unno, Norbert Wermes and Dave Charlton hope new chair for first IB meeting.

• First ITk-IB meeting (26th Feb) in ITk-week, where we will discuss various items including the effort tables collated by Leo and a discussion of the critical gaps in coverage for certain areas.

Country Number of institutions

Australia 3

Canada 7

CERN 1

China 1 (cluster)

Czech Republic 3

Denmark 1

France 6

Germany 10

Italy 6: BO, CS, GE, LE, MI, UD

Japan 7

Netherland 1

Norway 2

Poland 2

Russia 1

Switzerland 2

Spain 2

Slovenia 1

Sweden 2

South Africa 1 (cluster)

Taiwan 1

United Kingdom 12

United States 21

Total 93

Trento raised formal request to join ATLAS


ITk Descoping Scenario

• LHCC request a cost document for ATLAS Phase II with possible de-scoping – document ready for discussion on 15th Sep, draft to LHCC for June.

• ATLAS mandate a subgroup of the USC to study 3 scenarios: 275, 235 and 200 MCHF (old CHF rate!).

• For ITk too short time to focus on “preferred” layout (many under study see Layout TF).• Concentrate on LoI layout + extension at h = 4• For ITk should be considered as pure exercise: not what we are going to build,

but how performance goes with de-scoping• Effort must be coherent with CMS


ITk “275” layout

• LoI + VF extension to h = 4• Not clear if we can simulate rings in

time (presumably not…)• Should be possible to move to 25x100

pixel size (occupancy/rates)

CostStrips 95.7 MPixel 24.8 MCommon 11.0 MVF extension 12.0 MSavings (wrt LoI) -8.7 M–––––––––––––––––––––––––Total 134.8 M

Ref.: P. Morettini – R&D Phase II Italia – 23/1/2015



WRT “275”:• VF extension only to h=3.2• Strip “stub” layer removed

Cost“275” 134.8 MVF to h=3.2 -6.0 MStub -2.0 M–––––––––––––––––––––––––Total 126.8 M




WRT “275”:• VF extension only to h=3.2• 1 strip barrel and 1 disk set removed• 2 strip barrel single layer (not stereo)


Cost“275” 134.8 MVF to h = 3.2 -6.0 M1 barrel+1disk -24.0 M2 barrel layers -7.0 M–––––––––––––––––––––––––Total 97.8 M


Layout TF Work Model

ITk Layout tasks force

• New Task Force (Claudia e Andy chairs), with mandate to define the ITk layout go down in options, by end 2015.

• Need help for simulation (interesting task for young people too).

To study: Local supports for layers 3-4

(inclined planes, like “alpine” less silicon and material)

Look at extra pixel layer(s) with cheaper technologies to replace strips.

Realistic simulation of services and routings.

R/O sizing based on detector characteristics.



SLIM – Stiff Longeron for ITk Staves

IP Barrel Cells Tilted Cells

Connecting Structure

5th pixel layer inside the PST – HV-CMOS “optimized” – 2.5 m long at layer 5.

one slim stave is equivalent to two adjacent conventional staves

Ref.: S. Michal, ITk Pixel Design Group, 29/01/2015


SLIM – Material BudgetLower surface and consequently lower cost

22 % less for a 1.5 m stave at layer 5 39 % less for a 2.5 m stave at layer 5

Note: only structural cells studied

Ref.: S. Michal, ITk Pixel Design Group, 29/01/2015


RD_FASE2Tracker R&D in CSN1


3D Sensors with FBK: TN + FBK

IBL like 3D sensor on 6” – FBK and Trento• 1st 3D test batch on 6” wafers finished, all wafers tested. • Test structures show good breakdown behaviour. • Defect rate higher than IBL (DRIE process, partially understood),

no totally good FE-I4! • One wafer will be bump-bonded at IZM/Selex with special

bump-mask: leave unconnected pixel column with low VBD

• Planning irradiation & test-beam with FE-I4/PSI46dig

ATLAS FE-I4 (13x) CMS Single chip (24x)(1E, 2E, 3E, 4E)

CMS Quads (6x)(2E, 3E)

MEDIPIX2 (4x)

NA62 test chip (20x)

275

µm

Partially etched junction columns

Column (10÷13 µm) partially filled with doped poly-silicon

Passing-through ohmic columns

250µ

m

Good IV Pixel columns:BB to FE-I4 pixel

Bad IV Pixel columns: disconnect from Pixel inputs

One FE-I4 tile: IV for 80 cols of 336 pixels

Ref.: G. Giacomini – R&D Phase II Italia

Proc

ess

x-se

ction


3D / Active Edge – RD_FASE2New generation of 3D sensors• Single-sided process on SiSi

DWB and SOI substrates – Substrates from IceMOS;

• 100÷130 µm thick active layer;• Technology suitable for new

RD53 Pixel chips (small 50x50 or 25x100 µm2 pixels) and low threshold (~1000 e-) operation;

• Design for 2x1016 neq/cm2;• Strategy: 3 technical batches

funded by CSN1 (ATLAS/CMS) + [1 batch of Active edge planar sensors]

Batch 1 – mechanical test• DRIE test of 100 ÷ 150 µm

narrow (5 µm) columns;• Test filling with poly.

P- Epi layer / P- High Ω•cm wafer

P++ Low Ω•cm wafer

-Vb

Charge Amp.Bump-bond

metal

Thin-down

Single side 3D process

p++ col

n++ col

SOI –

SiS

i DW

B

158

um

5.6 um

3.8 um

Ref.: M. Boscardin and S. Ronchin, FBK

100÷130µmOpt.: 200 nm oxide (SOI)

DRIE for ohmic columns


3D / Active Edge – RD_FASE2Batch 2 – substrates test

• p-type SiSi DWB wafers from IceMOS • 100 ÷ 130 µm high-R active sensor thickness • p-spray & p-stop isolation • Started in Sept. 2014, completed in Nov. 2014 • Good electrical characteristics – from CV

measurements depletion is in accordance with nominal thickness of active (device) substrate.

Module assembly:• 5 wafers will be processed by IZM:

Substrate thinning Metallisation with mask of back BCB processing for HV isolation

• 1 wafer bump-bonded by Selex

Table: good tiles per wafers:• ATLAS (1) – Current limit 0.2 µA, VBD ≥ 100V• CMS (2) – Current limit 50 nA, VBD ≥ 100V

CMSATLAS

wafer # material thickness p-spray ATLAS (1)

CMS (2)

30 Si-Si 100 2.00E+12 9 / 10 20 / 30

33 Si-Si 100 2.00E+12 8 / 10 17 / 30

49 Si-Si 100 2.00E+12 8 / 10 20 / 30

63 Si-Si 130 2.50E+12 7 / 10 25 / 30

69 Si-Si 130 2.50E+12 10 / 10 26 / 30

74 Si-Si 130 2.00E+12 8 / 10 19 / 30

75 Si-Si 130 2.00E+12 7 / 10 14 / 30

80 Si-Si 130 1.50E+12 10 / 10 26 / 30

81 Si-Si 130 1.50E+12 8 / 10 26 / 30

1 FZ 275 2.00E+12

FE-I4


3D / Active Edge – RD_FASE2Batch 3 – 3D with new substrates• Test small pixels cells with FE-I4 – tricky layout

mixing small pixels and grounded/larger pixels (see example)

• Wafer layout and cell simulation in advanced stage – parameters extracted from batch 1 and 2 will be used for the new design

• About 2 month delay accumulated since start of the project: some concern with the DRIE machine at FBK (14 weeks asked for repair) – becoming difficult to have process finished before summer.

• Substrates• IceMOS SiSi substrates (baseline option):

already in house• Shinetsu epitaxial substrates: given-up (not

fulfilling specifications)• SOI substrates: we are going to order some

wafers (could be used given delay of DRIE).

2x50 + 2x450 4x50 + grid

50 µ

m45

0 µm

45

0 µm

450 fF

450 fF

50 fF


Thinking Towards ITk ModulesAssume ITk layer 1 & 2 with 3D• Need 3000 RD53 chips/single tile sensors to cover the ~1 m2 area.• Considering 25 tiles/wafer (6”), 50 % yield in sensors and 50 % in good tiles to

used modules: 600 wafers are needed• FBK + CNM (maybe SINTEF) are in the business – pre-production + production

from 2018 to 2021.• Requested exercise: evaluate feasibility and cost!

Considerations on bump-bonding• Complete qualification at Selex with 6” sensor wafers, FE-I4 like modules;• Discuss with Selex plans for R&D and involvement in ITk production:

R&D/Upgrade needs at Selex: qualify process for 120k bumps/chip, upgrade to 12” wafers (RD53 wafers).

Consider 8.2 m2 of hybrid pixels is Selex interested in part of it? • Direct playing with FBK and Selex make easier optimization of BB for 3D sensor

and “sell” the full package to the collaboration.


Steering R/O R&D ActivitiesTable-top ROD/BOC version (BO)• Use expertise on IBL ROD, no VME needs• Full SW/FW compatibility with PIT cards• Half ROD, up to 16 FE• Funded by CSN1

Possible activities on read-out• Expand existing FE-I4 R/O systems to

HV/HR-CMOS (see bottom fig.)• Common HW/FW/SW interface definition • Integrate mini-DCS in the read-out• GBT concentrator

FE

Generic R/O systemUSBPix

RCEROD/BOCPCIExpress

FPGALV

CTRLTX

RXMod TX/RX



Evaporative CO2 cooling Milano

2014 Activities• Completed design of TRACI v.3

100 W transportable CO2 recirculating system Collaboration: CERN, NIKHEF, MILANO, SHEFFIELD,

OXFORD, LIVERPOOL Test on M PUMPS, Corbola (RO)

• Purchased all components: Being part of collaboration allows purchase sharing In Milano co-funded by LHCb and Dotazioni

2015 Plans• Assemble and Commissioning TRACI• Needed for LHCb and for ATLAS

• Finite Element Analysis of stave designs based onmini-piping – well known expertise of the MI group from IBL Ti pipe, 2 mm𝜙

• Test of prototypes with TRACI Need to build a setup based on TRACI,

similar to what done for IBL

17

TRACI

Thermal simulation (IBL)

Test setup (IBL)


RD_FASE2 – “Richieste 2015”

Legend:

ATLAS Common ATLAS / CMS

Attività Descrizione BO CS GE MI TN UD

3D

6" Wafer procurement (SOI, wafer bonding, epi) - - - - 10.0 -

PicoScope 6407 Digitizer with 1.5 GHz probes and accessories. - - - - 8.5 -

BB

6" dummy wafers - test deposition on 6" and high-density bumps (150 k-bumps/chip) - - - 20.0 - -

BB for 3D sensor test - - 24.0 - - -

MODUpgarde R/O Systems - 2.0 2.0 2.0 - 2.0

Module assembly and irradiation, RD on flex - - 10.0 - - -

MM-R/O Multi module R/O 15.0 - - - - -

CO2/µCH Develop µ-channel cooling - - - 10.0 - -

Total requested by ATLAS 15.0 2.0 36.0 32.0 18.5 2.0

105.5

Trento:• Request of 4 k€ of Travel Money

for test-beam participation and support.

Aggiornare con

assegnazioni


HVR_CCPDActivities on HV/HR-CMOS in CSN5 – BO, GE, MI


HVR_CCPD: The project


STM Chip


Hybridization


AIDA-2020 : Funded !AIDA-2020 Funded !• AIDA-2020 has been officially selected by the

EC with a funding of 10 M€.

The project has a ranking of 14.5/15 with• 5/5 excellence• 5/5 impact• 4.5 implementation

The grant agreement procedure is quite fast

Groups in ATLAS who havebeen funded:• Genova• Milano• Trento


Conclusions

ITk project moving ahead:• Kick-off meeting, Institute Board, …• De-scoping scenarios under study• Layout TF

RD_FASE2 • Activities on sensors/modules progressing… constructive activity with CMS

HVR_CCPD• Test chip submitted with STM• Hybridization work progressing, few devices assembled at Genova tested in TB

AIDA2020• Project approved, new resources and R&D framework for HL-LHC developments


SPARE SLIDES


Activities in ITkITk management looking at interest of Countries in ITk R&D’s

Table from discussion with Paolo. Comments?

For discussion

o inner tracker upgradeg. darbo – infn / genova milano, 10 february 2015 inner tracker upgrade x...

Documents

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darbo infn genova milano

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layout loi vf extension

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atlas phase

loi layout extension