oRD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014

Pixel : LS1, Run2 and Fase 2

Slides per Clara

17 September 2014

G. Darbo– INFN / Genova

Indico agenda:• https://agenda.infn.it/conferenceDisplay.py?confId=8420

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 2

2014 Activities – 2015 Plan2014: CSN1 funded (Feb and May) R&D Phase 2 activities for ATLAS & CMS inner trackers.• Development of 3D and Active Edge sensors with FBK – 3 Batches (ATLAS/CMS)• Bump-bonding: development of Indium bumps (6” sensors) and produce modules• Develop a technology for pixel detector hybridization using C (dielectric) instead of R

(bump-bonding) coupling• Completion of CO2 test plant (combined ATLAS / LHCb)

2015: Activities and line of funding• Continue with 3D Sensor plan: produce modules, test in lab and TB, irradiate, procure

sensors for next FBK run.• Bump-bonding: for testing FBK sensors and to develop for future RD53 requirements• CO2 cooling: contribute to ATLAS stave R&D, thermal simulation and test with CO2

plant• Multi-module R/O: use leading experience of ROD designer (BO) to develop a 16

module table-top road for architecture study and for test-beam application.• Upgrade to USBPix3: most diffused single module system based on USB. Upgrade also

for use if HV/HR-CMOS• HV/HR-CMOS: presented a new project in CSN5 (BO, GE, MI)

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 3

3D Sensor Program - 2014Planned 3 run at FBK in 2014 – Funded by CSN1 in Feb• No.1: DRIE process setting up for thin columns. Process in completion. Found that 5-6

µm are the best suitable column diameter.

• No.2: test planar process with SiSi DWB and Epi substrates. Layout completed, mask submission, wafer expected in 6 weeks.

• No.3: 3D single side process with SiSi DWB and Epi substrates. Layout in discussion. Compatible layout with other foundries (CNM) to simplify common test of devices.

Note:• A second 3D run is foreseen at the

end of 2015 / early 2016 – layout matching RD-53 layout.

Schedule presented in Feb’14. Still up to date. Need approval from MEMS3 committee of 3rd batch!

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 4

FBK: Status of BatchesBatch 1: study of columns

In measurement

Batch 2: study SiSi subtratesMask submitted 15

8 um

5.6 um

3.8 um

CMSATLAS

Test structures for Si-Si qualification

Batch 3: 3D sensors

Layout study and Simulation of a3D pixel cell

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 5

CCPD HybridizationHV/HR-CMOS chip coupled capacitively to R/O chip (CCPD – Capacitively Coupled Pixel Detector) instead of “classic” bump-bonding• Develop a technique to insert uniform, well defined

thickness of dielectric between R/O and HV/HR-CMOS chips

• Should be a cost effective, rad-hard process to transfer to industry

Test program in progress:• See preliminary results next slide

Activities will continue in the HVR_CCPD project in CSN5 (new experiment)• Involving BO, GE & MI• Also scientists outside ATLAS will participate.

R/O CHIP

R/O CHIP

Process Recipe Spin SU-8 photoresistPattern pillars by mask

Spacer define the distance between chips

Target to D = 5 µm, C ~ 4 fF for 18 µm pad diameter.

Proper qualified glue

Glue deposition

R/O CHIPDETECTOR CHIPAlign & pressure

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Deposition of Pillars (spacers)2-inch mask below with different Densities of spacers – FE-I4/FE-I3 Structures.

SU8-2005 deposited on 2-inch wafer from Siegert

Credits: V. Ceriale

FE-I4 with matrix of SU8 spacers:200 µm x 200 µm columns 4.7 µm high

FE-I4 with matrix of SU8 spacers:40 µm x 40 µm columns 4.7 µm high

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2014 - CO2 Cooling Plant

Attilio…

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 8

Milestones

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 9

SPARE SLIDES

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3D Sensors – Proposed Process

New generation of 3D sensors• 6” wafer new process at FBK• Smaller pixel (event pileup)• reduce column distance (2x1016 neq/cm2) • Thinner pixel (≤1.5ke threshold)• TCAD simulation: Optimal Q, Lower Cdet ,… • Bias voltage applied to back side (as IBL)

Single side 3D process on:• Si-Si DWB (Direct Wafer Bonding)• Epitaxial wafers

P+ Epi layer / P+ High Ω•cm wafer

P++ Low Ω•cm wafer

-Vb

Charge Amp.Bump-bond

100÷150µm

metal

Thin-down

TCAD capacitance simulation

• Layout: 2 n-columns in 25x150 µm2

• Total capacitance for dcol=5µm• 100 µm thick 71 fF/pix• 150 µm thick 88 fF/pix

• It was 200 fF/pix for IBL

Single side 3D process

p++ col

n++ col

Epi –

SiS

i DW

B

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 11

DRIE for Ohmic Columns

158

um

5.6 um

3.8 um

7.6 um

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DRIE for Junction Columns

ID# Nominal diameter (um)

Depth(um)

Surface diameter (um)

Diameter at tip (um)

5.1 5 99 3.5 3.2

5.5 5 99.5 5.5 2.95.5 5 100 5.5 3.55.6 5 98 4.3 2.65.8 5 98 5.5 2.65.9 5 98 3.9 2.95.10 5 95 3.3 2.75.11 5 95 3.3 2.7

LEFT

CENTER

RIGHT

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Planar test batch

CMSATLAS

Test structures for Si-Si qualification

• p-type SiSi DWB wafers from ICEMOS

• 100-mm and 130-mm HR active sensor thickness

•p-spray & p-stop isolation

•Layout ready, masks ordered

• To start now, to be completedin 6-7 weeks

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Wafers Sets – To Bump-Bond

In program 4 sensor batches that would need BB in 2014/15:• 3D double side – October - Funds (MI) assigned for 2014• Planar ATLAS/CMS Batch 2 – November – Funds (FI/PI) assigned 2014• 3D and Active edge batches coming 2015 – no funds yet. In 2015 request

14

ATLAS FE-I4 (13x) CMS Single chip (24x)(1E, 2E, 3E, 4E)

CMS Quads (6x)(2E, 3E)

MEDIPIX2 (4x)

NA62 test chip (20x)

CMSATLAS

Test structures for Si-Si qualification

3D Double Side Batch Planar ATLAS/CMS “Batch 2”

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 15

SU8-2005 Results

1.26 µm of bow. Column highs are very uniform: 4.7 µm over 2 cmResults obtained with a spinning rotation of 2500 rpm and SU8-2005

Profile scan direction

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Future Plan: M-Module R/OLe caratteristiche della scheda sono:• Completa compatibilità firmware e software con il ROD/BOC IBL ROD/BOC in one card• Possibilità di operare senza crate (table-top)• Connessione ottica o elettrica di 16 FE-I4• Possibilità di connessione esterna via Gbit ETH, S-Link (Modalità compatibile con FW/SW IBL)• Possibilità di utilizzo per test GBT/FELIX, con uscita PCIe e protocolli Infiniband, rapid-io, 40-100 GBe

Costi:• Prototipaggio e fabbricazione di due schede 10 k€• Realizzazione di 5 schede per i laboratori italiani 15 k€• Componenti off-shelf per il sistema 10 k€

Attività BO-GEPrototipi 2015Produzione 5 schede 2016

RD_FASE2 – Slides per ClaraG. Darbo – INFN / Genova Roma, 17 September 2014 17

Got Funded3D• Funded 3 batches at FBK: • Mechanical test – approved by MEMS3 committee – order placed (3x2200 €)• Simple planar to qualify substrates – approved by MEMS3 – order placed (6x2200 €)• 3D batch, single side, on hold waiting batch 2.

• Substrates• Ordered 55 wafers from IceMOS (SiSi wafer bonded) – material is on shipment• Looking for Epi wafers – indirect contact with SHINETSU – offer received (25 wafers –

11.9 kCHF) – doubts on specifications (epi-layer thickness spread: 104÷156 µm!)

Bump-bonding• Funded 20 k€ for BB at Selex + 7 k€ for FE-I4B• Bump-bond 3D sensors in production at FBK – old design IBL-like • Develop In-bumps for high density – incomplete funding (cut the dummy wafers).

HV-CMOS hybridization• FE-I4B plus consumables to test hybridization

CO2 cooling• Funded TRACI CO2 cooler