nonratioed and ratioed logic static cmos circuits...ßpass-transistor ßnonratioed and ratioed logic...

B.Supmonchai August 1st, 2004

2102-545 Digital ICs 1

Chapter 6

Static CMOS Circuits

Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory

August , 2004; Revised - June 28, 2005

2102-545 Digital ICs Static CMOS Circuits 2

B.Supmonchai

Goals of This Chapter

q In-depth discussion of CMOS logic families

ß Static and Dynamic

ß Pass-Transistor

ß Nonratioed and Ratioed Logic

q Optimizing gate metrics

ß Area, Speed, Energy or Robustness

q High Performance circuit-design techniques


B.Supmonchai

Combinational Sequential

Output = f(In)

CombinationalLogic

CircuitOutIn

CombinationalLogic

CircuitOutIn

State

Output = f(In, Previous In)

Combinational vs. Sequential Logic


B.Supmonchai

Static CMOS Circuits

q At every point in time (except during the switchingtransients) each gate output is connected to eitherVDD or VSS via a low-resistance path.

q The outputs of the gates assume at all times thevalue of the Boolean function, implemented by thecircuit (ignoring, once again, the transient effectsduring switching periods)

q This is in contrast to the dynamic circuit class, whichrelies on temporary storage of signal values on thecapacitance of high impedance circuit nodes




B.Supmonchai

PUN and PDN are dual logic networks

F(In1,In2,…InN)

VDD

In1

PUN

PDN

In2

InN

……

In1

In2

InN

Static Complementary CMOS

PMOS transistors only

NMOS transistors only

Pull-Up Network: make a connectionfrom VDD to F when F(In1,In2,…InN) = 1

Pull-Down Network: make a connectionfrom F to GND when F(In1,In2,…InN) = 0


B.Supmonchai

Threshold Drops

PDN

PUN

CL

VDD Æ

VDD

0 Æ

CL

VDD

VDD

VDD Æ

CL

0 Æ

VDD

CL

S

D

S

D S

D

VGS

S

D

VGS

VDD VDD - VTn

0 |VTp|


B.Supmonchai

A

BA B

Construction of PDN

q Transistors can be thought as a switch controlled by itsgate signal

q NMOS switch closes when switch control input is high

NMOS Transistors pass a “strong” 0 but a “weak” 1

A • B

Series = NAND

A + B

Parallel = NOR


B.Supmonchai

Construction of PUN

q PMOS switch closes when switch control input is low.

PMOS Transistors pass a “strong” 0 but a “weak” 1

A

BA B

Series = NOR

A • B = A + B

Parallel = NAND

A + B = A • B




B.Supmonchai

Duality of PUN and PDN

q PUN and PDN are dual networks

ß De Morgan’s theorems

ß A parallel connection of transistors in the PUNcorresponds to a series connection of the PDN

q Complementary gate is naturally inverting(NAND, NOR, AOI, OAI)

q Number of transistors for an N-input logic gate is 2N

A + B = A • B [!(A + B) = !A • !B or !(A | B) = !A & !B]

A • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B]


B.Supmonchai

A • B

A

B

A B

011

101

110

100

FBA

Example: CMOS NAND gate

VDD

A

BF

PDN: G = A · B

PUN: F = A + B

Conduction to GND

Conduction to VDD

G(In1, In2, …, InN) = F(In1, In2, …, InN)


B.Supmonchai

Example: CMOS NOR gate

A + B

A

B

A B

VDD

011

001

010

100

FBA

AB

F


B.Supmonchai

D

A

B C

D

A

B

C

OUT = D + A • (B + C)

Complex CMOS Gate

Derive PUN hierarchicallyby identifying sub-nets




B.Supmonchai

Cell Design: An Introduction

q Standard Cells

ß A general purpose logic

ß Synthesizable

ß Same height but varying width

q Datapath Cells

ß For regular, structured designs (arithmetic)

ß Including some wiring in the cell

ß Fixed height and width


B.Supmonchai

Example of A Standard Cell

Cell boundary

N WellCell height 12 metal tracksMetal track is approx. 3l + 3l

Pitch = repetitive distance between objects

2l

Rails ~10l

InOut

VDD

GND

Cell height is “12 pitch”

Minimum-SizeInverter


B.Supmonchai

signals

Routing channel

VDD

GND

Standard Cell Layout Methodology – 1980s

Routing channel What logic function is this?


B.Supmonchai

M2

No Routingchannels

VDD

GNDM3

VDD

GND

Mirrored Cell

Mirrored Cell

Standard Cell Layout Methodology – 1990s




B.Supmonchai

Contains no dimensionsRepresents relative positions of transistors

Inverter

In

Out

VDD

GND

NAND2

A

Out

VDD

GNDB

Stick Diagrams


B.Supmonchai

OAI21 Logic Graph

C

A B

B

AC

i

j

j

VDDX

X

i

GND

AB

CPUN

PDN

ABC

X = C • (A + B)

Node of thecircuit

TransitionControl


B.Supmonchai

Two Stick Diagrams of C • (A + B)

A B C

X

VDD

GND

X

CA B

VDD

GND

Crossover can be eliminated by re-ordering inputs


B.Supmonchai

j

VDDX

X

i

GND

AB

C

A B C

q For a single poly strip for every input signal, the Eulerpaths in the PUN and PDN must be consistent (the same)

Consistent Euler Pathq An uninterrupted diffusion strip is possible only if there

exists an Euler path in the logic graph

Euler path: a path through allnodes in the graph such thateach edge is visited once andonly once.




B.Supmonchai

ABCD

C

A B

B

A

D

C

D

X = (A+B)•(C+D)VDDX

X

GND

AB

C

PUN

PDN

D

OAI22 Logic Graph


B.Supmonchai

BA D

VDD

GND

C

X

q Some functions have no consistent Euler path likex = !(a + bc + de) (but x = !(bc + a + de) does!)

OAI22 Layout


B.Supmonchai

A

B A ⊕ B

XNOR XOR

A

B

A ⊕ B A ⊕ BA

B

A

B A ⊕ B

q How many transistor in each?q Can you create the stick diagrams for the lower left circuit?

XNOR/XOR Implementation


B.Supmonchai

VGS2 = VA –VDS1

VGS1 = VB

M1

M2

M3 M4

A

B

F= A • B

A B

Cint

D

D

S

S 0

1

2

3

0 1 2

A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->1

0.5m/0.25m NMOS0.75m /0.25m PMOS

weakerPUN

VTC Characteristics are dependent upon the data input patternsapplied to the gate (so the noise margins are also data dependent!)

VTC is Data-Dependent




B.Supmonchai

Observation I

q The difference between the blue and the orangelines results from the state of internal node intbetween the two NMOS Devices.

q The threshold voltage of M2 is higher than M1due to the body effect (g),

ß VSB of M2 is not zero (when VB = 0) due to thepresence of Cint

VTn1 = VTn0 and VTn2 = VTn0 + g(÷(|2fF| + Vint) - ÷|2fF|)


B.Supmonchai

Review: CMOS Inverter - Dynamic

tpHL = f(Rn, CL)

tpHL = 0.69 Reqn CL

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.52 CL / (W/Ln k’n VDSATn )

VDD

Rn

Vout

Vin = V DD

CL

propagation delay is determined by the time tocharge and discharge the load capacitor CL


B.Supmonchai

Review: Designing for Performanceq Reduce CL

q Increase W/L ratio of the transistorß the most powerful and effective performance optimization tool

ß watch out for self-loading!

q Increase VDD

ß only minimal improvement in performance at the cost ofincreased energy dissipation

q Slope engineering - keeping signal rise and fall timessmaller than or equal to the gate propagation delays andof approximately equal valuesß good for performance and power consumption


B.Supmonchai

A

ReqA

CL

A

Rn

A

Rp

B

Rp

B

Rn Cint

NAND

Rp

A

A

Rn CL

INVERTER

Rp

Rp

Rn Rn CL

Cint

B

A

A B

NOR

Switch Delay Model




B.Supmonchai

Input Pattern Effects on Delayq Delay is dependent on the pattern of inputs

q Low to high transition

ß both inputs go low

ÿ delay is 0.69 Rp/2 CL since two p-resistors areon in parallel

ß one input goes low

ÿ delay is 0.69 Rp CL

q High to low transition

ß both inputs go high

ÿ delay is 0.69 2Rn CL

q Adding transistors in series (without sizing)slows down the circuit

CL

A

Rn

A

Rp

B

Rp

B

Rn Cint

NAND


B.Supmonchai

Delay Dependence on Input Patterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=1Æ0

A=1, B=1Æ0

A=1 Æ0, B=1

time [ps]

Vo

ltag

e [V

]

81A= 1Æ0, B=1

80A=1, B=1Æ0

45A=B=1Æ0

61A= 0Æ1, B=1

64A=1, B=0Æ1

67A=B=0Æ1

Delay

(psec)

Input Data

Pattern

NMOS = 0.5mm/0.25 mm, PMOS = 0.75mm/0.25 mm, CL = 100 fF


B.Supmonchai

Transistor Sizing Basic

q Inverter as a reference circuitDevice Transconductance (See Supplement 1)

kn = kn’(W/L)n = (µneox/tox)((W/L)n

kp = kp’(W/L)p = (µpeox/tox)((W/L)p

For rise time equal to fall time,

kp = kn (Rp = Rn)OutIn

VDD

(W/L)p

(W/L)n

CL

Because µp ~ µn /2

(W/L)p = 2 (W/L)n

The size of PMOS must be twice as large as that of NMOS

2

1


B.Supmonchai

Transistor Sizing: NAND and NOR

2

2

2 2

11

4

4CL

A

Rn

A

Rp

B

Rp

B

Rn Cint

NAND

Rp

Rp

Rn Rn CL

Cint

B

A

A B

NOR

Symmetric Response RPUN = RPDN

Rp µ 1/(W/L)p

Rn µ 1/(W/L)n

RPDN = Rn + Rn

RPUN = Rp + Rp




B.Supmonchai

Note on Transistor Sizingq By assuming RPUN = RPDN, we ignores the extra

diffusion capacitance introduced by wideningthe transistors.

q In DSM, even larger increases in the width areneeded due to velocity saturation.ß For 2-input NANDs, the NMOS transistors should

be made 2.5 times as wide.

q NAND implementation is clearly preferredover a NOR implementation, since a PMOSstack series is slower than an NMOS stack dueto lower carrier mobility


B.Supmonchai

1

2

2 2

4

48

8

Transistor Sizing: Complex CMOS Gate

D

A

B C

D

A

B

C

6

612

12

q Red sizing assuming RPUN = RPDN

ß Follow short path first; note PMOSfor C and B,4 rather than 3 (averagein pull-up chain of three =(4+4+2)/3)

ß Also note structure of pull-up andpull-down to minimize diffusioncap. at output (e.g., single PMOSdrain connected to output)

q Green for symmetric response andfor performance (where Rp = 3Rn)

ß Sizing rules of thumb: PMOS = 3* NMOS


B.Supmonchai

Fan-In Considerations

DCBA

D

C

B

A CL

C3

C2

C1

Distributed RC model(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function offan-in – quadratically in the worst case.


B.Supmonchai

Notes on Fan-In Considerationsq While output capacitance makes full swing transition from

VDD to 0, internal nodes only swing from VDD-VTn to GND

q C1, C2, and C3, each includes junction capacitance as wellas the gate-to-source and gate-to-drain capacitances(turned into capacitances to ground using the Miller effect)ß For W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS, values are on

the order of 0.85 fF

q CL = 3.47 fF with NO output load (all of diffusioncapacitance = intrinsic capacitance of the gate itself).

q tpHL = 85 ps (simulated as 86 ps).ß The simulated worst case low-to-high delay was 106 ps.




B.Supmonchai

tp as a Function of Fan-In

Gates with a fan-in greater than 4 should be avoided.

quadratic

linear

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

tpLH

t p (

pse

c)

fan-in

tpHL tp


B.Supmonchai

tp as a Function of Fan-OutAll gates have the same drive current.

0

200

400

600

800

1000

1200

2 4 6 8 10 12 14 16

tpNOR2

t p (

pse

c)

eff. fan-out

tpNAND2

tpINV

Slope is a function of “driving strength”


B.Supmonchai

tp as a Function of Fan-In and Fan-Out

q Fan-in: quadratic due to increasing resistanceand capacitance

q Fan-out: each additional fan-out gate adds twogate capacitances to CL

tp = a1FI + a2FI2 + a3FO

Parallel Chain Serial Chain


B.Supmonchai

Distributed RC line

M1 > M2 > M3 > … > MN

(the FET closest to the outputshould be the smallest)

Can reduce delay by morethan 20%; decreasing gainsas technology shrinks

Fast Complex Gates: Design Technique 1

q Transistor sizingß as long as fan-out capacitance dominates

q Progressive sizing

InN CL

C3

C2

C1In1

In2

In3

M1

M2

M3

MN




B.Supmonchai

Notes on Design Technique 1q With transistor sizing, if the load capacitance is dominated

by the intrinsic capacitance of the gate, widening the deviceonly creates a “self loading” effect and the propagationdelay is unaffected (and may even become worse).

q For progressive sizing, M1 have to carry the dischargecurrent from M2 (C1), M3 (C2), … MN and CL so make itthe largest.ß MN only has to discharge the current from MN (CL)(no internal

capacitances).

q While progressive sizing is easy in a schematic, in a reallayout it may not pay off due to design-rule considerationsthat force the designer to push the transistors apartß increasing internal capacitance.


B.Supmonchai

charged

charged

delay determined by timeto discharge CL, C1 and C2

delay determined by timeto discharge CL

discharged

discharged

Fast Complex Gates: Design Technique 2q Input re-orderingß when not all inputs arrive at the same time

CL

C2

C1In3

In2

In1

M1

M2

M3

critical path

1

1

0Æ1 chargedCL

C2

C1In1

In2

In3

M1

M2

M3

critical path

1

0Æ1

charged1

Place latest arriving signal (critical path)closest to the output can result in a speed up.


B.Supmonchai

Example: Sizing and Ordering Effects

DCBA

D

C

B

A CL = 100 fF

C3

C2

C1

3 3 3 3

4

4

4

4

4

5

6

7

Progressive sizing in pull-downchain gives up to a 23%improvement.

Input ordering saves 5% critical path A – 23% critical path D – 17%


B.Supmonchai

F = ABCDEFGH


q Alternative logic structuresß Reduced fan-in results in deeper logic depth

Reduction in fan-in offsets, by far, theextra delay incurred by the NOR gate.




B.Supmonchai

Notes on Design Technique 3

q Reducing fan-in increases logic depth of thecircuit

ß More stages but each stage has smaller delay

q Only simulation will tell which of the twoalternative configurations is faster and has lowerpower dissipation.


B.Supmonchai

CLCL


q Isolating fan-in from fan-out using bufferinsertionß Optimizing the propagation delay of a gate in isolation

is misguided.

Reduce CL on large fan-in gates, especially for large CL,and size the inverters progressively to handle the CLmore effectively


B.Supmonchai

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )


q Reducing the voltage swing

ÿ linear reduction in delayÿ also reduces power consumption

q But the following gate is much slower!

q Or requires the use of “sense amplifiers” on thereceiving end to restore the signal level (memorydesign)


B.Supmonchai

Sizing Logic Paths for Speed

q Frequently, input capacitance of a logic path isconstrained

q Logic also has to drive some capacitance

ß Example: ALU load in an Intel’s microprocessor is0.5pF

q How do we size the ALU data path to achievemaximum speed?

q We have already solved this for the inverter chain– can we generalize it for any type of logic?




B.Supmonchai

Inverter Chain: Recap

CL

In Out

1 2 N

1 f f N-1

For given N: Ci+1/Ci = Ci/Ci-1 = f = ÷(CL/Cin)N

q For optimum performance, we try to keep f ~ 4,which give us the number of stages, N.

q Can the same approach (logical effort) be usedfor any combinational circuit?


B.Supmonchai

Delay of a Complex Logic Gate

q For a complex gate, we expand the inverter chain equation

†

t p = t p 0 1+Cext

g ⋅ Cg

Ê

Ë Á Á

ˆ

¯ ˜ ˜ = tp 0 1+

fg

Ê

Ë Á

ˆ

¯ ˜

ß tp0 is the intrinsic delay of an inverter

ß f is the effective fan-out (Cext/Cg) - also called theelectrical effort

ß p is the ratio of the intrinsic (unloaded) delay of thecomplex gate and a simple inverter (a function of thegate topology and layout style)

ß g is the logical effort

†

t p = t p0 p +g ⋅ f

g

Ê

Ë Á

ˆ

¯ ˜


B.Supmonchai

Notes on Delay of a Logic Gate

Gate delay: D = h + p

Effort delay Intrinsic delay

Effort delay: h = g f

LogicalEffort

ElectricalEffort

(effective fan-out)

q Logical effort first defined by Sutherland andSproull in 1999.

q In a simpler format,

= Cout/Cin


B.Supmonchai

Intrinsic Delay Term, pq The more involved the structure of the complex

gate, the higher the intrinsic delay compared toan inverter

Ignoring second order effects such as internal node capacitances

n 2n-1XOR, XNOR

2nn-way mux

nn-input NOR

nn-input NAND

1Inverter

pGate Type




B.Supmonchai

Logical Effort Term, gq Logical effort of a gate, g, presents the ratio of its input

capacitance to the inverter capacitance when sized todeliver the same currentß g represents the fact that, for a given load, complex gates have

to work harder than an inverter to produce a similar (speed)response

2

(2n+1)/3

(n+2)/3

4

12

2

7/3

5/3

3

4

2

5/3

4/3

21

XOR

Mux

NOR

NAND

1Inverter

g (for 1 to 4 input gates)Gate Type


B.Supmonchai

Notes on Logical Effortq Inverter has the smallest logical effort and intrinsic delay

of all static CMOS gates

q Logical effort of a gate tells how much worse it is atproducing an output current than an inverter (how muchmore input capacitance a gate presents to deliver sameoutput current)

q Logical effort is a function of topology, independent ofsizingß Logical effort increases with the gate complexity

q Electrical effort (Effective fanout) is a function ofload/gate size


B.Supmonchai

A + B

A

B

A B

A

A

A

2

1

Cunit = 3

2 2

2

2

Cunit = 4

4

4

1 1

Cunit = 5

Example of Logical Effortq Assuming a PMOS/NMOS ratio of 2, the input

capacitance of a minimum-sized inverter is three timesthe gate capacitance of a minimum-sized NMOS (Cunit)

A • B

A

B

A B


B.Supmonchai

Delay as a Function of Fan-Out

q The slope of the line isthe logical effort of thegate

q The y-axis intercept isthe intrinsic delay

q Can adjust the delay byadjusting the effectivefan-out (by sizing) orby choosing a gate witha different logical effort

0

1

2

3

4

5

6

7

0 1 2 3 4 5n

orm

aliz

ed d

elay

fan-out f

NAND2: g=4/3, p

= 2

INV: g=1, p=1

intrinsic delay

effort delay

Gate Effort: h = fg




B.Supmonchai

1a b c

CL5

Path Delay: Complex Logic Gate Network

q Total path delay through a combinational logic block

tp = Â tp,j = tp0 Â(pj + (fj gj)/g )

q So, the minimum delay through the path determines thateach stage should bear the same gate effort

f1g1 = f2g2 = . . . = fNgN

q Consider optimizing the delay through the logic network

how do we determine a, b, and c sizes?


B.Supmonchai

Path Delay Equation Derivationq The path logical effort, G = ’ gi

q And the path effective fan-out (path electrical effort) isF = CL/g1

q The branching effort accounts for fan-out to othergates in the network

b = (Con-path + Coff-path)/Con-path

q The path branching effort is then B = ’ bi

q The total path effort is then H = GFB

q So, the minimum delay through the path isN

D = tp0 ( Âpj + (N ÷H)/ g)


B.Supmonchai

Example: Complex Logic Gates

q For gate i in the chain, its size is determined by

q For this networkß F = CL/Cg1 = 5

ß G = 1 x 5/3 x 5/3 x 1 = 25/9

ß B = 1 (no branching)

ß H = GFB = 125/9, so the optimal stage effort is ÷H = 1.93

ÿ Fan-out factors are f1=1.93, f2=1.93 x 3/5 = 1.16, f3 = 1.16, f4 = 1.93

ß So the gate sizes are a = f1g1/g2 = 1.16, b = f1f2g1/g3 = 1.34 andc = f1f2f3g1/g4 = 2.60

4

j=1

i -1

si = (g1 s1)/gi ’ (fj/bj)

1a b c

CL5


B.Supmonchai

Example – 8-input AND




B.Supmonchai

Summary: Method of Logical Effort

q Compute the path effort: F = GBH

q Find the best number of stages N ~ log4F

q Compute the stage effort f = F1/N

q Sketch the path with this number of stages

q Work either from either end, find sizes:

Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.


B.Supmonchai

Summary: Key Definitions

Sutherland,SproullHarris


B.Supmonchai

VDD

VSS

PDN

In1

In2

In3

F

RLLoad

ResistiveN transistors + Load

• VOH = VDD

• VOL = RPN

RPN + RL

• Assymetrical response

• Static power consumption

•

• tpL= 0.69 RLCL

Ratioed Logic

q N transistors + Load

q VOH = VDD

q VOL = RPDN / (RPDN + RL)

q Asymmetrical Response

q Static Powerconsumption Plow

q tpL = 0.69 RLCL

Goal: To Reduce the number of devices over complementary CMOS


B.Supmonchai

VDD

VSS

In1In2In3

F

VDD

VSS

PDNIn1In2In3

F

VSS

PDN

DepletionLoad

PMOSLoad

depletion load NMOS pseudo-NMOS

VT < 0

Ratioed Logic: Active Loads

VDD

VSS

In1In2In3

F

VDD

VSS

PDNIn1In2In3

F

VSS

PDN

DepletionLoad

PMOSLoad

depletion load NMOS pseudo-NMOS

VT < 0




B.Supmonchai

Pseudo NMOS NAND and NOR

D

C

B

A CL

F

NAND

DCBA CL

F

NOR

q Psedo-NMOS is useful when area ismost importantß Reduce transistor countsß Used occasionally for large fan-in gates


B.Supmonchai

†

kn VDD -VTn( )VOL -VOL

2

2Ê

Ë Á

ˆ

¯ ˜ + kp -VDD -VTp( ) ⋅VDSATp -

VDSATp2

2

Ê

Ë Á

ˆ

¯ ˜ = 0

†

VOL =kp VDD + VTp( ) ⋅ VDSATp

kn VDD -VTn( )ª

mnW p

mpWn

⋅ VDSATp

†

Plow = VDDIlow ª VDD ⋅ kp -VDD -VTp( ) ⋅VDSATp -VDSATp

2

2

Ê

Ë Á

ˆ

¯ ˜

Pseudo-NMOS Inverter Characteristics

q Assumptions:

ß NMOS resides in linear modeß VOL is small relative to the gate drive (VDD-VT))


B.Supmonchai

Pseudo-NMOS Inverter VTC

0.0 0.5 1.0 1.5 2.0 2.50.0

0.5

1.0

1.5

2.0

2.5

3.0

W/Lp = 4

W/Lp

= 2

W/Lp

= 1

W/Lp = 0.25

W/Lp = 0.5

Vou

t (V

)

Vin (V) 569410.0310.25

268800.0640.5

1231600.1331

562980.2732

145640.6934

tpLH

(ps)

Pstat

(µW)

VOL

(V)Size

NMOS size = 0.5 µm/0.25 µm

Larger pull-up device not only improves performance (delay)but also increases power dissipation and lowers noise marginsby increasing VOL


B.Supmonchai

q M1 >> M2

q The idea is to reducestatic power consump-tion by adjusting theloadß Load M2 when there are

not too many inputs(A, B, C, or D) active

ß Switch to Load M1when all inputs areactive (thus require highamount of current todrive)

Improved Loads: Adaptive Load

A B C D

F

CL

M1M2 M1 >> M2Enable

VDD

Adaptive Load

Enable




B.Supmonchai

Improved Loads: DCVSLVDD

VSS

PDN1

Out

VDD

VSS

PDN2

Out

AABB

M1 M2

Differential Cascode Voltage Switch Logic (DCVSL)


B.Supmonchai

B

A A

B B B

Out

Out

XOR-NXOR gate

DCVSL Example


B.Supmonchai

DCVSL Characteristics

q Dual Rail Logic

ß Each input is provided in complementary format and each gateproduces complementary output

ß Increasing complexity

q Rail-to-Rail Swing

q No static power dissipation

q Sizing of the PMOS relative to PDN is critical tofunctionality, not just performance

ß PDNs must be strong enough to bring outputs below VDD - |VTp|


B.Supmonchai

DCVSL Transient Response

0 0.2 0.4 0.6 0.8 1.0-0.5

0.5

1.5

2.5

Time [ns]

Vo l

tag e

[V] A B

A B

A,BA,B

Transient Response of a 2-input AND/NAND gate. How does it look like?

tin->out = 197 ps

tin->out = 321 ps




B.Supmonchai

A B

X YX = Y if A and B

X Y

A

B X = Y if A or B

NMOS Transistors in Series/Parallel

q Primary inputs drive both gate and source/drain terminals

q NMOS switch closes when the gate input is high

Remember - NMOS transistors pass a strong 0 but a weak 1


B.Supmonchai

PMOS Transistors in Series/Parallel

q Primary inputs drive both gate and source/drain terminals

q PMOS switch closes when the gate input is low

Remember - PMOS transistors pass a strong 1 but a weak 0

X = Y if A and B = A + B

X = Y if A or B = A • B

A B

X Y

X Y

A

B


B.Supmonchai

A

0

B

B F= A•B0.5/0.25

0.5/0.25

0.5/0.25

1.5/0.25

0

1

2

0 1 2

B = VDD, A = 0ÆVDD

A = VDD, B = 0ÆVDDA = B = 0ÆVDD

Vo

ut,

(V)

Vin, (V)

l Pure PT logic is not regenerative - the signalgradually degrades after passing through a numberof PTs (can fix with static CMOS inverter insertion)

VTC of PT AND Gate


B.Supmonchai

Complementary PT Logic (CPL)

B

AAB PT Network F

F

B

AAB

InversePT Network F

F

A

A

B F=A+B

B

BB

OR/NOR

F=A+B

A

A

B F=A·B

B

BB

AND/NAND

F=A·B

F=A⊕B

F=A⊕B

A

A

A

A

BB

XOR/XNOR




B.Supmonchai

CPL Propertiesq Differential, so complementary data inputs and outputs are

always available (don’t need extra inverters)

q Static, since the output defining nodes are always tied toVDD or GND through a low resistance path

q Design is modular; all gates use the same topology, onlythe inputs are permuted.

q Simple XOR makes it attractive for structures like adders

q Fast! (assuming number of transistors in series is small)

q Additional routing overhead for complementary signals

q Still have static power dissipation problems


B.Supmonchai

NMOS-Only PT Driving an Inverter

q Threshold voltage drop causes static power consumption(M2 may be weakly conducting forming a path fromVDD to GND)

q Notice VTn increases of pass transistor due to body effect(VSB)

Vx does not pull up to VDD, but VDD – VTn

VGS

In = VDD

A = VDDVx

M1

M2

B

SD Out


B.Supmonchai

Voltage Swing of PT Driving an Inverter

q Body effect – large VSB at X - when pulling high (B is tiedto GND and S charged up close to VDD)

q So the voltage drop is even worse

Vx = VDD - (VTn0 + g(÷(|2ff| + Vx) - ÷|2ff|))

0

1

2

3

0 0.5 1 1.5 2Time (ns)

Vo

ltag

e (V

)

In

Out

X = 1.8VIn = 0 Æ VDD

VDDX

Out0.5/0.25

0.5/0.25

1.5/0.25

D

S

B


B.Supmonchai

Cascaded NMOS-Only PTsB = VDD

Out

M1

yM2

A = VDD

C = VDD

x

G

SG

S

xM1

B = VDD

OutyM2

C = VDD

A = VDD= VDD - VTn1

Swing on y = VDD - VTn1 - VTn2 Swing on y = VDD - VTn1

q Pass transistor gates should never be cascaded as onthe left

q Logic on the right suffers from static powerdissipation and reduced noise margins




B.Supmonchai

M1

M2

A Mn

x

B

Out

Solution 1: Level Restorer

q For correct operation Mr

must be sized correctly(ratioed)

q Full swing on x (due toLevel Restorer) so no staticpower consumption byinverter

q No static backward currentpath through Level Restorerand PT since Restorer isonly active when A is high

LevelRestorer

Mr

0ÆVDD

0ÆVDD

B

ON0VDDVDD

OFFVDD00

MrOutXA


B.Supmonchai

Transient Level Restorer Circuit Response

0

1

2

3

0 100 200 300 400 500

Vo

ltag

e (V

)

Time (ps)

W/Lr=1.75/0.25

W/Lr=1.50/0.25

W/Lr=1.25/0.25W/Lr=1.0/0.25

node x never goes belowVM of inverter so outputnever switches

q Restorer has speed and power impacts:

ß Increases the capacitance at x, slowing down the gate

ß Increases tr (but decreases tf)

W/Ln=0.50/0.25, W/L1=0.50/0.25, W/L2=1.50/0.25


B.Supmonchai

Notes on Level Restorer

q Pull down must be stronger than restorer (pull up)to switch node X

q If resistance of restorer transistor is too small (toowide transistor) it is impossible to bring thevoltage at node X below the switching threshold ofthe inverter, and the inverter never switches!

q Sizing of Mr is critical for DC functionality, notjust performance!!

q It belongs to Dynamic Logic Family


B.Supmonchai

Solution 2: Multiple VT Transistorsq Technology solution: Use (near) zero VT devices for

the NMOS PTs to eliminate most of the threshold drop(body effect still in force preventing full swing to VDD)

Out

In2 = 0V

In1 = 2.5V

A = 2.5V

B = 0V

low VT

transistors

sneakpath

on

off butleaking

Watch out for subthresholdcurrent flowing through PTs




B.Supmonchai

Solution 3: Transmission Gates (TGs)

q Full swing bidirectional switch controlled by the gatesignal C, A = B if C = 1

A B

C

C

B

C = VDD

C = GND

A = VDD B

C = VDD

C = GND

A = GND

q Most widely used solution

A B

C

C


B.Supmonchai

Resistance of TG

0

5

10

15

20

25

30

0 1 2Vout (V)

Res

ista

nce

(k

W)

Rp

Rn

Req

Rp

Rn

2.5V

0V

2.5V Vout

W/Ln=0.50/0.25

W/Lp=0.50/0.25

q TG is not an ideal switch - series resistance

q Req is relatively constant ( about 8kohms in this case),so can assume has a constant resistance

Req = Rp || Rn


B.Supmonchai

S

S

S

In2

In1

F

F = !(In1 • S + In2 • S)GND

VDD

In1 In2S S

S S F

TG Multiplexer


B.Supmonchai

off

off

B

A A ⊕ B

Transmission Gate XOR

q F always has a connection to VDD or GND - not dynamic

q No voltage drop

6 Transistors




B.Supmonchai


B

A F = A‘

VDD (B)

0 (B’)

q When B = 1, the circuit behaves as if it is an inverter,hence F(B = 1) = A’

off

off

1


B.Supmonchai


q When B = 0, the circuit acts as a transmission gate,hence F(B = 0) = A (TG ensures no voltage drop)

B

A F = A

when A = 0weak 0

weak 1 when A = 1

VDD (B’)

0 (B)

on

on

0


B.Supmonchai


B

A A‘ B + A B’

q Combine the results using Shannon’s expansion theorem,

F = B·F(B = 1) + B’·F(B = 0) = A’B+AB’ = A ⊕ B


B.Supmonchai

TG Full Adder

Sum

Cout

A

B

Cin

• 16 Transistors, no more than 2 PTs in series• Full swing• Similar delay for Sum and Carry




B.Supmonchai

Delay of a TG Chain

C C C C

VN

V1 Vi Vi+1

5

0

5

0

5

0

5

0Vin

q Delay of the RC chain (N TG’s in series) is

tp(Vn) = 0.69 ÂkCReq = 0.69 CReq (N(N+1))/2 ª 0.35 CReqN2

Req Req Req ReqVin

C C C C

V1 Vi Vi+1VN


B.Supmonchai

Notes on TG Chain Delay

q Delay grows quadratically in N (in this case in thenumber of TGs in series) and increases rapidly with thenumber of switches in the chain.

q E.g., for 16 cascaded minimum-sized TG’s, each with anReq of 8kohms.

ß The node capacitance is the sum of the capacitances of twoNMOS and PMOS devices (junctions and drains).

ß Capacitance values is approx. 3.6 fF for low to high transitions.

q The delay through the chain is

ß tp = 0.69 CReq(N(N+1))/2 = 0.69 x 3.6fF x 8kΩ x (16x17)/2= 2.7ns


B.Supmonchai

q Delay of buffered chain (M TG’s between buffer)

tp = 0.69 ÎN/M CReq (M(M+1))/2˚ + (N/M - 1) tpbuf

Mopt = 1.7 ÷ (tpbuf/CReq ) ª 3 or 4

TG Delay Optimization

q Can speed it up by inserting buffers every M switches

Vin

VN

M

C5

0

5

0

5

0

C C5

0

5

0

5

0

C CC


B.Supmonchai

Notes on Delay Optimization

q Buffered chain is now linear in N

ß Quadratic in M but M should be small

q This buffer insertion technique works to speed up thedelay down long wires as well.

q Consider 16TG chain example. Buffers = inverters(making sure correct polarity is output).

ß For 0.5micron/0.25micron NMOSs and PMOSs in the TGs,

ÿ simulated delay with 2TG per buffer is 154 ps,

ÿ for 3TGs is 154ps, and for 4TG is 164ps.

ÿ The insertion of buffering inverters reduces the delay by afactor of almost 2.

nonratioed and ratioed logic static cmos circuits...ßpass-transistor ßnonratioed and ratioed logic...

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