lecture 13 - jon tselecture 13 logic families ii professor sunil bhave cu school of electrical and...
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Lecture 13Lecture 13
Logic Families II
Professor Sunil BhaveCU School of Electrical and Computer p
Engineering
March 17, 2010
RatioedLogic
Ratioed Logicg
VDD
RLLoad
VDD VDD
V
Resistive DepletionLoad
PMOSLoadVT < 0
PDNIn1In2I
FIn1In2I
F
PDNIn1In2I
FVSS
PDN
VSS
In3
VSS
In3
VSS
In3
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOSGoal: to reduce the number of devices over complementary CMOS
Ratioed LogicgVDD
N i L d
RLLoadResistive
N transistors + Load
• VOH = VDD
•
F
• VOL = RPN
RPN + RL
PDNIn1In2In3
• Assymetrical response
• Static power consumption
VSS
3 p p
• tpL= 0.69 RLCL
Active LoadsVDD VDD
VSS
DepletionLoad
PMOSLoadVT < 0
In1
F
In1
F
VSS
In2In3
PDNIn2In3
PDN
VSS VSS
depletion load NMOS pseudo-NMOS
Pseudo-NMOS
VDDDD
FCA B C D CL
VOH = VDD (similar to complementary CMOS)O p y
kn VDD VTn–( )VOLVOL
2
2-------------–
⎝ ⎠⎜ ⎟⎛ ⎞ kp
2------ VDD VTp–( )
2=
VOL VDD VT–( ) 1 1kpkn------–– (assuming that VT VTn VTp )= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
P d NMOS VTCPseudo-NMOS VTC
2.5
3.0
1 5
2.0
]
W/Lp = 4
1.0
1.5
Vou
t[V
]
W/Lp = 2
W/L = 1W/L = 0 5
0.0 0.5 1.0 1.5 2.0 2.50.0
0.5W/Lp = 1
W/Lp = 0.25
W/Lp 0.5
Vin [V]
Improved Loadsp
V
M1
VDD
F
M1M2 M1 >> M2Enable
A B C D
F
CL
Ad ti L dAdaptive Load
Improved Loads (2)p ( )VDD VDD
M1 M2
Out Out
APDN1 PDN2A
BB
VSS VSS
Differential Cascode Voltage Switch Logic (DCVSL)g g ( )
DCVSL Examplep
Out
B B B B
Out
B
A A
B B B
XOR-NXOR gate
DCVSL T i t RDCVSL Transient Response
2.5
1.5
ge[V
] A B
A B
0.5
Vol
tag A B
A,BA,B
0 0.2 0.4 0.6 0.8 1.0-0.5
Time [ns][ ]
Pass-Transistor Logicg
ts Switch OutOut
A
B
Inpu
t
NetworkOut
BB
• N transistors• N transistors• No static consumption
E l AND G tExample: AND Gate
BB
BA
F = AB
0
NMOS O l L iNMOS-Only Logic
In
3.0
In
VDDOut
x
0.5μm/0.25μm0 5μm/0 25μm
1.5μm/0.25μm 2.0
Volta
ge[V
]
xOut
0.5μm/0.25μm
0 0.5 1 1.5 20.0
1.0V
0 0.5 1 1.5 2Time [ns]
NMOS-only Switchy
A = 2.5 V
C = 2.5V
A = 2.5 V
C = 2.5 V
BM2
MnB
CL M1
Mn
VB does not pull up to 2.5V, but 2.5V -VTNThreshold voltage loss causes
static power consumption
B TN
NMOS has higher threshold than PMOS (body effect)
NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor
VDD
M
MrB
VDDVDDLevel Restorer
M2
Mn OutAX
M1
• Advantage: Full Swing• Restorer adds capacitance takes away pull down current at X Restorer adds capacitance, takes away pull down current at X• Ratio problem
Restorer SizingRestorer Sizing
3.0•Upper limit on restorer size•Pass-transistor pull-down
2.0
W/Lr =1.50/0.25
W/Lr =1.75/0.25
olta
ge[V
]
pcan have several transistors in stack
1.0
W/Lr =1.0/0.25 W/Lr =1.25/0.25
Vo
0 100 200 300 400 5000.0
Time [ps]
Solution 2: Single Transistor Pass Gate with V =0VT=0
VDD
VDD
0V
OutVDD
0V 2.5V
0V
2.5V
VDD 0V
WATCH OUT FOR LEAKAGE CURRENTSWATCH OUT FOR LEAKAGE CURRENTS
Complementary Pass Transistor Logicp y g
P T i tA
FPass-Transistor
NetworkABB
A Inverse
(a)
FPass-TransistorNetwork
ABB
Inverse
A
B B B B
A
B B
A
B
A
B
B
A
B
F=AB
F=AB
F=A+B
F=A+B
A
A
A
F=A⊕ΒÝ
F=A⊕ΒÝ
(b)
OR/NOR EXOR/NEXORAND/NAND
Solution 3: Transmission Gate
CC
A B A B
CC
BA = 2.5 V
C = 2.5 V
CL
C = 0 V