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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic 1
Digital Microelectronic
Circuits
(361-1-3021 )
Ratioed Logic
Presented by: Mr. Adam Teman
Lecture 8:
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Motivation
In the previous lecture, we learned about
Standard CMOS Digital Logic design.
CMOS is unquestionably the leading design family in use
today, do to its many advantages and relative simplicity.
However, it has a number of drawbacks that have led to the
development of alternative solutions.
The main drawback of Standard CMOS is its relatively large
area (2N transistors to implement an N-input gate).
In this lecture, we will start to overview a number of
alternative logic families that try to reduce the number of
transistors needed to implement a logic function.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
What will we learn today?
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8.1 Ratioed Logic
8.2 Pseudo NMOS
8.3 LE of Pseudo NMOS
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
RATIOED LOGIC
Let’s start with an important
concept that has driven a number
of logic families:
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8.18.1 Ratioed Logic
8.2 Pseudo NMOS
8.3 LE of Pseudo NMOS
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Ratioed Logic Concept
When we discussed Standard CMOS during the previous
two lectures, we spent quite a while analyzing the
sizes of the transistors.
It is important to note that these sizing considerations
improved the performance (=speed) of the logic gates,
but not their functionality.
In other words, even if we implemented the gates
without size considerations, we would arrive at the
requested logic function (though it might take a while…).
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Ratioed Logic Concept
Ratioed Logic is an attempt to reduce the number of
transistors required to implement a given logic function,
waiving the assurance of functionality.
As its name implies, in order to ensure functionality, a
certain ratio of sizes has to be kept between various devices
that make up the gate.
Ratioed Logic has another great disadvantage – high static
power dissipation – which makes it vary scarcely used. But
the concept is implemented in quite a few complex circuits
(such as memory circuits), and so it is important to
understand.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Ratioed Logic Concept
The concept of Ratioed Logic uses the same Pull Down Network
as CMOS, but uses a simple Load as its Pull Up Network.
This Load constantly leaks current from the supply to the output
capacitance. In this way, the output is charged when the PDN is
closed, providing a ‘1’.
On the other hand, the Load’s resistance
is much larger than that of an open PDN,
so when the PDN is open, the output is
pulled down to VOL.
The ratio between the resistance of the
Load and the PDN is crucial in designing
such a gate, hence it is called
“Ratioed” Logic.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
VTC of Generic Ratioed Logic Gate
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Ratioed Logic Characteristics
N transistors + Load
Asymmetrical Response
Static Power Consumption
Slow pull up:
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VDD
VSS
PDN
In1
In2
In3
F
RLLoad
ResistiveN transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
OH DDV V
PDNOL
PDN L
RV
R R
0.69pLH out Lt C R
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Load Implementation
Early Ratioed Logic designs used a simple
resistor as the Load.
This approach had several drawbacks,
especially with the difficulty in resistor
implementation in VLSI.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Load Implementation
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Accordingly, the Load was replaced with a
Diode-connected nMOS (VGD=0) a.k.a.
Saturated Load Inverter.
This circuit stopped conducting at
VGS=VDD-VTn (weak ‘1’) providing a largely
reduced swing.
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Load Implementation
To improve the swing, the nMOS (also
known as an “enhancement mode” nMOS)
was replaced with a “Depletion Mode” nMOS.
This is a special, highly doped nMOS
with a negative threshold voltage (VTn<0).
This was used for some time until the
Pseudo nMOS inverter was invented,
replacing the nMOS load with a pMOS connected to ground.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
PSEUDO NMOSThe only really surviving ratioed logic family is:
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8.28.1 Ratioed Logic
8.2 Pseudo NMOS
8.3 LE of Pseudo NMOS
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS
The topology of a Pseudo nMOS gate
is shown in the following figure:
The clear advantage of this gate over Standard CMOS is the
reduced number of transistors:
» N+1 transistors to implement an N-input gate.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS
Using a pMOS in the PUN, we get a
Strong ‘1’ when the PDN is closed,
so VOHmax=VDD.
On the other hand, when the PDN is
open, there is a “fight” between the
PDN and the pMOS load.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS
To calculate VOLmin, we will equate the pMOS saturation
current with the PDN current, assuming that it consists of
nMOS devices in Linear Mode.
We will mark the drive strength of the PDN as kneq and
assume short channel devices*:
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2
21
2 2
DSATDp p DD Tp DSAT Dn neq DD Tn OL OL
VI k V V V I k V V V V
*Calculate for long channel devices at home!
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS
Making a few minor assumptions, we arrive at:
So to get a Low VOLmin, we need the
pMOS to be much smaller than the
equivalent width of the nMOS
network.
Making the pMOS small means
a small charge current, resulting
in a large tpLH!
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p DD Tp DSAT p p
OL DSAT
neq DD Tn n neq
k V V V WV V
k V V W
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS
In addition, we get static power dissipation from the direct
path between VDD and GND when outputting a ‘0’:
Accordingly, Pseudo nMOS won’t usually be used
in low power or high frequency applications.
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2
2
DSATlow DD low DD p DD Tp DSAT
VP V I V k V V V
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS
However, when large fan-in
gates are needed, the
reduced transistor count
can be attractive.
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
VTC of Pseudo NMOS
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo NMOS Characteristics Summary
Small β ratio (small pMOS, big PDN):
» Lower VOL
» Better Gain
» Less static power
» Fast tpHL
But…
» Slow tpLH
» Bigger capacitive load
In general:
» N+1 Transistors
» Only 1 NMOS load to previous stage
» Make sure RPMOS resistance at least 4 x RPDN
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
LOGICAL EFFORT OF PSEUDO NMOS
Now we can compare this logic family using our previously
developed design methodology:
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8.38.1 Ratioed Logic
8.2 Pseudo NMOS
8.3 LE of Pseudo NMOS
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo-NMOS – Rising Edge
tpLH is simply through the pMOS:
Let’s look at the Logical Effort parameters of this transition:
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Wmin
βWminA
Wmin
C1
,mineq pR R
,min0.69pLH L pt C R
minG n gC C
min1d n dC C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Rising Edge Logical Effort
Now it is straightforward to
calculate the LE parameters.
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Wmin
C1
,min
min
min1
eq p
G n g
d n d
R R
C C
C C
,min min
,min min
1 21
2 3 3
p n d
n
p d
R Cp
R C
4 2for =1: 3 3n p LE
,
,min
,
,min
gate d gate
inv d
gate g gate
inv g
R Cp
R C
R CLE
R C
,min min
,min min
2
2 3 3
p n dn
p d
R CLE
R C
10 8for =4: 3 3n p LE
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo-NMOS – Falling Edge
But what about tpHL?
» Let’s find the Thevenin Equivalent:
» So we would expect:
» But the swing is VDD/2, not VThevenin/2
» So it actually takes a bit longer to discharge.
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0.69pHL L Thevenint C R
NThevenin DD
N P
RV V
R R
N P
Thevenin
N P
R RR
R R
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Response on Falling edge
The smaller RPUN:
» The smaller the swing, so it takes less time to reach 0.5(VOH-VOL)
» But the longer it takes to reach 0.5VDD !
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Falling Edge Logical Effort
tpHL presents a new problem:
» Both the PUN and PDN are conducting.
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thevenin n pR R R
C1
IPUN
IPDN
IPDN-IPUN So Req is smaller than Rn?
How could this be – the pmos is
“fighting” the discharge…
It’s because of the swing…
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS Logical Effort
What is the actual R?
» Available Current is the difference between PDN and PUN.
» The current is approximately proportional to the resistance.
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DD DD DD
eq PDN PUN
V V VR R R
C1
IPUN
IPDN
IPDN-IPUN
So Req is bigger than Rn?
That makes more sense…
,min
,min ,min
1 1 1
12
n
eqneq p n
n
RR
RR R
,minfor =1: 2n eq nR R
,min ,min
for =4:
3.5
n
n neq
n
R RR
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS Logical Effort
So the parameters for pull down:
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min
min
min
12
1
neq
n
G n g
d n d
RR
C C
C C
,minmin
min ,min
1 11
0.5 3 3 0.5
n dn n
n n d n
CRp
R C
4 2for =1: 3 3n p LE
C1
IPUN
IPDN
IPDN-IPUN
,
,min
,
,min
gate d gate
inv d
gate g gate
inv g
R Cp
R C
R CLE
R C
,minmin
min ,min0.5 3 3 0.5
n gn n
n n g n
CRLE
R C
10 8for =4: 21 21n p LE
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Pseudo nMOS Logical Effort - Summary
So to summarize:
» With β=1 (high VOL), we got:
» Our LE is LOWER than an inverter!
» But don’t forget we have depleted noise margins and we
have static power…
» With β=4 (more realistic), we got:
» Our HL transition has much better performance than
CMOS!
» But the LH transition is much worse.
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4 2 4 2: :3 3 3 3pLH pHLt p LE t p LE
10 8 10 8: :3 3 21 21pLH pHLt p LE t p LE
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Last Lecture
Pseudo NMOS
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Last Lecture
Rising Edge (easy):
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Last Lecture
Falling Edge (“complicated”):
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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8: Ratioed Logic
Another Example
What if we were to give the pMOS a long L?
» Say we want β=4, so we would choose Wp/Lp=Wmin/4Lmin
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C1
IPUN
IPDN
IPDN-IPUN
ming gC C2 116 8: 8 8
3 33 3LH LHLH p LE
min
min4
W
L
min
min
W
L
8 2 8 116 8:21 217 3 7 3
HL HLHL p LE
min2d dC C
4 8eqLH P eqR R R
74 8
pHL n eq
II I I
817eqHL eq
eq
R RI