Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing

Bo Fu and Paul Ampadu Electrical and Computer Engineering

University of Rochester Rochester, NY 14627, USA

<bofu, ampadu>@ece.rochester.edu

Abstract—A leakage power minimization method in nanoscale CMOS circuits by transistor sizing in non-critical paths is presented. It is shown that a small increase in delay by transistor downsizing of non-critical paths can provide a significant reduction in leakage power. Moreover, nonlinear dependence of leakage current on width (due to inverse narrow width effects) can be exploited to minimize leakage power at non-minimum widths. A 64-bit carry-lookahead adder, with carry blocks optimized for speed and sum blocks minimized for leakage power, achieves a reduction in leakage power by about 25%.

I. INTRODUCTION Leakage power is a significant portion of total power

dissipation in nanoscale CMOS circuits [1], and a variety of techniques for leakage power reduction have been investigated [2]-[4]. Input vector control reduces leakage power by using stack effects of serially connected devices [2], and multiple threshold voltage techniques, using low threshold and high threshold devices in the critical and non-critical paths respectively, reduce leakage power without sacrificing performance [3]. Power supply gating shuts down the power supply to reduce leakage power of idle units. This can be implemented by inserting “sleep transistors” in the power supply path [4].

Transistor sizing is another approach to reduce leakage power. Gate-length biasing was proposed to reduce leakage power because of the exponential increase of the threshold voltage with a small increase in transistor length [5]. Transistor sizing combined with the dual threshold voltage technique has been used for fine grain leakage current control [6]. A nonlinear dependence of leakage current on width due to inverse narrow width effects can lead to minimum leakage current at non-minimum widths [7].

In this paper, a leakage power minimization method by sizing transistors in non-critical paths is proposed. Section II evaluates the impact of transistor sizing on leakage current when threshold voltage modulation is considered. In Section III, leakage power reduction using transistor sizing for a variety of logic gates are examined. Simulations of a 64-bit carry-lookahead adder using the proposed sizing scheme for minimizing critical path delay and non-critical path leakage power are presented in Section IV. Conclusions are presented in Section V.

II. SIZING FOR MINIMUM LEAKAGE CURRENT There are basically four types of leakage current in a

MOS transistor—reverse-biased junction leakage, gate-induced drain leakage, gate direct-tunneling leakage, and subthreshold leakage [8]. Subthreshold leakage is the drain-source current of a transistor operating in the weak inversion region and constitutes the main component of leakage current [8].

The subthreshold drain current is given by [9]

)1(exp1exp)/( 2DS

th

DS

th

TGSthoxD V

VV

sVVVVLWCI λημ +⎥

⎦

⎤⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛−−⎟⎟

⎠

⎞⎜⎜⎝

⎛ −=

(1)

whereschsi Nq φξη 2/ = , Vth = kT/q is thermal voltage, λ

is the channel length modulation factor, VGS is gate-to-source voltage and µ, Cox, W, L, s, k, T, and q are carrier surface mobility, gate oxide capacitance per unit area, effective width and length of the device, subthreshold slope factor, Boltzman constant, temperature, and electron charge, respectively.

Leakage current is not exactly proportional to width as might be concluded from (1). In nanoscale CMOS, threshold voltage modulation due to narrow width effects leads to a nonlinear dependence of leakage current on width. Raised field oxide and semi-recessed local oxidation isolation (LOCOS) structures can result in threshold voltage that increases with decreasing width [7]. Fully recessed local oxidation and shallow trench isolation (STI) structures can lead to a decrease in threshold voltage with decreasing width [7].

If the inverse narrow width effect is observed in a technology employing STI, minimum leakage current is attained at a width given by [10]

2

2

min24

oxth

oxthBBoxthBSTI_leak CsV

CsVQQCsVQCW

−+−= (2)

where QB is body charge and CSTI is the shallow trench isolation capacitance [7].

Fig. 1 shows the threshold voltage and leakage current of NMOS and PMOS transistors in a 90 nm CMOS STI technology.

1-4244-0395-2/06/$20.00 ©2006 IEEE. 1101

Fig. 1(a) shows that the threshold voltage of NMOS transistors increases with transistor width W for this technology, and in the region from W=0.12 μm to W=0.21 μm, threshold voltage increases significantly for a small increase in width. A minimum leakage current is observed at Wmin, current=0.21 μm, and leakage current at Wmin, current is about 25% less than the leakage current at minimum width, as shown in Fig. 1(a). Fig. 1(b) shows that the magnitude of threshold voltage of a PMOS transistor in this technology decreases with increasing transistor width, which leads to a fast leakage current increase at large PMOS transistor widths.

Leakage current depends on circuit topology as well. Stacked devices have proven to be effective in reducing subthreshold leakage current [11]. Fig. 2 shows the leakage current of a stack of two equal sized NMOS transistors and that of a single NMOS transistor. The leakage current of the stacked device decreases by about 90% compared to that of a single NMOS transistor. The ratio of leakage current for these two cases is almost constant as transistor width is varied, and minimum leakage current of the two-transistor stack occurs not at minimum width but at the same width Wmin,current as for the single transistor. Sizing NMOS transistors in a stack to Wmin,current can reduce the leakage current by about 25% compared to that at minimum width.

III. SIZING LOGIC GATES FOR LEAKAGE POWER REDUCTION In this section, effects of transistor sizing on leakage

power and delay for basic CMOS gates are examined. A method for minimizing leakage power in non-critical paths by downsizing transistors is presented.

A. Sizing a Static Inverter for Minimum Leakage Power Fig. 3 shows the average leakage power of a static

CMOS inverter loaded by three equally-sized inverters. The inverter under test is first optimized for minimum delay, which is the average value of high-to-low and low-to-high delay. Then the NMOS transistor and the PMOS transistor widths are varied separately to evaluate the effect of transistor sizing on leakage power and delay. Fig. 3 (a) shows that both leakage power and delay of the inverter increase rapidly for NMOS transistor widths smaller than Wmin,current (the shaded region in Fig. 3 (a)). The leakage power is lower by about 15% and delay is higher by about 34% for NMOS widths close to Wmin,current compared to when the NMOS transistor is sized for minimum delay. Fig. 3 (b) shows that minimum leakage power of an inverter as PMOS transistor width is varied occurs at minimum PMOS transistor width. The leakage power decreases by about 75% and delay increases by about 2.5 times for the PMOS transistor sized to minimum width compared to that at minimum delay. Downsizing the PMOS transistor achieves a larger leakage power reduction than downsizing the NMOS transistor, due to different effects of threshold voltage modulation on PMOS and NMOS transistors for the technology examined.

Fig. 3(c) compares the effects of PMOS and NMOS transistor sizing on delay and leakage power. When delay increases by about 10%, the leakage power reduction due to the downsized PMOS transistor is about 55%, while the leakage power reduction due to the downsized NMOS transistor is 14%. When delay increases by 20%, the leakage power reduction due to decreased PMOS and NMOS transistor widths is 64% and 16%, respectively. A small increase in delay by downsizing the PMOS transistor provides a significant reduction in leakage power.

Figure 2. Leakage current of a two-transistor NMOS stack.

(a) (b)

(c)

Figure 3. Delay and leakage power of a static CMOS inverter.

(a) (b)

Figure 1. Threshold voltage and leakage current of (a) NMOS and (b) PMOS transistor.

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B. Sizing NAND and NOR gates A comparison of the leakage power of different basic

gates in deep submicron technologies without consideration of delay constraints is presented in [12]. In this section, the effect of transistor sizing on the leakage power of basic static CMOS gates is examined with two sizing schemes—sizing for minimum leakage power and sizing for minimum delay. For minimum leakage power sizing, NMOS and PMOS transistors are set to Wmin, current = 0.21 μm and minimum width (0.12 μm), respectively. The leakage power considered here is the average value over all possible input combinations, not the worst case leakage power.

Fig. 4 (a) shows that total leakage power is dominated by NMOS transistors when transistors are sized to minimize leakage power. When transistors are sized to minimize delay, the relative contribution of PMOS and NMOS transistors to total leakage power depends on technology details, gate type, fan-in, and input vector. For the 90 nm technology employed in the simulations presented in Fig. 4 (b), the leakage current of PMOS transistors is larger than that of NMOS transistors for devices larger than about 1 μm. Therefore in this technology, NAND-style gates consume less leakage power than NOR-style gates, because NOR-type gates have stacked PMOS devices at least one of which is off for all but one input vector. Fig. 4 (b) also shows that high fan-in gates have smaller leakage power than small fan-in gates.

Fig. 5 shows the leakage power of a 2-input static CMOS NAND gate for all possible input vectors. When the gate is optimized for leakage power, minimum leakage power occurs at input vector “11” as shown in Fig. 5 (a). When the gate is optimized for delay, minimum leakage power occurs at input vector “00” instead, as can be seen in Fig. 5 (b). This shows that leakage power reduction by input vector control techniques requires detailed consideration of transistor sizing effects.

Fig. 6 shows the effect of transistor downsizing on delay and leakage power for basic static CMOS gates. For each gate, a region exists for which a small increase in delay by transistor downsizing leads to a significant decrease in leakage power. The figure also shows that for the same delay increase near this region, NOR-style gates of a given fan-in achieve larger leakage power reduction than NAND-style gates with the same fan-in.

C. Leakage Reduction via Non-critical Path Transistor Sizing

A sizing algorithm for non-critical path transistors is motivated by observations that a significant reduction in leakage power can be obtained for a small increase in delay, and small fan-in gates can achieve larger leakage power reduction than high fan-in gates when transistors are downsized to minimize leakage power. This method may reduce the total leakage power without sacrificing system throughput. The algorithm is presented as follows: 1) Optimize the circuit for delay. After timing analysis, partition the circuit into critical and non-critical paths. Keep critical paths delay-optimized.

2) For each logic gate in a non-critical path

a) If gates are in a low-leakage state, skip them. b) Otherwise, put the gate in a priority queue. The gate

achieving larger leakage power reduction for the same delay increase gets higher priority. i) Small fan-in gates get priority than large fan-in gates. ii) When NAND and NOR gates with the same fan-in

are queued, NOR gates should be given priority. c) Repeat a) and b) until the end of this path.

3) Pop the highest-priority gate from the queue and downsize this gate to the region where deceasing leakage power further leads to a significant increase in delay. If there is sufficient slack to permit this delay increase, continue to downsize other gates. Otherwise end leakage minimization in this non-critical path.

4) Repeat 2) and 3) until leakage power of all the non-critical paths is minimized.

Figure 6. Leakage power vs. delay curves.

(a) (b)

Figure 4. Leakage power of static CMOS gates sized for (a) minimum leakage and (b) minimum delay.

(a) (b)

Figure 5. Leakage power of a NAND2 static CMOS gate sized for (a) minimum leakage and (b) minimum delay.

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IV. EXPERIMENTS AND RESULTS

A. Simulation Environment Simulations were performed in the Cadence design

environment using Spectre and a 90 nm CMOS technology with a 1 V supply voltage. The output of the test unit is loaded with three static inverters.

B. Application to a 64-bit carry-lookahead adder A 64-bit carry-lookahead adder is implemented to

demonstrate the proposed leakage power minimization by sizing transistors in non-critical paths. The adder is first sized for optimum delay. The critical path, from propagate and generate signals to the most significant sum bit, as shown by the dotted line shown in Fig. 7, is kept unchanged. The non-critical paths, comprising other carry and sum blocks, are downsized to reduce the leakage power using the algorithm presented in section III (c).

The worst-case delay of the adder is 1.2 ns. The delay of the sum block, composed of static CMOS XOR, is 80 ps when transistors are sized using the proposed algorithm. Thus, sizing non-critical paths for minimum leakage power does not change the critical path.

Fig. 8 shows the leakage power for the two sizing strategies. The leakage power shown is the average value of the all-‘0’ and all-‘1’ input cases. Fig. 8 shows that sizing non-critical paths for minimum leakage power reduces the leakage power of non-critical paths by about 52%, leading to a reduction of total leakage power by about 25% compared to sizing for minimum delay.

V. CONCLUSION The effect of transistor sizing on leakage power, when

threshold voltage modulation is considered, was evaluated. For a given technology, threshold voltage modulation may have different effects on PMOS and NMOS transistors. In the STI technology examined, NMOS threshold voltage increases with transistor width, and the magnitude of PMOS threshold voltage decreases with transistor width. PMOS transistors dominate the total leakage power for basic static CMOS gates when transistors are optimized for delay. Minimum leakage current for a NMOS transistor does not occur at minimum width due to the inverse

narrow width effect.

Leakage power and delay curves of basic CMOS gates due to transistor sizing show a distinctive region for which a small increase in delay leads to a significant reduction in leakage power. Sizing transistors in non-critical paths to these regions may reduce leakage power without sacrificing system throughput. A 64-bit carry-lookahead adder is implemented using the proposed method to size non-critical paths. The simulation result shows that the proposed method can reduce total leakage power by 25% without sacrificing throughput.

VI. REFERENCES [1] W. M. Elgharbawy and M. A. Bayoumi, “Leakage sources and

possible solutions in nanometer CMOS technologies,” IEEE Circuits Syst. Mag., vol. 5, pp. 6–17, fourth quarter 2005.

[2] L. Yuan and G. Qu, “A combined gate replacement and input vector control approach for leakage current reduction,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, pp. 173–182, Feb. 2006.

[3] J. T. Kao and A. P. Chandrakasan, “Dual-threshold voltage techniques for low-power digital circuits,” IEEE J. Solid-State Circuits, vol. 35, pp. 1009–1018, Jul. 2000.

[4] V. Kursun and E. G. Friedman, “Sleep switch dual threshold voltage domino logic with reduced standby leakage current,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, pp. 485–496, May 2004.

[5] A. B. Kahng, S. Muddu, and P. Sharma, “Impact of gate-length biasing on threshold-voltage selection,” in Proc. ISQED’06, pp. 747–754.

[6] S. Augsburger and B. Nikolic, “Combining dual-supply, dualthreshold and transistor sizing for power reduction,” in Proc. ICCD’02, pp. 316–321.

[7] C. Pacha., et al. “Impact of STI-induced stress, inverse narrow width effect, and statistical VTH variations on leakage currents in 120 nm CMOS,” in Proc. ESSDERC’04, pp. 397– 400.

[8] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep submicrometer CMOS circuits,” in Proc. IEEE, vol. 91, pp. 305–327, Feb. 2003.

[9] Cheng, Y. C. et al. BSIM3v3 Manual. [Online]. Available: http://www-device.eecs.berkeley.edu/~bsim3/.

[10] B. Fu, Q. Yu, and P. Ampadu, “Energy-delay minimization in nanoscale domino logic,” in Proc. GLSVLSI’06, pp. 316–319.

[11] S. Narendra, et al., “Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-um CMOS,” IEEE J. Solid-State Circuits, vol 39, pp. 501–510, Mar. 2004.

[12] G. Merrett and B. M. Al-Hashimi, “Leakage power analysis and comparison of deep submicron logic gates,” in Proc. PATMOS’04, pp. 198-207.

Figure 8. Comparison of two sizing strategies for non-critical paths of

a 64-bit carry-lookahead adder. Figure 7. A 64-bit carry-lookahead adder.

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