nanoscale device modelling: cmos and beyond

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G. Iannaccone Università di Pisa G. Iannaccone Università di Pisa and IU.NET [Italian Universities Nanoelectronics Consortium] Via Caruso 16, I-56122, Pisa, Italy. [email protected] Nanoscale Device Nanoscale Device Modelling: Modelling: CMOS and beyond CMOS and beyond

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Nanoscale Device Modelling: CMOS and beyond. G. Iannaccone Università di Pisa and IU.NET [Italian Universities Nanoelectronics Consortium] Via Caruso 16, I-56122, Pisa, Italy. [email protected]. Acknowledgments. People that did (are doing) the “real” work - PowerPoint PPT Presentation

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Page 1: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

G. IannacconeUniversità di Pisa

and IU.NET [Italian Universities Nanoelectronics Consortium]

Via Caruso 16, I-56122, Pisa, Italy. [email protected]

Nanoscale Device Nanoscale Device Modelling:Modelling:

CMOS and beyondCMOS and beyond

Page 2: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

AcknowledgmentsAcknowledgments

People that did (are doing) the “real” work A. Campera, P. Coli, G. Curatola, G. Fiori, F. Crupi,

G. Mugnaini, A. Nannipieri, F. Nardi, M. Pala, L. Perniola Partners

IMEC, LETI, STM, Silvaco (EU FinFlash Project) Univ. Wuerzburg, ETH Zurich, TU Vienna, MPG Stuttgart,

NMRC Cork (EU NanoTCAD Project) EU Sinano NoE (43 partners) Next: PullNANO IP IU.NET Italian Universities Nanoelectronics Corsortium Univ. Bologna, Univ. Udine, Univ. Roma (PRIN

Programme) Philips Research Leuven, Purdue University, Univ.

Illinois at Urbana Champaign, Samsung Funding (past and present)

European Commission, Italian Ministry of University, Italian National Research Council, Foundation of Pisa Savings Bank, Silvaco International

Page 3: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

The ProblemThe Problem

“Yesterday’s technology modeled tomorrow”

(M.E.Law, 2004)

TCAD and numerical modeling tools – both for process and device simulation – are accurate, or “predictive”, only for a sufficiently stable and “mature” technology, and after a lengthy calibration procedure.

Page 4: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Modeling as a Strategic ActivityModeling as a Strategic Activity

Modeling is a strategic activity because it enables to

perform an early evaluation of technology options

make choices and cut unpromising initiatives

strategically position and focus R&D efforts

Modeling supports the definition and the

implementation of a R&D strategy

Page 5: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Emerging Research Devices

Nanocrystal and discrete trap flash memories

Quantum dots and single electron transistors

CNT-FETs Resonant Tunneling

Devices

Fundamentals of Nanoelectronics

Decoherence and dephasing

Spin-dependent transport Mesoscopic transport

ITRS Roadmap Issues Quantum ballistic and

quasiballistic modeling of nanoscale MOSFETs (2D-3D)

Alternative device structures (DG MOSFETs, FINFETs, SNWTs)

Tunneling currents through oxides and high-k gate stacks, also in the presence of defects (SILCs, etc.)

Atomistic effects in nanoscale MOSFETs

Compact modeling of nanoscale MOSFETs

Present activity in PisaPresent activity in Pisa

Page 6: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

ITRS Roadmap Issues Quantum ballistic and

quasiballistic modeling of nanoscale MOSFETs (2D-3D)

Alternative device structures (DG MOSFETs, FINFETs, SNWTs)

Tunneling currents through oxides and high-k gate stacks, also in the presence of defects (SILCs, etc.)

Atomistic effects in nanoscale MOSFETs

Compact modeling of nanoscale MOSFETs

Present activity in PisaPresent activity in Pisa

Emerging Research Devices

Nanocrystal and discrete trap flash memories

Quantum dots and single electron transistors

CNT-FETs Resonant Tunneling

Devices

Fundamentals of Nanoelectronics

Decoherence and dephasing

Spin-dependent transport Mesoscopic transport

Page 7: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

NanoTCAD3DNanoTCAD3D

3D Non linear Poisson

1D Schrödinger per slice

Ballistic Transport

DD per each 2D subband

3D Schrödinger

The many body Schrödinger equation is solved with DFT-LDA, effective mass approximation

The Kohn-Sham equation for electrons is solved for each pair of minima in the conduction band (three times)

The Kohn-Sham equation for holes is solved for heavy and light holes

+2D Schrödinger per

section

Ballistic Transport

DD per each 1D subband

+

Page 8: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

1Dx

z

y

2D

3D

NanoTCAD3DNanoTCAD3D

Depending on device architecture, multiple regions different types of confinement may be considered: Planar MOSFET: 1D vertical confinement Nanowire: 2D confinement in the transversal cross section Dots: 3D

Many body Schrödinger equation solved with DFT-LDA, effective mass approximation

Page 9: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Quantum ballistic and Quantum ballistic and quasiballistic modeling of quasiballistic modeling of nanoscale MOSFETs (3D)nanoscale MOSFETs (3D)

Lead: G. Fiori

Page 10: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Candidate device structures for MOSFETs with channel length of order 10 nm – Suppressed SCE

Silicon Nanowire Transistors (SNWT)Silicon Nanowire Transistors (SNWT)

Page 11: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

x

nqD

x

EnqJ i

i

Dn

iDnni

11

The 3D electron density is obtained as :

Transport models in the 1D Transport models in the 1D subbandssubbands

Two models for current1. Ballistic transport in each subband (including

tunneling)2. Drift-Diffusion transport in each 1D subband (Ei).

(note: The mobility model must be improved).1D subband profiles

2nd

3rd

4th

1st

n3D i

2n1Dii

Page 12: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

SNWT simulated structures : same transversal cross-section (5x5 nm, 1.5 nm

oxide) different channel lengths (L=7,10,15,25 nm)

Simulation of SNWT (I)Simulation of SNWT (I)

Page 13: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Simulation of SNWT (II)Simulation of SNWT (II)

Electrostatic potential in a y-z cross section in the middle of the channel :

Vds = 0.5 V ; Vgs = 0.5 V

Electron Density Isosurface n=1.4x1019cm-3; L=15 nm; Vgs=0.5 V; Vds=0.5V

source

draingate

Page 14: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Simulation of SNWT (III)Simulation of SNWT (III)

S degrades for small L but is still acceptable and almost insensitive to the transport mechanism

DIBL is much higher for ballistic than for DD transport.

Page 15: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Silicon Nanowire Transistors (IV)Silicon Nanowire Transistors (IV)

Source-drain tunneling above threshold gives a contribution only slightly dependent on L , and significant already for L=25 nm.

Page 16: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

High-k dielectricsHigh-k dielectrics

Lead: Andrea Campera

Page 17: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Structures investigatedStructures investigated

Experimental data: I-V, C-V and I(T)-V In all three cases the substrate is p-doped with NA=5∙1017 cm-3

C-V characteristics have been measured for capacitors of area 70 µm x 70 µm

J-V curves have been measured for n-MOSFET with W=10 µm and L=1, 5 and 10 µm ( we show results only for L=5 µm)

Temperature from 298 to 473 K

SiO2

HfO2

Poly-Si

bulk

4 nm1 nm SiON

HfSiONPoly-Si

bulk

2 nm1 nm SiON

HfSiONPoly-Si

bulk

1 nm1 nm

EOT a) 1.7 nm b) 1.6 nm c) 1.3 nm

Page 18: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

1D Poisson-Schrödinger solver1D Poisson-Schrödinger solver

Poly depletion and finite density of states in the bulk

2

2

1 exp2( ) ln

1 exp

1 exp4( ) ln

1 exp

Fl ilt ril il

Fr ili

Fl itt l rit it

Fr iti

E E kTqkTJ m T E

E E kT

E E kTqkTm m T E

E E kT

Self-consistent solution of the P-S equation, taking into account quantum confinement at the

emitter, quantum confinement in the poly mass anisotropy in CB, light and heavy holes

Extraction of the band profile with the quasi-equilibrium approx., eigenvalues and eigenvectors for electrons and holes

Page 19: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Results: I-V and C-VResults: I-V and C-V

summary of physical parameters extracted for HfO2 , HfSiON and SiON

HfO2 HfSiON SiON

Electron affinity 1.575 eV 1.97 eV 1.27 eV

Electron eff mass

0.08m0 0.24m0 0.45m0

r 25 11 5

FLP 0.35 V 0.13 V -

Page 20: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Experiment: Temperature-dependent Experiment: Temperature-dependent I-VI-V

HfO2 and HfSiON shows a different temperature dependence

A pure tunneling current can explain only transport in HfSiON but not in HfO2

In HfO2 we can observe a strong temperature dependence

Page 21: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

g1= g1c+ g1v

g2= g2c+ g2v

r1= r1c+ r1v

r2= r2c+ r2v

Temperature-dependent transport Temperature-dependent transport modelmodel

1 2 2 1

1 2 1 2TAT

g r g rJ q

g g r r

We assume that transport in HfO2 is due to Trap Assisted Tunneling

gi and ri depend on the properties of traps responsible for transport

They depend on the capture cross section, that we have assumed to be “Arrhenius like”

0 exp BE k T

The TAT current reads

Page 22: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Energy position of traps Energy position of traps

Traps in hafnium oxide from ab-initio calculations

From simulations we observe that traps must be within the energy range 1÷2 eV below the HfO2 conduction band in order to allow us to reproduce the shape of J-V characteristics

We consider that relevant traps are located 1.6 eV below the hafnium oxide CB

Gavartin, Shluger, Foster, Bersuker Jour.Appl. Phys 2005

Page 23: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Simulations of I(V) with varying TSimulations of I(V) with varying T

0.4 0.5 0.6 0.7 0.8 0.9 1.01E-4

1E-3

0.01

0.1

1

10

=0.1 eV

=0.084 eV=0.05 eV

=0.01 eV

measured @ 475 K

Cu

rren

t d

en

sity

(A/m

2 )

Gate Voltage (V)

=0.001 eV

From ETRAP=1.6 eV we can extract Г from the slope of the J-V @ 475 K and σ(475) from the amplitude of the same J-V

At T=475 K TAT is the entire current density We assume that σ has an Arrhenius temperature

dependence and that Г is constant: Then we can extract σ as a function of temperature

320 340 360 380 400 420 440 460 480

0.0

2.0x10-7

4.0x10-7

6.0x10-7

8.0x10-7

1.0x10-6

1.2x10-6

simulated Arrhenius fit

sig

ma

(m2 J

)

Temperature (K)

infexp(-E/kT)

inf= 0.555

E=0.542 eV

0 exp BE k T

Page 24: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Main resultsMain results

0.4 0.6 0.8 1.010-3

10-2

10-1

100

101 theory experiments

Cu

rren

t D

ensi

ty

(A/m

2 )

Gate Voltage (V)

T from 300 to 475 K

0.5 1.0 1.5 2.0100

101

102

103

104

105

106

Experiments @ 400 K Experiments @ 300 K Theory (pure tunneling)

Curr

ent D

ensi

ty (A

/m2 )

Gate Voltage (V)

HfSiON c)

HfO2HfSiON

Transport in HfSiON can be described by pure tunneling processes Transport in HfO2 can be described by temperature dependent TAT Arrhenius like capture cross section Traps involved in transport processes are 1.6 eV below the

hafnium oxide CB (this traps states have been recently found by ab-initio calculations, Gavartin et al. Jour. Appl. Phys 2005)

Page 25: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Decoherence and dephasingDecoherence and dephasing

Lead: Marco Pala*

M. Pala, G. Iannaccone, PRB vol. 69, 235304 (2004)M. Pala, G. Iannaccone, PRL vol. 93, 256803 (2004)

* now with IMEP-CNRS, Grenoble

Page 26: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Transport in mesoscopic structuresTransport in mesoscopic structures

Landauer-Büttiker theory of transport Eigenvalues of the tt† matrix as

enables us to compute conductance and shot noise

Transmission and reflection matrices can be obtained computing the scattering matrix (S-matrix) of the system

The domain is subdivided in several tiny slices in the propagation direction

The S-matrix of the system is obtained by combining the S-matrices of all adjacent slices

n

nhe TG

22

n

nnhVe TTS )1(

32

R

L

R

L

R

L

b

a

rt

tr

b

as

a

b

'

'

Page 27: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Monte Carlo approach (M. Pala, G. Iannaccone, PRB 2004)

Random fluctuation of the phase of all modes

The propagation in each slice is described by a diagonal term in the transmission matrix

We modify the transmission matrix by adding a random phase to each diagonal term

The random phase has a Gaussian distribution with zero average and variance inversely proportional to the dephasing lenght

Each S-matrix is a particular occurrence and the average transport properties are obtained by averaging over a sufficient number of runs

nmxikj

nmRj

jnet

lx jj /2

Page 28: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Aharonov-Bohm rings

Simulation recover experimental results due to the suppression of quantum coherence

Non integer conductance steps are recovered Corrections are of the order of G0

Experiments by A.H.Hansen et al.,

PRB 2004

B=0 Tesla

Page 29: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

MagnetoconductanceMagnetoconductance

Experiment (Hansen et al., PRB 2004)

Theory(Pala et al., 2004)

Page 30: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Density of statesDensity of states

Computation of the partial density of states

Application: Aharonov-Bohm oscillations of a ring

[M.G. Pala and G. Iannaccone, PRB 69, 235304 (2004)]

The wave-like behavior of the propagating mode is destroyed when a strong decoherence is present

2|),,(|),,( EyxEyx

Page 31: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Influence on shot noise (M. Pala et al. PRL 2004)

Aharonov Bohm ring

First order cumulant of the current proportional to conductance

Second order cumulant of the current = Fano factor (prop to noise)

Page 32: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Perspectives of Carbon Perspectives of Carbon Nanotube Field Effect Nanotube Field Effect

TransistorsTransistors

Lead: G. Fiori

Collaboration with Purdue University,

G. Fiori et al., IEDM 2005 – to be published on IEEE-TED, new results at ESSDERC 2006

Page 33: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Discretization : box-integration. Newton-Raphson method with predictor corrector scheme.

n() in the nanotube by means of NEGF

Self-consistent 3D Poisson/NEGF Self-consistent 3D Poisson/NEGF solversolver

The 3D Poisson equation reads

while p(f), ND+(f), NA-(f) e n(f) are computed semiclassically elsewhere. Transport is ballistic.

In particular, the Schrödinger equation has been solved using a tight-binding hamiltonian with an atomistic (pz-orbital) real space basis

Page 34: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Non-Equilibrium Green’s FunctionNon-Equilibrium Green’s Function

The Green’s Function can be expressed as

A point charge approximation is assumed, i.e. all the free charge around each carbon atoms is condensed in the elementary cell including the atom.

Current is computed through the Landauer’s formula

Page 35: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Short Channel Effect in CNT-FETs Short Channel Effect in CNT-FETs (I)(I)

By defining different geometries, we can study how short channel effects can be controlled through different device architectures.

Considered CNT-FET (11,0) zig-zag nanotube doping molar fraction f

= 10-3. gatelength 15 nm SiO2 as gate dielectric. single, double and triple

gate layout.

Page 36: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Short Channel Effect in CNT-FETs Short Channel Effect in CNT-FETs (II)(II)

Quasi-ideal S are obtained for the double gate structure, also for thick oxide thickness.

Good S and DIBL for the single gate device are obtained for tox=2nm. As expected, triple gate layout show better S and DIBL

Page 37: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

IIon per unit width

Ion is one order of magnitude higher than that typically obtained in silicon

warning: ballistic transport and very dense CNTs considered

Page 38: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

High frequency perspectivesHigh frequency perspectives

Optimistic estimate (zero stray capacitances)

Perspective for THz applications

High frequency behaviour is only limited by stray gate capacitance

Page 39: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

TransconductanceTransconductance

Page 40: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

IIoff per unit width

the Ion/Ioff requirement is met for a tube density smaller than 0.1

Page 41: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Efs

Efd

LDOS for Vgs=0, Vds=0.6 VCharge density computed for

Vgs=0 and Vds=0.6 V

electronselectrons

holesholes

Effects of bound states in HOMO Effects of bound states in HOMO (I)(I)

For large drain-to-source voltages, electrons in bound states in the channel can tunnel to states in the drain, leaving holes in the channel. Such effect lowers the barrier seen by propagating electrons in the channel.

Page 42: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

As the drain-to-source voltage is increased, holes are accumulated in the channel and the gate loses control of the potential over the channel, with a degradation of the current in the off-state.

Transfer characteristic for a double gate (14,0) nanotube, with L=10 nm and tox=2 nm

Effects of bound states in HOMO (II)

Page 43: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Work in ProgressWork in Progress

Page 44: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

in Progress: Mobility in Si in Progress: Mobility in Si NanowiresNanowires

Phonon scattering (acousting and optical) Surface Roughness and Cross Section

Fluctuations Impurity Scattering

5 nm

Page 45: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

10 ps

Partially ballistic transportPartially ballistic transport

Boltzmann Transport Equation solved in each 2D subband

Direct solution (no Montecarlo)

S D

Ballistic peak

Page 46: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Partially ballistic transportPartially ballistic transport

Boltzmann Transport Equation solved in each 2D subband

Direct solution (no Montecarlo)

S D

Ballistic peak

1 ps

Page 47: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Partially ballistic transportPartially ballistic transport

Boltzmann Transport Equation solved in each 2D subband

Direct solution (no Montecarlo)

S D

Ballistic peak

1 ps

Page 48: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Partially ballistic transportPartially ballistic transport

Boltzmann Transport Equation solved in each 2D subband

Direct solution (no Montecarlo)

S D

1 ps

Page 49: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Personal ConclusionPersonal Conclusion

Critical objectives of nanoscale device modeling: Provide useful insights of device behavior, helping us to understand

what are the relevant physical aspects for the issues at hand

what are the main trends what we should focus on and what we should

stop.

Such mission does not requires huge do-it-all tools, but simulation tools with different degrees of sophistication, tailored to the particular problem at hand.

Page 50: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Modeling of ballistic and quasi-Modeling of ballistic and quasi-ballistic MOSFETsballistic MOSFETs

Lead: G. Curatola*

In collaboration with Philips Research Leuven,

G. Curatola et al. IEEE-TED vol. 52, p. 1851-1858, 2005

* now with Philips Research Leuven

Page 51: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Typical aspects of the nanoscaleTypical aspects of the nanoscale

DD1st ordermomentum

HD2nd ordermomentum

CompleteThermalization(equilib.)

SCALING DOWNTechnology GenerationTime

Fully ballistictransport

Carrier distribution in the phase space

DSmetal

Polyx

yz

L

STI

Plus: Strong confinement in the 2DEG Strong confinement in the Poly !

Page 52: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Drift-Diffusion per subband Drift-Diffusion per subband

Poisson Eq. + Schrödinger Eq. + Continuity Eq.

Leff

0 x

EFD

EFS

dxxx

dxxyxxy

ii

ii

i)()(

)(),()()(

*

*

F

i

inini

En

nμD

Continuity eq. is solved within each subband obtained after the solution of the 1D Schrödinger equation.

Fermi-Dirac statistics is required.

Full self-consistent approach

Approximation: Semi-empirical local

mobility model is used. The mobility in each

subband is weighted with the corresponding eigenfunction.

Modified diffusion coefficient to include Fermi-Dirac statistics.

Page 53: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Bulk nMOSFETs: Inverse Bulk nMOSFETs: Inverse ModellingModelling

Data (PLI1043 process) from Philips Research Leuven: Doping profile obtained with TSUPREM4 Oxide thickness Tox=1.5nm C-V and I-V characteristics Set of devices with different gate length!

Several Unknowns: Gate length (dispersion with respect to

nominal value) Channel doping Polysilicon Doping LDD, HDD, pocket implant doping

Page 54: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Inverse ModellingInverse Modelling

-1.0 -0.5 0.0 0.5 1.0

0.006

0.008

0.010

0.012

0.014

0.016

ND=1.2 x 1020 cm-3

Experiment NANOTCAD2D

Cap

acita

nce

[F/m

2 ]V

GS [V]

0.0 0.1 0.2 0.3 0.41

2

3

4

5

Dose=6.7*1013 atoms/cm2

Bor

on p

rofil

e [x

1018

cm

-3]

x [nm]

-50 -40 -30 -20 -10 0 10 20 30 40 50

1E18

1E19

1E20L

eff=26nm

degenerate doping level

Dop

ing

[cm

-3]

y [nm]

Long device C-V and I-V

experimental characteristics are used.

Accumulation and low-inversion C-V and I-V used to extract the doping profile in the well.

Donor concentration in the poly extracted from the strong-inversion C-V curve.

Short device Fitting with C-V & I-V

characterization. The doping of pockets,

HDDs and LDDs has been fitted with a Gaussian function

Page 55: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

PLI1043 Process (T10-T07-T05-PLI1043 Process (T10-T07-T05-T04)T04)

0.0 0.2 0.4 0.6 0.8 1.0

1E-4

1E-3

0.01

0.1

1

10

100

1000

LG=200 nm (T07)

Cur

rent

[A/m

]

VGS

[V]

Experiment NANOTCAD2D

-0.2 0.0 0.2 0.4 0.6 0.8 1.01E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

100

1000

LG=64 nm (T05)

Cur

rent

[A/m

]

VGS

[V]

Experiment NANOTCAD2D

0.2 0.4 0.6 0.8 1.01E-5

1E-4

1E-3

0.01

0.1

1

10

100

LG=880 nm (T10)

Cur

rent

[A/m

]

VGS

[V]

Experiment NANOTCAD2D

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.01E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

100

1000

LG=40nm (T04)

Cur

rent

[A/m

]

VGS

[V]

Experiment NANOTCAD2D

Page 56: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

0.0 0.2 0.4 0.6 0.8 1.00

100

200

300

400

500

600

VDS

= 0.05,0.55,1.05 V

Cur

rent

[A/m

]

VGS

[V]

Experiment DD per subband

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.01E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

100

1000

Cur

rent

[A/m

]

VGS

[V]

Experiment DD per subband

64nm nMOSFET (50 nm L64nm nMOSFET (50 nm Leff))

Extracted effective channel lenght: Leff=50nm

Capability to reproduce experimental results both in sub-threshold and in strong-inversion conditions.

Behavior in strong inversion requires that extension resistances are included in the simulation

Note: Electrostatics is more important than the mobility model !!

Page 57: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

-0.2 0.0 0.2 0.4 0.6 0.8 1.00

200

400

600

800

1000

VDS

= 0.05, 0.55, 1.05 V

Cur

rent

[A/m

]

VGS

[V]

Experiment DD per subband

-0.6 -0.3 0.0 0.3 0.6 0.91E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

100

1000

Cur

rent

[A/m

]

VGS

[V]

Experiment DD per subband

Extracted effective channel lenght: Leff=25nm

Capability of reproducing experimental results in the sub-50nm regime.

Comparison with DESSIS-Synopsys. Simulation time comparable.

-0.2 0.0 0.2 0.4 0.6 0.8 1.00

200

400

600

800

1000

VDS

= 0.05, 0.55, 1.05 V

Cur

rent

[A/m

]

VGS

[V]

Experiment NANOTCAD2D DESSIS

40nm nMOSFET (25 nm L40nm nMOSFET (25 nm Leff))

Page 58: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

In the ballistic device a series (extension and overlap) resistance RDS = 110 m has been considered

Extracted velocity:

The ballistic efficiency is about 50%

The 25nm bulk-Si MOSFET roughly operate at 50% of its ballistic limit.

0.00 0.25 0.50 0.75 1.000

200

400

600

800

1000

1200

1400

1600

Cur

rent

[A/m

]

VGS

[V]

Experiment Ballistic + R

SD=110 ohm-um

scmv

scmv

ball

eff

/1035.1

/1022.77

6

Ballistic EfficiencyBallistic Efficiency

Page 59: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Nanocrystal and discrete-trapNanocrystal and discrete-trapFlash memoriesFlash memories

Lead: G. Fiori

G. Fiori et al., APL, vol. 86, 113502 (2005)

In collaboration with LETI, IMEC, STM (now in the FinFlash project)

Page 60: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

M. Saitoh, E. Nagata, and T. Hiramoto, Appl. Phys. Lett., Vol. 82,

No. 11, 2003

Such behavior has been related to the presence of percolating paths in the channel

Nanocrystal memories on SOI wiresNanocrystal memories on SOI wires

Page 61: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Device fabricationDevice fabrication

Device Cross-Section

BOX

Control gate

Control oxide

A-A’

n+ n+Si-filmBOX

Control gate

Control oxide

B-B’

Si-film

DUVDUV E-beam

SiBOX

8” SOI wafers

A

B’B

A’

Realized by G. Molas, B. De Salvo, CEA-LETI

Page 62: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Experimental results (LETI)Experimental results (LETI)

The effect is also observed in the strong inversion regime, when percolating paths cannot possibly be present.

Page 63: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

50nm

S DW

Actual and simulated geometryActual and simulated geometry

S D

Poly gate

Page 64: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Discrete charge distribution in the dot layer Discrete charge distribution in the dot layer (I)(I)

We have then considered a discrete distribution of fixed charge in the dot layer.

Average dot density is 5x1011 cm-2.

Electron density isosurface n=1018 cm-3

computed for VGS=1.6 V

n+

dot layer

L

W

SiO2

xy

z

gate

Page 65: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Discrete charge distribution in the dot layer Discrete charge distribution in the dot layer (II)(II)

strong inversion sub-threshold

Threshold voltage shift over a sample of twelve devices with the same nominal dot density, but with a different discrete distribution of charged dot

Page 66: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Stored charge Stored charge local tunnel current density local tunnel current density (I)(I)

Since dots are charged by direct tunneling current, we have assumed the fixed charge density proportional to the direct tunneling current.

W = 30 nm

W = 80 nm

Electron density isosurface n=7.5x1023m-3 computed for VGS=-0.4 V, in case of charged and discharged dots.

discharged dots

charged dots

Page 67: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

The assumption that the stored charged is proportional to the local current density, allows us to reproduce the experiments behavior

Stored charge Stored charge local tunnel current local tunnel current density (II)density (II)

Page 68: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

““Rounded” structure (2D)Rounded” structure (2D)

This effect is also present also if the structure does not have sharp edges. Consider the minimum curvature structure

Above threshold

Sub-threshold

G. Fiori et al., APL, vol. 86, 113502 (2005)

Page 69: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Effect of a Finite Curvature at the Effect of a Finite Curvature at the edgeedge

63 nm

20 nm

63 nm

20 nm

local tunnel current density along the Si/SiO2 interface

SONOS FinFET structure with round fin edges. Simulation with Silvaco ATLAS + Post processing with in-house tools Curvature radius of 5 nm and 10 nm.

-80 -60 -40 -20 0 20 40 60 80100

101

102

103

104

105

106

curvature radius=10 nm

curvature radius=5 nm

Cu

rren

t D

ensi

ty (

A/m

2 )

Curvilinear Coordinate (nm)

Current is injected mainly

at the edges

Page 70: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Experimental CV-CurvesExperimental CV-Curves From long devices:

extraction of doping profile in the well.

Quantum confinement must be considered both in the polysilicon layer and in the channel.

Region1: Schrödinger

Region2: Potential at the

poly/SiO2 interface is increased due to quantum effects Negative shift of the threshold voltage

-10 -8 -6 -4 -2 0 2 4

0.8

1.0

1.2

1.4

Poly Quantum No Poly Quantum

Pot

entia

l [V

]

x [nm]0 1 2 3 4 5 6

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Ele

ctro

n D

ensi

ty [x

1023

m-3]

x [nm]

Schrödinger + Drift-DiffusionSchrödinger + Ballistic Model

Poly SiO2 Si

Page 71: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Co/Ti

Rcsd Rdeep Rext Rov

Rcsd= contact resistance

Rdeep= HDD resistanceRdeep= extension resistanceRov= overlap resistance

Quantum Box

Series ResistanceSeries Resistance

0.00 0.25 0.50 0.75 1.000

50

100

150

200

LG=40nm (T04)

Cur

rent

[A/m

]

VGS

[V]

Experiment W=10nm W=40nm W=50nm W=180nm

Contact resistance and deep HDD resistance are not included in the simulation.

Overlap and extension resistances considered adjusting the lateral dimension on the quantum region where continuity eq. is solved.

Page 72: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

NanoTCAD2DNanoTCAD2D2D Poisson

ii) i) ii) iii)

i) +

+

+

Quantum Bohm Potential (QBP)

1D SchrödingerBallistic Model (BM)

Drift-diffusion per subband (DDS)

1D Schrödinger2D Schrödinger

The Schrödinger equation must be solved twice for each slice: For the 2 minima along the vertical (kx) direction

For the other 4 minima

lililiClil

yE~Ey,xxmx

1

2

2

tititiCtit

yE~Ey,xxmx

1

2

2

TkEE~

explnTmk

nB

Flili

tBli 12

2

Tk

EE~expln

mmTkn

B

Ftiti

tlBti 12

2kx

ky

kz

kx

kz

ky

Page 73: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Uniform stored charge in the dot Uniform stored charge in the dot layerlayer

The average dot density is 5x1011cm-2. As a first attempt, we have modelled the dot layer

as a uniform fixed charge layer Different behavior from experiments

n+

gate

dot layer

L

W

SiO2

xy

z

Page 74: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

Direct Tunneling CurrentDirect Tunneling Current

i i

tili nnn 42

The current density is larger in correspondence of the corner of the structure.

),( bEJ The direct tunnel current is a

function of the electric field (E) and of the barrier heigth (Φb)

Page 75: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

63 nm

20 nm

Transfer characteristics from 3D Transfer characteristics from 3D simulationsimulation

Curvature radius 5nm

Vth shift of about 0.5 V and dependent on

Effect of the stored charge on Vth shift

The transfer characteristics are not simply shifted

Assumption of locally stored charge proportional to the local Injected tunnel current-1 0 1 2 3 4

10-10

10-9

10-8

10-7

10-6

10-5

10-4

0 1 2 3 4

20

40

60

80

100

Cu

rren

t (A

)

Gate Voltage (V)

Fresh Cell

=3x1019 cm-3

=1020 cm-3

Cu

rren

t (

A)

Gate Voltage (V)

Page 76: Nanoscale Device Modelling: CMOS and beyond

G. Iannaccone Università di Pisa

63 nm

20 nm

Electron concentration at the Si-SiO2 Electron concentration at the Si-SiO2 interfaceinterface

0 10 20 30 40 50 60 701010

1012

1014

1016

1018

1020

1022

Vg=1.0 V

Vg=2.0 V

Vg=3.0 V

Vg=4.0 V

Ele

ctro

n C

once

ntra

tion(

cm-3)

Curvilinear Coordinate (nm)

The stored charge inhibits channel formation ONLY at the edges The programmed device behaves as the parallel of

a low Vth fresh device (channel at the flat fin surface) and a very high Vth device (channel at the fin edges).

0 10 20 30 40 50 60 7010-610-410-2100102104106108

1010101210141016101810201022

Vg=1.0 V

Fresh Cell

=3x1019cm-3

=1020cm-3

Ele

ctro

n C

once

ntra

tion

(cm

-3)

Curvilinear Coordinate (nm)

Programmed cell r=5 nm