teaching cmos circuit design in nanoscale technologies using microwind

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1 TEACHING CMOS CIRCUIT DESIGN IN NANOSCALE TECHNOLOGIES USING MICROWIND Etienne Sicard Sonia Ben Dhia Department of Electrical & Computer Engineering INSA – University of Toulouse France e-mail: [email protected] r [email protected] Syed Mahfuzul Aziz School of Electrical & Information Engineering University of South Australia Australia e-mail: [email protected]. au

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TEACHING CMOS CIRCUIT DESIGN IN NANOSCALE TECHNOLOGIES USING MICROWIND. Syed Mahfuzul Aziz School of Electrical & Information Engineering University of South Australia Australia e-mail: [email protected]. Etienne Sicard Sonia Ben Dhia - PowerPoint PPT Presentation

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Page 1: TEACHING CMOS CIRCUIT DESIGN IN NANOSCALE TECHNOLOGIES USING MICROWIND

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TEACHING CMOS CIRCUIT DESIGN IN NANOSCALE TECHNOLOGIES USING MICROWIND

Etienne Sicard Sonia Ben DhiaDepartment of Electrical & Computer EngineeringINSA – University of ToulouseFrancee-mail: [email protected]@insa-toulouse.fr

Syed Mahfuzul AzizSchool of Electrical & Information EngineeringUniversity of South AustraliaAustraliae-mail: [email protected]

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1. CONTEXT

2. EDUCATIONAL NEEDS

3. MICROWIND

4. EVALUATION

5. PRESPECTIVES

7. CONCLUSION

SUMMARY

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0.18 µm2000

500 MHz

Devices

Interconnects

Frequency 2V

3 nMOS, 3 pMOS

CONTEXT

NANO-CMOS – MORE AND MORE COMPLEX

2005 90 nm

1.5 GHz

1V

6 nMOS, 6 pMOS

2010 32 nm

5 GHz

1V

12 nMOS, 12 pMOS

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CONTEXT

NANO-CMOS – TEACHING CHALLENGE

Low K

Double patterning

Metal gate

nMOS Strain

Pocket implant

pMOS Strain

High K oxide

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

0.0 0.5 1.0

Poly - SiO2

High-

Gate voltage (V)

Drain current (A/µm)

Ioff current decrease

Ion current increase

« Ideal device »

The quest for the « perfect switch »

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CONTEXT

NANO-CMOS – TEACHING CHALLENGE

Parasiticconsumption

High (x 10)

Moderate (x 1)

Low (x 0.1)

Speed

Fast (+50%)

Moderate (0%)

Low (-50%)

High

- end servers

Servers

Networking

Computing

Mobile Computing

Consumer

3G phones

2G phones

MP3

Digital camera High speed

General Purpose

Low leakage

Personal org.

1

10

100

1000

500 1000 1500

Ion (µA/µm)

Ioff (nA/µm)

« Super high

speed »

« Super low

leakage »

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CONTEXT

1995 1998 2001 2004 2007 2010

Complexity(Millions transistors)

0.1

1

10

100

1000

Logic design

Layout design

IP design

Link Controller

Link Controller

RFRF

RSRS

Host Interface

Code Manager

System design

Technology always ahead

2013Microwind

NANO-CMOS – COMPLEXITY CHALLENGETeaching cell design – still necessary ?

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EDUCATIONAL NEEDS

The commercial chip design tools available today are very powerful

However, these tools are highly complex and need long time to learn.

Teaching hours in Nano-CMOS are decreased

Physics of semiconductors are exploding in complexity (100-1000 parameters in MOS models)

Student and engineer diversity must be considered. Gaps in the background knowledge must be addressed

TEACHING NANO-CMOS – TRENDS

PhysicsCMOS design

Teaching hours

System integration

Years

Embedded software

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EDUCATIONAL NEEDS

Tools should be used by large number of students at undergraduate level

Design tools should provide intuitive design, simulation and visualization environments

Design tools should be easily accessible. Most of the work is done out of regular teaching hours (e-learning, project-based..)

Target course and practical training duration: 15 H

TEACHING NANO-CMOS – NEEDS

Professional tools

Graduates

Undergraduates

PhDs

Educational tools Short

sessions :

Simple designConcepts

Long practical sessions :

Ambitious designs

Large number of students

Reduced number of students

Learning curve

Hours

Industry-oriented tools

Education-oriented tools

Rapid progress

5 10 15 20

Slow progress

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MICROWIND

Technology scale down, where we come from, where we are (45 nm), where we go..

A tutorial on MOS devices, based on problem-based learning

The design of inverters, and a simple ring oscillator, and a small student contest.

The design of basic logic gates introducing interconnect design, compact design strategies, and impact on switching speed and power consumption.

The design of analog blocs introducing amplification, voltage reference, addition of analog signals, and mixed-signal blocs

A design project, e.g. converter, processing unit, OpAmp, radio-frequency block, etc..

COURSE CONTENTS (1-2 days)

1995 2000 2005 2010 2015

0.1nm

1nm

10nm

Equivalent Gate Dielectric Thickness

(nm)

Year

0.25m

0.18m

0.13m 90nm

65nm

High voltage MOS (double

gate oxide)

Technology addressed in

2010

22nm Low voltage

MOS (minimum gate oxide)

SiO2 (r=3.9)

SiON (r=4.2-6.5)

HighK (r=7-20)

45nm 32nm

18nm 11nm

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MICROWIND

User-friendly and intuitive design tool for educational use.

The student draws the masks of the circuit layout and performs analog simulation

The tool displays the layout in 2D, static 3D and animated 3D

Editing window

One dot on the grid is 5 lambda, or 0.175 µm

Editing icons

Access to simulation

2D, 3D views

Simulation properties

Layout library

Active technology

Palette of layers

INTRODUCTION THE TOOL

Ion current

Voltage cursors

List of model parameters for BSIM4

Memory effect due to source capacitance

Threshold voltage effect

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MICROWIND

MOS DEVICE

Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids

Our approach : step-by-step illustration of the most important relationships between layout and performance.

1. Design of the MOS

2. I/V Simulation

3. 2D view

4. Time domain analysis

1.

2.

3.4.

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MICROWIND

BASIC GATE DESIGN

Illustration of the most important relationships between layout and performance.

1. Design of pMOS

2. Design of inverters

3. Design of a VCO

4. Try to optimize the VCO for highest possible speed

5. Improve MOS size

6. Change MOS options

7. Make the layout more compact

8. Keep an eye on power consumption

1.2.

3.4.

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MICROWIND

PROJECT EXAMPLES

engage students in a stimulating learning experience using latest CMOS technologies

1. Circuit analysis and optimization using WinSpice

2. Combinational and sequential circuit layouts

3. ALU Design

4. Power amplifier Bluetooth

1.2.

3.4.

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EVALUATION

• The VLSI course was evaluated anonymously by the students

• UNISA course evaluation questionnaire containing ten core questions and open text response.

• The students rated the course very highly in all the evaluation items.

• The course in the in the top-5 courses offered in engineering in UniSA.

• (off-line: Dr. Aziz won the “top teacher of the year” in Australia 2009)

AUDIENCE# Question

1 I have a clear idea of what is expected of me in this course.

2 The ways in which I was taught provided me with opportunities to pursue my own learning.

3 The course enabled me to develop and/or strengthen a number of the qualities of a [University of South Australia,INSA] graduate.

4 I felt there was a genuine interest in my learning needs and progress.

5 The course developed my understanding of concepts and principles

6 The workload for this course was reasonable given my other study commitments

7 I have received feedback that is constructive and helpful.

8 The assessment tasks were related to the qualities of a [University of South Australia, INSA] graduate.

9 The staff teaching in this course showed a genuine interest in their teaching.

10

Overall I was satisfied with the quality of this course

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EVALUATION

Answers to questionnaire

RESULTS

0%10%20%30%40%50%60%70%80%90%

1 2 3 4 5 6 7 8 9 10

Evaluation item #

% r

esp

on

se

Strongly agree Agree Neutral Disagree Strongly disagree

UNISA

0%

10%

20%

30%

40%

50%

60%

70%

80%

1 2 3 4 5 6 7 8 9 10

Evaluation item #

% r

espo

nse

Strongly agree Agree Neutral Disagree Strongly disagree

5. The course developed my

understanding of concepts and

principles

INSA

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EVALUATION

“From just a few logic gates, we have created a 4-stage binary counter and compiled it into layout. It also gave us the basic concepts to understand the operation of the transistors in order to extract their models.”

“The 24-hours clock project was a good exercise which permitted us to see how it is inside a semiconductor and how it works.”

“We learned a lot about designing integrated circuit. We faced some practical problems, and tried to solve them or to understand them.”

“This study allows us to understand the DAC running. In spite of some design problems, we managed to make the DAC work well.”

“Before doing this project, we hadn’t thought that there are as many ways to realize an amplifier. It’s an area not easy to understand. Each technique has its limit. We tried to optimize our operational amplifier design to maximize the gain.”

COMMENTS

Students“The tools along with the project-based course resources have assisted us to develop an educational program in our Bachelor of Engineering Program. The tools offer easy to use menus for design and simulation, and the choice of a range of technology models to enable students to develop critical design and analysis skills using the latest technologies.” (Malaysia).

“Microwind and Dsch tools are used for VLSI teaching programs at both postgraduate and undergraduate levels. The project-based methodology supported by a variety of learning resources has made the learning of VLSI Design very stimulating.” (Bangladesh).

“Exploring the tools is a lot of fun. The interface is very friendly, and the program is both educational and useful for designing CMOS chips.” (USA)

Teachers

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PERSPECTIVES

• Application note on 32 nm & 22 nm technologies

• Application note on process variability and Monte-Carlo simulation

• 3D views of packages based on IBIS

• 3D views of carbon-nano tubes

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Intuitive and user friendly design tools enabled students to develop circuit

design skills using nano-CMOS technologies

Illustrations (2D, 3D, I/V) help to handle increased process complexity and

refinements

Effective project-based learning methodologies, helping to understand the

impacts of technology scale down on factors such as speed, power and

noise.

Digital and analog basic bloc design with high levels of student satisfaction.

Projects stimulate student curiosity and thinking.

Software to be tuned to 22, 17 and 11 nm technologies

Novel devices to be introduced when appropriate

CONCLUSION

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[1] E. Sicard and S. Ben Dhia “Basic CMOS Cell Design” McGraw Hill professional series, 2006.[2] E. Sicard and S. Ben Dhia “Advanced

CMOS Cell Design” McGraw-Hill professional series, 2007.[3] E. Sicard, “Microwind & Dsch User's

Manual, Version 3.5”, June 2009. Online at www.microwind.org.[4] S. M. Aziz, E. Sicard, S. Ben Dhia “Effective

Teaching in Physical Design of Integrated Circuits using Educational Tools” to appear IEEE Trans Education, 2010

REFERENCES

The tool, manual and course slides are online at www.microwind.org

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REFERENCES

MICROWIND DOWNLOADS – www.microwind.net

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THANK YOU FOR YOUR ATTENTION