lab manual ic

8/13/2019 Lab Manual ic

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DIGITAL ELECTRONICS LAB

Ex. No:1

STUDY OF LOGIC GATESDate:

AIM:To study about logic gates and e!i"y t#ei! t!ut# tables$

APPARATUS REQUIRED:

THEORY:

Ci!cuit t#at ta%es t#e logical decision and t#e &!ocess a!e called logic gates$

Eac# gate #as one o! 'o!e in&ut and only one out&ut$

OR( AND and NOT a!e basic gates$ NAND( NOR and )*OR a!e %no+n as

unie!sal gates$ Basic gates "o!' t#ese gates$

AND GATE:

Page No: ,

SL No$ CO-.ONENT S.ECIFICATION /TY

0$ AND GATE IC 1,23 0

4$ OR GATE IC 1,54 0

5$ NOT GATE IC 1,2, 0

,$ NAND GATE 4 I6. IC 1,22 07$ NOR GATE IC 1,24 0

8$ )*OR GATE IC 1,38 0

1$ NAND GATE 5 I6. IC 1,02 0

3$ IC TRAINER 9IT * 0

:$ .ATC; CORD * 0,


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T#e AND gate &e!"o!'s a logical 'ulti&lication co''only %no+n as AND

"unction$ T#e out&ut is #ig# +#en bot# t#e in&uts a!e #ig#$ T#e out&ut is lo+ leel

+#en any one o" t#e in&uts is lo+$

OR GATE:

T#e OR gate &e!"o!'s a logical addition co''only %no+n as OR "unction$

T#e out&ut is #ig# +#en any one o" t#e in&uts is #ig#$ T#e out&ut is lo+ leel +#en

bot# t#e in&uts a!e lo+$

NOT GATE:

T#e NOT gate is called an ine!te!$ T#e out&ut is #ig# +#en t#e in&ut is

lo+$ T#e out&ut is lo+ +#en t#e in&ut is #ig#$

NAND GATE:

T#e NAND gate is a cont!action o" AND*NOT$ T#e out&ut is #ig# +#en bot#

in&uts a!e lo+ and any one o" t#e in&ut is lo+ $T#e out&ut is lo+ leel +#en bot#

in&uts a!e #ig#$

NOR GATE:

T#e NOR gate is a cont!action o" OR*NOT$ T#e out&ut is #ig# +#en bot#

in&uts a!e lo+$ T#e out&ut is lo+ +#en one o! bot# in&uts a!e #ig#$

X-OR GATE:

T#e out&ut is #ig# +#en any one o" t#e in&uts is #ig#$ T#e out&ut is lo+ +#en

bot# t#e in&uts a!e lo+ and bot# t#e in&uts a!e #ig#$

Page No: 7


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PROCEDURE:


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NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

Page No: 1


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-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

!-INPUT NAND GATE :

Page No: 3


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NOR GATE:

Page No: :


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RESULT:

T#us t#e logic gates a!e studied and t#ei! t!ut# tables a!e e!i"ied$

Ex. No:

DESIGN OF ADDER AND SUBTRACTORDate:

AIM:To design and const!uct #al" adde!( "ull adde!( #al" subt!acto! and "ull

subt!acto! ci!cuits and e!i"y t#e t!ut# table using logic gates$

APPARATUS REQUIRED:

Sl$No$ CO-.ONENT S.ECIFICATION /TY$

0$ AND GATE IC 1,23 0

4$ )*OR GATE IC 1,38 0


,$ OR GATE IC 1,54 0


,$ .ATC; CORDS * 45

THEORY:

Page No: 02


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HAL" ADDER:

A #al" adde! #as t+o in&uts "o! t#e t+o bits to be added and t+o out&uts one

"!o' t#e su' > S? and ot#e! "!o' t#e ca!!y > c? into t#e #ig#e! adde! &osition$ Aboe

ci!cuit is called as a ca!!y signal "!o' t#e addition o" t#e less signi"icant bits su'

"!o' t#e )*OR Gate t#e ca!!y out "!o' t#e AND gate$

"ULL ADDER:

A "ull adde! is a co'binational ci!cuit t#at "o!'s t#e a!it#'etic su' o" in&ut@ it

consists o" t#!ee in&uts and t+o out&uts$ A "ull adde! is use"ul to add t#!ee bits at a

ti'e but a #al" adde! cannot do so$ In "ull adde! su' out&ut +ill be ta%en "!o' )*OR

Gate( ca!!y out&ut +ill be ta%en "!o' OR Gate$

HAL" SUBTRACTOR:

T#e #al" subt!acto! is const!ucted using )*OR and AND Gate$ T#e #al"

subt!acto! #as t+o in&ut and t+o out&uts$ T#e out&uts a!e di""e!ence and bo!!o+$ T#e

di""e!ence can be a&&lied using )*OR Gate( bo!!o+ out&ut can be i'&le'ented using

an AND Gate and an ine!te!$

"ULL SUBTRACTOR:

T#e "ull subt!acto! is a co'bination o" )*OR( AND( OR( NOT Gates$ In a "ull

subt!acto! t#e logic ci!cuit s#ould #ae t#!ee in&uts and t+o out&uts$ T#e t+o #al"

subt!acto! &ut toget#e! gies a "ull subt!acto! $T#e "i!st #al" subt!acto! +ill be C and

A B$ T#e out&ut +ill be di""e!ence out&ut o" "ull subt!acto!$ T#e e&!ession AB

asse'bles t#e bo!!o+ out&ut o" t#e #al" subt!acto! and t#e second te!' is t#e ine!ted

di""e!ence out&ut o" "i!st )*OR$

LOGIC DIAGRAM:

HAL" ADDER

Page No: 00


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TRUTH TABLE:

A B CARRY SUM

#

#

1

1

#

1

#

1

#

#

#

1

#

1

1

#

$-Ma% &o' SUM: $-Ma% &o' CARRY:

SUM ( A)B * AB) CARRY ( AB

LOGIC DIAGRAM:

"ULL ADDER USING T+O HAL" ADDER

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TRUTH TABLE:

A B C CARRY SUM

#

##

#

1

1

1

1

#

#1

1

#

#

1

1

#

1#

1

#

1

#

1

#

##

1

#

1

1

1

#

11

#

1

#

#

1

$-Ma% &o' SUM: $-Ma% &o' CARRY:

SUM ( A)B)C * A)BC) * ABC) * ABC CARRY ( AB * BC * AC

LOGIC DIAGRAM:

HAL" SUBTRACTOR

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TRUTH TABLE:

A B BORRO+ DI""ERENCE

#

#

1

1

#

1

#

1

#

1

#

#

#

1

1

#

$-Ma% &o' DI""ERENCE: $-Ma% &o' BORRO+:

DI""ERENCE ( A)B * AB) BORRO+ ( A)B

"ULL SUBTRACTOR

Page No: 0,


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"ULL SUBTRACTOR USING T+O HAL" SUBTRACTOR:

TRUTH TABLE:

A B C BORRO+ DI""ERENCE

#

#

##

1

1

1

1

#

#

11

#

#

1

1

#

1

#1

#

1

#

1

#

1

11

#

#

#

1

#

1

1#

1

#

#

1

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$-Ma% &o' D,&&e'ee: $-Ma% &o' Bo''o/:

D,&&e'ee ( A)B)C * A)BC) * AB)C) * ABC Bo''o/ ( A)B * BC * A)C

PROCEEDURE:


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Ex. No: !

DESIGN AND IMPLEMENTATION O" CODE CON0ERTORDate:

AIM:To design and i'&le'ent ,*bit


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A t+o*leel logic diag!a' 'ay be obtained di!ectly "!o' t#e Boolean

e&!essions de!ied by t#e 'a&s$ T#ese a!e a!ious ot#e! &ossibilities "o! a logic

diag!a' t#at i'&le'ents t#is ci!cuit$

LOGIC DIAGRAM:BINARY TO GRAY CODE CON0ERTOR

$-Ma% &o' G!: $-Ma% &o' G:

G!( B!

$-Ma% &o' G1: $-Ma% &o' G#:

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TRUTH TABLE:

B,a'2 ,%3t G'a2 o4e o3t%3t

B! B B1 B# G! G G1 G#

#

#

##

#

#

#

#

1

1

1

1

11

1

1

#

#

##

1

1

1

1

#

#

#

#

11

1

1

#

#

11

#

#

1

1

#

#

1

1

##

1

1

#

1

#1

#

1

#

1

#

1

#

1

#1

#

1

#

#

##

#

#

#

#

1

1

1

1

11

1

1

#

#

##

1

1

1

1

1

1

1

1

##

#

#

#

#

11

1

1

#

#

#

#

1

1

11

#

#

#

1

1#

#

1

1

#

#

1

1

#

#1

1

#

LOGIC DIAGRAM:

GRAY CODE TO BINARY CON0ERTOR

Page No: 0:


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TRUTH TABLE:

G'a2 Co4e B,a'2 Co4e

G! G G1 G# B! B B1 B#

#

#

#

#

#

#

#

#

1

11

1

1

1

1

1

#

#

#

#

1

1

1

1

1

11

1

#

#

#

#

#

#

1

1

1

1

#

#

#

#1

1

1

1

#

#

#

1

1

#

#

1

1

#

#

11

#

#

1

1

#

#

#

#

#

#

#

#

#

1

11

1

1

1

1

1

#

#

#

#

1

1

1

1

#

##

#

1

1

1

1

#

#

1

1

#

#

1

1

#

#1

1

#

#

1

1

#

1

#

1

#

1

#

1

#

1#

1

#

1

#

1

$-Ma% &o' B!: $-Ma% &o' B:

B! ( G!

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$-Ma% &o' B1: $-Ma% &o' B#:

LOGIC DIAGRAM:

BCD TO EXCESS-! CON0ERTOR

$-Ma% &o' E!: $-Ma% &o' E:

E! ( B! * B 5B# * B16

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$-Ma% &o' E1: $-Ma% &o' E#:

TRUTH TABLE:

BCD ,%3t Exe77 8 ! o3t%3t

B! B B1 B# G! G G1 G#

#

#

#

#

##

#

#

1

1

1

1

1

11

1

#

#

#

#

11

1

1

#

#

#

#

1

11

1

#

#

1

1

##

1

1

#

#

1

1

#

#1

1

#

1

#

1

#1

#

1

#

1

#

1

#

1#

1

#

#

#

#

#1

1

1

1

1

x

x

x

xx

x

#

1

1

1

1#

#

#

#

1

x

x

x

xx

x

1

#

#

1

1#

#

1

1

#

x

x

x

xx

x

1

#

1

#

1#

1

#

1

#

x

x

x

xx

x

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EXCESS-! TO BCD CON0ERTOR:

$-Ma% &o' A: $-Ma% &o' B:

A ( X1 X * X! X9 X1

$-Ma% &o' C: $-Ma% &o' D:

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TRUTH TABLE:

Exe77 8 ! I%3t BCD O3t%3t

B! B B1 B# G! G G1 G#

#

#

#

#

#

1

1

11

1

#

1

1

1

1

#

#

##

1

1

#

#

1

1

#

#

11

#

1

#

1

#

1

#

1

#1

#

#

#

#

#

#

#

#

#1

1

#

#

#

#

1

1

1

1#

#

#

#

1

1

#

#

1

1#

#

#

1

#

1

#

1

#

1#

1

PROCEDURE:


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Ex. No: 9

DESIGN OF ,*BIT ADDER AND SUBTRACTORDate:

AIM:

To design and i'&le'ent ,*bit adde! and subt!acto! using IC 1,35$

APPARATUS REQUIRED:

Sl$No$ CO-.ONENT S.ECIFICATION /TY$0$ IC IC 1,35 0

4$ E)*OR GATE IC 1,38 0



,$ .ATC; CORDS * ,2

THEORY:

9 BIT BINARY ADDER:A bina!y adde! is a digital ci!cuit t#at &!oduces t#e a!it#'etic su' o" t+o

bina!y nu'be!s$ It can be const!ucted +it# "ull adde!s connected in cascade( +it# t#e

out&ut ca!!y "!o' eac# "ull adde! connected to t#e in&ut ca!!y o" net "ull adde! in

c#ain$ T#e augends bits o" >A? and t#e addend bits o" >B? a!e designated by subsc!i&t

nu'be!s "!o' !ig#t to le"t( +it# subsc!i&t 2 denoting t#e least signi"icant bits$ T#e

ca!!ies a!e connected in c#ain t#!oug# t#e "ull adde!$ T#e in&ut ca!!y to t#e adde! is

C2and it !i&&les t#!oug# t#e "ull adde! to t#e out&ut ca!!y C,$

9 BIT BINARY SUBTRACTOR:

T#e ci!cuit "o! subt!acting A*B consists o" an adde! +it# ine!te!s( &laced

bet+een eac# data in&ut >B? and t#e co!!es&onding in&ut o" "ull adde!$ T#e in&ut

ca!!y C2'ust be eual to 0 +#en &e!"o!'ing subt!action$

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9 BIT BINARY ADDERSUBTRACTOR:

T#e addition and subt!action o&e!ation can be co'bined into one ci!cuit +it#

one co''on bina!y adde!$ T#e 'ode in&ut - cont!ols t#e o&e!ation$ #en -2( t#e

ci!cuit is adde! ci!cuit$ #en -0( it beco'es subt!acto!$

9 BIT BCD ADDER:

Conside! t#e a!it#'etic addition o" t+o deci'al digits in BCD( toget#e! +it#

an in&ut ca!!y "!o' a &!eious stage$ Since eac# in&ut digit does not eceed :( t#e

out&ut su' cannot be g!eate! t#an 0:( t#e 0 in t#e su' being an in&ut ca!!y$ T#e

out&ut o" t+o deci'al digits 'ust be !e&!esented in BCD and s#ould a&&ea! in t#e

"o!' listed in t#e colu'ns$

ABCD adde! t#at adds 4 BCD digits and &!oduce a su' digit in BCD$ T#e 4

deci'al digits( toget#e! +it# t#e in&ut ca!!y( a!e "i!st added in t#e to& , bit adde! to

&!oduce t#e bina!y su'$

PIN DIAGRAM "OR IC ;9

Page No: 48


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LOGIC DIAGRAM:

9-BIT BINARY ADDER

LOGIC DIAGRAM:

9-BIT BINARY SUBTRACTOR

Page No: 41


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LOGIC DIAGRAM:

9-BIT BINARY ADDERSUBTRACTOR

Page No: 43


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TRUTH TABLE:

LOGIC DIAGRAM:

BCD ADDER

Page No: 4:

I%3t Data A I%3t Data B A44,t,o S3=t'at,o

A9 A! A A1 B9 B! B B1 C S9 S! S S1 B D9 D! D D1

1 # # # # # 1 # # 1 # 1 # 1 # 1 1 #

1 # # # 1 # # # 1 # # # # 1 # # # #

# # 1 # 1 # # # # 1 # 1 # # 1 # 1 #

# # # 1 # 1 1 1 # 1 # # # # 1 # 1 #

1 # 1 # 1 # 1 1 1 # # 1 # # 1 1 1 1

1 1 1 # 1 1 1 1 1 1 # 1 # # 1 1 1 1

1 # 1 # 1 1 # 1 1 # 1 1 1 # 1 1 # 1


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$ MAP

Y ( S9 5S! * S6

TRUTH TABLE:

BCD SUM CARRY

S9 S! S S1 C

# # # # #

# # # 1 #

# # 1 # #

# # 1 1 ## 1 # # #

# 1 # 1 #

# 1 1 # #

# 1 1 1 #

1 # # # #

1 # # 1 #

1 # 1 # 1

1 # 1 1 1

1 1 # # 1

1 1 # 1 1

1 1 1 # 1

1 1 1 1 1

PROCEDURE:


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THEORY:

T#e co'&a!ison o" t+o nu'be!s is an o&e!ato! t#at dete!'ine one nu'be! is

g!eate! t#an( less t#an


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$ MAP

Page No: 55


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TRUTH TABLE

A1 A# B1 B# A ? B A ( B A @ B

# # # # # 1 #

# # # 1 # # 1

# # 1 # # # 1

# # 1 1 # # 1# 1 # # 1 # #

# 1 # 1 # 1 #

# 1 1 # # # 1

# 1 1 1 # # 1

1 # # # 1 # #

1 # # 1 1 # #

1 # 1 # # 1 #

1 # 1 1 # # 1

1 1 # # 1 # #1 1 # 1 1 # #

1 1 1 # 1 # #

1 1 1 1 # 1 #

PIN DIAGRAM "OR IC ;9:

Page No: 5,


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LOGIC DIAGRAM:

< BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A?B A(B A@B# # # # # # # # # # # # # # # # # 1 #

# # # 1 # # # 1 # # # # # # # # 1 # #

# # # # # # # # # # # 1 # # # 1 # # 1

PROCEDURE:

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Ex. No:

1 BIT ODDE0EN PARITY CHEC$ER GENERATORDate:

AIM:

To design and i'&le'ent 08 bit odd6een &a!ity c#ec%e! and gene!ato! using

IC 1,032$

APPARATUS REQUIRED:



0$ .ARITY IC IC 1,032 4

4$ IC TRAINER 9IT * 05$ .ATC; CORDS * 52

THEORY:

A &a!ity bit is used "o! detecting e!!o!s du!ing t!ans'ission o" bina!y

in"o!'ation$ A &a!ity bit is an et!a bit included +it# a bina!y 'essage to 'a%e t#e

nu'be! is eit#e! een o! odd$ T#e 'essage including t#e &a!ity bit is t!ans'itted and

t#en c#ec%ed at t#e !eceie! ends "o! e!!o!s$ An e!!o! is detected i" t#e c#ec%ed &a!ity

bit doesn?t co!!es&ond to t#e one t!ans'itted$ T#e ci!cuit t#at gene!ates t#e &a!ity bit

in t#e t!ans'itte! is called a >&a!ity gene!ato!? and t#e ci!cuit t#at c#ec%s t#e &a!ity in

t#e !eceie! is called a >&a!ity c#ec%e!?$

In een &a!ity( t#e added &a!ity bit +ill 'a%e t#e total nu'be! is een a'ount$

In odd &a!ity( t#e added &a!ity bit +ill 'a%e t#e total nu'be! is odd a'ount$ T#e

&a!ity c#ec%e! ci!cuit c#ec%s "o! &ossible e!!o!s in t#e t!ans'ission$ I" t#e in"o!'ation

is &assed in een &a!ity( t#en t#e bits !eui!ed 'ust #ae an een nu'be! o" 0?s$ An

e!!o! occu! du!ing t!ans'ission( i" t#e !eceied bits #ae an odd nu'be! o" 0?s

indicating t#at one bit #as c#anged in alue du!ing t!ans'ission$

PIN DIAGRAM "OR IC ;91


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"UNCTION TABLE:

INPUTS OUTPUTS

N3=e' o& H,g Data

I%3t7 5I# 8 I;6

PE PO E O

E0EN 1 # 1 #

ODD 1 # # 1

E0EN # 1 # 1

ODD # 1 1 #

X 1 1 # #

X # # 1 1

LOGIC DIAGRAM:

1 BIT ODDE0EN PARITY CHEC$ER

TRUTH TABLE:

Page No: 53


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38/74


DESIGN AND IMPLEMENTATION O" MULTIPLEXER AND

DEMULTIPLEXER

Date:

AIM:

To design and i'&le'ent 'ulti&lee! and de'ulti&lee! using logic gates and

study o" IC 1,072 and IC 1,07,$

APPARATUS REQUIRED:


0$ 5 I6. AND GATE IC 1,00 4




5$ .ATC; CORDS * 54

THEORY:

MULTIPLEXER:

-ulti&lee! 'eans t!ans'itting a la!ge nu'be! o" in"o!'ation units oe! a

s'alle! nu'be! o" c#annels o! lines$ A digital 'ulti&lee! is a co'binational ci!cuit

t#at selects bina!y in"o!'ation "!o' one o" 'any in&ut lines and di!ects it to a single

out&ut line$ T#e selection o" a &a!ticula! in&ut line is cont!olled by a set o" selection

lines$ No!'ally t#e!e a!e 4nin&ut line and n selection lines +#ose bit co'bination

dete!'ine +#ic# in&ut is selected$

DEMULTIPLEXER:

T#e "unction o" De'ulti&lee! is in cont!ast to 'ulti&lee! "unction$ It ta%es

in"o!'ation "!o' one line and dist!ibutes it to a gien nu'be! o" out&ut lines$ Fo! t#is

!eason( t#e de'ulti&lee! is also %no+n as a data dist!ibuto!$ Decode! can also be

used as de'ulti&lee!$ In t#e 0J , de'ulti&lee! ci!cuit( t#e data in&ut line goes to all

o" t#e AND gates$ T#e data select lines enable only one gate at a ti'e and t#e data on

t#e data in&ut line +ill &ass t#!oug# t#e selected gate to t#e associated data out&ut

line$

Page No: ,0


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BLOC$ DIAGRAM "OR 9:1 MULTIPLEXER:

"UNCTION TABLE:

S1 S# INPUTS Y

# # D# F D# S1) S#)

# 1 D1 F D1 S1) S#

1 # D F D S1 S#)

1 1 D! F D! S1 S#

Y ( D# S1) S#) * D1 S1) S# * D S1 S#) * D! S1 S#

CIRCUIT DIAGRAM "OR MULTIPLEXER:

TRUTH TABLE:

S1 S# Y ( OUTPUT

# # D#

# 1 D1

1 # D

1 1 D!

Page No: ,4


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BLOC$ DIAGRAM "OR 1:9 DEMULTIPLEXER:

"UNCTION TABLE:

S1 S# INPUT

# # X F D# ( X S1) S#)

# 1 X F D1 ( X S1) S#

1 # X F D ( X S1 S#)

1 1 X F D! ( X S1 S#

Y ( X S1) S#) * X S1) S# * X S1 S#) * X S1 S#

TRUTH TABLE:

INPUT OUTPUT

S1 S# IP D# D1 D D!

# # # # # # #

# # 1 1 # # #

# 1 # # # # #

# 1 1 # 1 # #1 # # # # # #

1 # 1 # # 1 #

1 1 # # # # #

1 1 1 # # # 1

Page No: ,5


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LOGIC DIAGRAM "OR DEMULTIPLEXER:

TRUTH TABLE:

INPUT OUTPUTS1 S# IP D# D1 D D!# # # # # # ## # 1 1 # # #

# 1 # # # # ## 1 1 # 1 # #1 # # # # # #1 # 1 # # 1 #1 1 # # # # #1 1 1 # # # 1

PIN DIAGRAM "OR IC ;91>#:

Page No: ,,


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PIN DIAGRAM "OR IC ;91>9:

PROCEDURE:


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RESULT:

T#us t#e 'ulti&lee! and de'ulti&lee! ci!cuits a!e designed and i'&le'ented

using logic gates( IC 1,072 and IC 1,07,$

Ex. No: :BCD TO DECIMAL DECODER:

PIN DIAGRAM "OR IC ;919;:

Page No: ,1


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LOGIC DIAGRAM "OR ENCODER:

Page No: ,3


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TRUTH TABLE:

INPUT OUTPUT

Y1 Y Y! Y9 Y> Y Y; A B C

1 # # # # # # # # 1

# 1 # # # # # # 1 #

# # 1 # # # # # 1 1# # # 1 # # # 1 # #

# # # # 1 # # 1 # 1

# # # # # 1 # 1 1 #

# # # # # # 1 1 1 1

LOGIC DIAGRAM "OR DECODER:

TRUTH TABLE:

Page No: ,:


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INPUT OUTPUT

E A B D# D1 D D!

1 # # 1 1 1 1

# # # # 1 1 1

# # 1 1 # 1 1

# 1 # 1 1 # 1# 1 1 1 1 1 #

PROCEDURE:


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RESULT:

T#us t#e encode! and decode! ci!cuits +e!e designed and i'&le'ented using

logic gates( IC 1,,7 and IC 1,0,1$

Ex. No:

CONSTRUCTION AND 0ERI"ICATION O" 9 BIT RIPPLE

COUNTER AND MOD 1#MOD 1 RIPPLE COUNTERDate:

AIM:

To design and e!i"y , bit !i&&le counte! 'od 026 'od 04 !i&&le counte!$

APPARATUS REQUIRED:


0$ 9 FLI. FLO. IC 1,18 4

4$ NAND GATE IC 1,22 0


,$ .ATC; CORDS * 52

THEORY:

A counte! is a !egiste! ca&able o" counting nu'be! o" cloc% &ulse a!!iing at its

cloc% in&ut$ Counte! !e&!esents t#e nu'be! o" cloc% &ulses a!!ied$ A s&eci"ied

seuence o" states a&&ea!s as counte! out&ut$ T#is is t#e 'ain di""e!ence bet+een a

!egiste! and a counte!$ In sync#!onous co''on cloc% is gien to all "li& "lo& and in

async#!onous "i!st "li& "lo& is cloc%ed by ete!nal &ulse and t#en eac# successie "li&

"lo& is cloc%ed by / o! / out&ut o" &!eious stage$ Because o" in#e!ent &!o&agation

delay ti'e all "li& "lo&s a!e not actiated at sa'e ti'e +#ic# !esults in async#!onous

o&e!ation$

PIN DIAGRAM "OR IC ;9;:

Page No: 70


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LOGIC DIAGRAM "OR 9 BIT RIPPLE COUNTER:

TRUTH TABLE:

CL$ QA QB QC QD

# # # # #

1 1 # # #

# 1 # #! 1 1 # #

9 # # 1 #

> 1 # 1 #

# 1 1 #

; 1 1 1 #

< # # # 1

1 # # 1

Page No: 74


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1# # 1 # 1

11 1 1 # 1

1 # # 1 1

1! 1 # 1 1

19 # 1 1 1

1> 1 1 1 1

LOGIC DIAGRAM "OR MOD - 1# RIPPLE COUNTER:

TRUTH TABLE:

CL$ QA QB QC QD

# # # # #

1 1 # # # # 1 # #

! 1 1 # #

9 # # 1 #

> 1 # 1 #

# 1 1 #

; 1 1 1 #

< # # # 1

Page No: 75


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1 # # 1

1# # # # #

LOGIC DIAGRAM "OR MOD - 1 RIPPLE COUNTER:

TRUTH TABLE:

CL$ QA QB QC QD

# # # # #1 1 # # #

# 1 # #

! 1 1 # #

9 # # 1 #

> 1 # 1 #

# 1 1 #

; 1 1 1 #

< # # # 1

1 # # 11# # 1 # 1

11 1 1 # 1

1 # # # #

Page No: 7,


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PROCEDURE:


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E$ NoJ 02

DESIGN AND IMPLEMENTATION O" ! BIT

SYNCHRONOUS UPDO+N COUNTERDateJ

AIM:To design and i'&le'ent 5 bit sync#!onous u&6do+n counte!$

APPARATUS REQUIRED:


0$ 9 FLI. FLO. IC 1,18 4

4$ 5 I6. AND GATE IC 1,00 0


,$ )OR GATE IC 1,38 0

7$ NOT GATE IC 1,2, 08$ IC TRAINER 9IT * 0

1$ .ATC; CORDS * 57

THEORY:

A counte! is a !egiste! ca&able o" counting nu'be! o" cloc% &ulse a!!iing at its

cloc% in&ut$ Counte! !e&!esents t#e nu'be! o" cloc% &ulses a!!ied$ An u&6do+n

counte! is one t#at is ca&able o" &!og!essing in inc!easing o!de! o! dec!easing o!de!

t#!oug# a ce!tain seuence$ An u&6do+n counte! is also called bidi!ectional counte!$

Usually u&6do+n o&e!ation o" t#e counte! is cont!olled by u&6do+n signal$ #en t#is

signal is #ig# counte! goes t#!oug# u& seuence and +#en u&6do+n signal is lo+

counte! "ollo+s !ee!se seuence$

$ MAP:

Page No: 78


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STATE DIAGRAM:

CHARACTERISTICS TABLE:

Q Qt*1 $

# # # X

# 1 1 X

1 # X 1

1 1 X #

LOGIC DIAGRAM:

Page No: 71


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TRUTH TABLE:

I%3t

U%Do/

P'e7et State

QA QB QC

Next State

QA*1 QB*1 QC*1

A

A $A

B

B $B

C

C $C

# # # # 1 1 1 1 X 1 X 1 X

# 1 1 1 1 1 # X # X # X 1

# 1 1 # 1 # 1 X # X 1 1 X

# 1 # 1 1 # # X # # X X 1

# 1 # # # 1 1 X 1 1 X 1 X# # 1 1 # 1 # # X X # X 1

# # 1 # # # 1 # X X 1 1 X

# # # 1 # # # # X # X X 1

1 # # # # # 1 # X # X 1 X

1 # # 1 # 1 # # X 1 X X 1

1 # 1 # # 1 1 # X X # 1 X

1 # 1 1 1 # # 1 X X 1 X 1

1 1 # # 1 # 1 X # # X 1 X

1 1 # 1 1 1 # X # 1 X X 1

1 1 1 # 1 1 1 X # X # 1 X

1 1 1 1 # # # X 1 X 1 X 1

PROCEDURE:


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57/74


AIM:

To design and i'&le'ent


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TRUTH TABLE:

CL$

Se',a , Se',a o3t

1 1 #

# #

! # #

9 1 1

> X #

X #

; X 1

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPUT

Page No: 80


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CL$ DATA QA QB QC QD1 1 1 # # #

# # 1 # #

! # # # 1 1

9 1 1 # # 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

TRUTH TABLE:CL$ Q! Q Q1 Q# OP

# 1 # # 1 1

1 # # # # #

# # # # #

! # # # # 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

Page No: 84


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TRUTH TABLE:

CL$

DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD

1 1 # # 1 1 # # 1

1 # 1 # 1 # 1 #

PROCEDURE:


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AIM:

To +!ite t#e Me!ilog ;DL &!og!a' "o! adde! and subt!acto! ci!cuit and

si'ulate it using ISE si'ulato!$

HARD+AREJ SO"T+ARE REQUIRED:

)ILIN9 :$0i Si'ulato!

.C IT; INDOS*).

THEORY:

HAL" ADDER:

F!o' t#e e!bal e&lanation o" a #al" adde!( +e "ind t#at t#is ci!cuit needs t+o

bina!y in&uts and t+o bina!y out&uts$ T#e in&ut a!iables designate t#e augends and

addend bits@ t#e out&ut a!iables &!oduce t#e su' and ca!!y$ e assign sy'bol >a?

and >b? to t#e in&uts and S a?

and >b?( !e&!esent t#e t+o signi"icant bits to be added$ T#e t#i!d in&ut >c? !e&!esents

t#e ca!!y "!o' t#e &!eious lo+e! signi"icant &osition$ T+o out&uts a!e necessa!ybecause t#e a!it#'etic su' o" t#!ee bina!y digits !anges in alue "!o' 2 to 5( and

bina!y 4 o! 5 needs t+o digits$ T#e t+o out&uts a!e designated by t#e sy'bols S "o!

su' and D "o! ca!!y$ T#e bina!y a!iable S gies t#e alue o" t#e least signi"icant bit

o" t#e su'$ T#e bina!y a!iable D gies t#e out&ut ca!!y$ T#e t!ut# table o" t#e "ull

adde! is listed in table$ T#e eig#t !o+s unde! t#e in&ut a!iables designate all

&ossible co'binations o" t#e a!iables$ T#e out&ut a!iables a!e dete!'ined "!o' t#e

a!it#'etic su' o" t#e in&ut bits$ #en all in&ut bits a!e 2( t#e out&ut is 2$ T#e S

Page No: 8,


62/74


out&ut is eual to 0 +#en only one in&ut is eual to 0 o! +#en all t#!ee in&uts a!e

eual to 0$ T#e D out&ut #as a ca!!y o" 0 i" t+o o! t#!ee in&uts a!e eual to 0$

T#e in&ut and out&ut bits o" t#e co'binational ci!cuit di""e!ent inte!&!etations at

a!ious stages o" t#e &!oble'$ .#ysically( t#e bina!y signals o" t#e in&uts a!e

conside!ed bina!y digits to be added a!it#'etically to "o!' a t+o*digit su' at t#e

out&ut$ On t#e ot#e! #and( t#e sa'e bina!y alues a!e conside!ed as a!iables o"

Boolean "unctions +#en e&!essed in t#e t!ut# table o! +#en t#e ci!cuit is

i'&le'ented +it# logic gates$ T#e 'a&s "o! t#e out&ut o" t#e "ull adde! a!e s#o+n in

belo+$

HAL" ADDER:

LOGIC DIAGRAM:

TRUTH TABLE:

A B CARRY SUM

#

#

1

1

#

1

#

1

#

#

#

1

#

1

1

#

PROGRAM "OR HAL" ADDERJ

o43e a&a44e' 573Ka''2KaK=6

,%3t aK=

Page No: 87


63/74


64/74


TRUTH TABLE:

A B C CARRY SUM

#

#

#

#

1

1

1

1

#

#

1

1

#

#

1

1

#

1

#

1

#

1

#

1

#

#

#

1

#

1

1

1

#

1

1

#

1

#

#

1

PROGRAM "OR "ULL ADDER:

'odule "ulladde!


65/74


HAL" SUBTRACTOR:

LOGIC DIAGRAM:

TRUTH TABLE:

A B BORRO+ DI""ERENCE

##

1

1

#1

#

1

#1

#

#

#1

1

#

PROGRAM "OR HAL" SUBTRACTOR:

'odule #al"subt!acto!


66/74


in&ut a(b@

out&ut di""(bo!!o+@

o!


67/74


A B C BORRO+ DI""ERENCE

##

#

#

1

11

1

##

1

1

#

#1

1

#1

#

1

#

1#

1

#1

1

1

#

##

1

#1

1

#

1

##

1

PROGRAM "OR "ULL SUBTRACTOR:

'odule "ullsubt!acto!


68/74


O&en &!oect naigato!$

Go to t#e "ile and clic% t#e ne+ &!oect

Ty&e t#e &!oect na'e

T#e &!o&e!ty +iKa!dP is o&en to c#ec% all &!o&e!ties suc# as &!oduct(

catego!ies( "a'ily( deice etc$ t#en clic% net

C!eate ne+ sou!ce +iKa!d a&&ea!s t#en clic% net

.!oect su''a!y is dis&layed t#en clic% net

Go to t#e &!oect and clic% ne+ sou!ceP

T#en ty&e t#e 'odule na'e as +ell as select e!ilog 'odule t#en clic% net

De"ine 'odule +indo+P #e!e +e assign t#e in&ut and out&ut o" #al" adde!(

clic%s net and clic% "inis#

Ty&e t#e &!og!a' and sae it

-a%e su!e t#at t#e sou!ce is in BE;AMIOURAL SI-ULATIONP

T#en clic% t#e ISE si'ulato! and ie+ t#e signal +indo+

Fo!ce t#e in&ut data co!!es&onding ci!cuit

Si'ulate t#e &!og!a' using ISE si'ulato!

RESULT:

T#us t#e Me!ilog ;DL &!og!a' "o! adde! and subt!acto! a!e +!itten and

si'ulated using ISE si'ulato!$

Page No: 10


69/74


Ex. No: 1!

SIMULATION O" MULTIPLEXER AND DE-MULTIPLEXER

USING 0ERILOG HDLDate:

AIM:

To +!ite t#e Me!ilog ;DL &!og!a' "o! 'ulti&lee! and de*'ulti&lee! ci!cuit

and si'ulate it using ISE si'ulato!$

HARD+AREJ SO"T+ARE REQUIRED:

)ILIN9 :$0i Si'ulato!

.C IT; INDOS*).

THEORY:

MULTIPLEXER:

A digital 'ulti&lee! is a co'binational ci!cuit t#at selects bina!y in"o!'ation

"!o' one o" 'any in&ut lines and di!ects it to a single out&ut line$ T#e selection o" a

&a!ticula! in&ut line is cont!olled by a set o" selection lines$ No!'ally( t#e!e a!e 4Qn

in&uts lines and n selection lines +#ose bit co'binations dete!'ine +#ic# in&ut is

selected$

In a , to 0 line 'ulti&lee!( t#e "ou! in&ut lines( I2 to I5 is a&&lied to one in&uto" an AND gate$ Selection lines S0 and S2 a!e decoded to select a &a!ticula! AND

gate$ A 'ulti&lee! is also called a data selecto!( since it selects one o" 'any in&uts

and stee!s t#e bina!y in"o!'ation to t#e out&ut line$

DEMULTIPLEXER:

T#e de'ulti&lee! does t#e !ee!se o&e!ation o" a 'ulti&lee!$ It can be used

to se&a!ate t#e 'ulti&leed signal into indiidual signals( T#e select in&ut code

dete!'ines to +#ic# out&ut t#e data in&ut +ill be t!ans'itted$ T#e nu'be! o" out&ut

lines is n and t#e nu'be! o" select lines is '( +#e!e n4Q'$ T#e in&ut data is

t!ans'itted to one o" t#e out&ut di by 'eans o" select signals a(b$ T#e ,*bit adde!

adds t#e in&ut a b and &!oduces t#e ,*bit su' as t#e out&ut$

Page No: 14


70/74


LOGIC DIAGRAM "OR MULTIPLEXER:

TRUTH TABLE:

S1 S# Y ( OUTPUT

# # D#

# 1 D1

1 # D

1 1 D!

PROGRAM "OR MULTIPLEXER:

Page No: 15


71/74


'odule 'u

Page No: 1,


72/74


TRUTH TABLE:

INPUT OUTPUT

S1 S# IP D# D1 D D!

# # # # # # #

# # 1 1 # # #

# 1 # # # # #

# 1 1 # 1 # #

1 # # # # # #

1 # 1 # # 1 #

1 1 # # # # #1 1 1 # # # 1

PROGRAM "OR DE-MULTIPLEXER:

'odule de'u


73/74


out&ut d2(d0(d4(d5@

+i!e a0(b0@

not


74/74


Ty&e t#e &!oect na'e

T#e &!o&e!ty +iKa!dP is o&en to c#ec% all &!o&e!ties suc# as &!oduct(

catego!ies( "a'ily( deice etc$ t#en clic% net

C!eate ne+ sou!ce +iKa!d a&&ea!s t#en clic% net

.!oect su''a!y is dis&layed t#en clic% net

Go to t#e &!oect and clic% ne+ sou!ceP

T#en ty&e t#e 'odule na'e as +ell as select e!ilog 'odule t#en clic% net

De"ine 'odule +indo+P #e!e +e assign t#e in&ut and out&ut o" #al" adde!(

clic%s net and clic% "inis#

Ty&e t#e &!og!a' and sae it

-a%e su!e t#at t#e sou!ce is in BE;AMIOURAL SI-ULATIONP

T#en clic% t#e ISE si'ulato! and ie+ t#e signal +indo+

Fo!ce t#e in&ut data co!!es&onding ci!cuit

Si'ulate t#e &!og!a' using ISE si'ulato!

RESULT:

T# # M il ;DL " l i l d d l i l i

lab manual ic

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