Introduction to Sequential Logic Design

Flip-flops

Prev… Latches

S-R S-bar-R-bar S-R with enable signal D

FF vs. Latch

Latches and flip-flops(FFs) are the basic building blocks of sequential circuits.

latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs, independent of a clocking signal.

flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.

Edge triggered D Fli-Flop A D FF combines a pair of D latches.

Master/slave D FF

Positive-edge-triggered D FF Negative-edge-triggered D FF Edge-Triggered D FF with Enable Scan FF

Potive-Edge-triggered D flip-flop

Dynamic-input indicator

Edge-triggered D flip-flop behavior

D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK)

D FF with asynchronous inputs

Force the D FF to a particular state independent of the CLK and D inputs. PR (Preset) and CLR (Clear)

Negative-edge triggered D FF

Simply inverts the clock input. Active low.

Edge-triggered D FF with Enable

Scan flip-flops -- for testing

TE = 0 ==> normal operation TE = 1 ==> test operation

All of the flip-flops are hooked together in a daisy chain from external test input TI.

Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.

Scan FF

J-K flip-flops

Not used much anymore

T (toggle)flip-flops

A T FF changes state on every tick of the clock. (be toggled on every tick)

Q has precisely half the frequency of the T. Important for counters

Positive-edge-triggered T FF

T (toggle)flip-flops with enable

Summary D FF J-K FF T FF

Next… FSM analysis Read Ch-7.3

Happy Thanksgiving!