ch 8. sequential logic design practices
DESCRIPTION
1. Documentation standards ▶ general requirements : signal name , logic symbol , schematic logic - state machine layout : a collection of F/F & combination logic on same - flip-flops : type , function , clocking behavior - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/1.jpg)
Ch 8. Sequential logic design practices
1. Documentation standards
▶ general requirements : signal name , logic symbol , schematic logic
- state machine layout : a collection of F/F & combination logic on same- flip-flops : type , function , clocking behavior- state machine description : state table/diagram, transition list text files in
H/W description language (VHDL)- Cascaded elements.- timing diagrams- timing spec : max.clock freq , set-up & hold time
min. pulse width
![Page 2: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/2.jpg)
8.1.4 Timing Diagrams and Specification
setup time margin = tclk – tffpd(max) – tcomb(max) – tsetup
hold time margin = tffpd(min) + tcomb(min) + thold
![Page 3: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/3.jpg)
< Table 8 –1> Propagation delay in ns of selected CMOS flip-flops, registers , and latches
8.1.4 Timing Diagrams and Specification
![Page 4: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/4.jpg)
8.1.4 Timing Diagrams and Specification
![Page 5: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/5.jpg)
8.1.4 Timing Diagrams and Specification
![Page 6: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/6.jpg)
2. Latch & flip flops8.2.1 SSI Latches and flip flops
![Page 7: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/7.jpg)
8.2.2 Switch debouncing
![Page 8: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/8.jpg)
8.2.3 The Simplest Switch debounder
![Page 9: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/9.jpg)
8.2.3 The Simplest Switch debounder
![Page 10: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/10.jpg)
8.2.4 Bus Holder Circuit
Low & high -> floatingLow <-> highSource or sink a small amountof additional current through R
If pull-up resistor is too high, slow transitionIf pull-up resistor is too low, too much current
![Page 11: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/11.jpg)
8.2.5 Multiple Registers and Latches
![Page 12: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/12.jpg)
8.2.5 Multiple Registers and Latches
![Page 13: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/13.jpg)
8.2.5 Multiple Registers and Latches
![Page 14: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/14.jpg)
8.2.5 Multiple Registers and Latches
![Page 15: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/15.jpg)
8.2.5 Multiple Registers and Latches
![Page 16: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/16.jpg)
8.2.5 Multiple Registers and Latches
If EN_L = 1, Q <- QIf EN_L = 0, Q <- P
![Page 17: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/17.jpg)
8.2.6 Registers and Latches in ABEL and PLDs
Data1 in Rom is readData2 in a different device is read
![Page 18: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/18.jpg)
8.2.6 Registers and Latches in ABEL and PLDs
![Page 19: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/19.jpg)
8.2.6 Registers and Latches in ABEL and PLDs
![Page 20: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/20.jpg)
8.2.7 Registers and Latches in VHDL
![Page 21: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/21.jpg)
8.2.7 Registers and Latches in VHDL
< Figure 7-12 D latch >
![Page 22: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/22.jpg)
8.2.7 Registers and Latches in VHDL
- Inferred latch- The code doesn’t say what to do if C ≠ 1,- The compiler infers a latch to retain the value of Q
![Page 23: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/23.jpg)
8.2.7 Registers and Latches in VHDL
![Page 24: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/24.jpg)
8.2.7 Registers and Latches in VHDL
< Fig 8-3 >
![Page 25: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/25.jpg)
8.2.7 Registers and Latches in VHDL
D
CLKEN
Q
CLK
clear’
IQ
CLR’
CLK
CLKEN
OE’
16
![Page 26: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/26.jpg)
3. Sequential PLD8.3.1 Sequential GAL Devices
![Page 27: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/27.jpg)
8.3.1 Sequential GAL Devices
![Page 28: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/28.jpg)
8.3.1 Sequential GAL Devices
- No architecture control bits- More product terms 8-16 terms- Two more inputs
![Page 29: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/29.jpg)
8.3.1 Sequential GAL Devices
![Page 30: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/30.jpg)
8.3.1 Sequential GAL Devices
![Page 31: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/31.jpg)
8.3.2 PLD Timing Specification
ㆍ A series PLD (ex : PAL26L8A ): tPD = 25n , tCO =15n, tSU = 25 nsec
ㆍ Suffix : -5 , -7 , A, B,…
![Page 32: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/32.jpg)
8.3.2 PLD Timing Specification
ㆍ tPD : propagation delay from input to outputㆍ tCO : P-delay from rising edge of clock to outputㆍ tSU (set-up), tcf( = tCO ), tH ( hold) fmax : reliable max.freqㆍ external PLD : PLD output -> connect to input of another PLDㆍ internal PLD : same PLD
![Page 33: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/33.jpg)
4. Counters
state diagram = single cycles
![Page 34: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/34.jpg)
Ripple counter
ㆍ connect in series or cascaded f/fㆍ Carry : ripples from LSB to MSB one bit at a time ㆍ slow : n * tPTQ ( propagation delay of T f/f)
CLK : applied to LSB F/F only
8.4.1 Ripple Counters
![Page 35: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/35.jpg)
8.4.2 Synchronous Counters
![Page 36: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/36.jpg)
8.4.2 Synchronous Counters
![Page 37: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/37.jpg)
- MSI counter : Modulus N counter/divider i) Sync : ㆍ binary 4 bit counter ( 161,163 ) 161 : Async. clear function
163 : Sync. clear ( fully sync. counter ) ㆍ decade counter : 160, 162ex) modulo-10 counter wavefarm < Fig 31> ㆍ 4 bit up/down counter :SN74169(TTL), 74C169(CMOS), CD40169(CMOS)up/down decade counter : 192
ii ) Async : ㆍ 4 bit binary counter : 193 ㆍ 12 counter : 92 ㆍ decade counter : 90 ㆍ 4 bit up/down counter : 191 ㆍ decade up/down counter : 190
8.4.3 MSI Counters and Applications
![Page 38: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/38.jpg)
8.4.3 MSI Counters and Applications
![Page 39: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/39.jpg)
8.4.3 MSI Counters and Applications
![Page 40: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/40.jpg)
RCO = 1 when OA = OB = OC = OD = 1 & ENT = 1
8.4.3 MSI Counters and Applications
![Page 41: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/41.jpg)
8.4.3 MSI Counters and Applications
![Page 42: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/42.jpg)
8.4.3 MSI Counters and Applications
![Page 43: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/43.jpg)
8.4.3 MSI Counters and Applications
![Page 44: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/44.jpg)
8.4.3 MSI Counters and Applications
![Page 45: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/45.jpg)
8.4.3 MSI Counters and Applications
![Page 46: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/46.jpg)
8.4.3 MSI Counters and Applications
![Page 47: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/47.jpg)
8.4.3 MSI Counters and Applications
![Page 48: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/48.jpg)
8.4.6 Counters in VHDL
![Page 49: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/49.jpg)
8.4.6 Counters in VHDL
![Page 50: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/50.jpg)
8.4.6 Counters in VHDL
![Page 51: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/51.jpg)
8.4.6 Counters in VHDL
![Page 52: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/52.jpg)
8.4.6 Counters in VHDL
![Page 53: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/53.jpg)
5. Shift Register8.5.1 Shift Register Structure
![Page 54: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/54.jpg)
8.5.1 Shift Register Structure
![Page 55: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/55.jpg)
8.5.2 MSI Shift Register
![Page 56: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/56.jpg)
8.5.2 MSI Shift Register
![Page 57: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/57.jpg)
ㆍ 4 bit bidirectional parallel-in, parallel-out shift register
= universal shift register ( shift left & right, parallel & serial in-out combination )ㆍ left ( QD -> QA ) & right ( QA -> QD) Rin ( right – in ) & Lin ( left – in )
8.5.2 MSI Shift Register
![Page 58: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/58.jpg)
8.5.3 Shift Register Counters
![Page 59: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/59.jpg)
S1S0 = 10RESET = 1, 0001 load then RESET = Ø = SØ
8.5.3 Shift Register Counters
![Page 60: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/60.jpg)
8.5.3 Shift Register Counters
![Page 61: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/61.jpg)
8.5.4 Ring Counters
![Page 62: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/62.jpg)
If Q0, Q1, Q2=1, then Ø to LIN
If Q0, Q1, Q2=0, then 1 to LIN
8.5.4 Ring Counters
![Page 63: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/63.jpg)
8.5.4 Ring Counters
![Page 64: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/64.jpg)
If Q0, Q1, Q2=1, LIN = ØElse LIN = 1when RESET, 1110 load
8.5.4 Ring Counters
![Page 65: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/65.jpg)
RESET = Ø = CLR, Q3Q2Q1Q0 = 0000
If Q3 = Ø, LIN = 1If Q3 = 1, LIN = Ø
8.5.4 Ring Counters
![Page 66: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/66.jpg)
8.5.5 Johnson Counters
![Page 67: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/67.jpg)
D Q D Q D Q
CLK
•••Q
: Twisted ring counter 2n : 1 scalar Ex) if n=4, 8 states • Simple decoding logic Ex) 4 bit Johnson counter [ ref binary counter ]
8.5.5 Johnson Counters
![Page 68: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/68.jpg)
2n – 2n abnormal states
OXXO -> 0001Then LOAD 0001
N = 4, 24 – 2x4 = 8(abnormal states)
If Q3 = 0, LIN = 1If Q3 = 1, LIN = Ø
8.5.5 Johnson Counters
![Page 69: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/69.jpg)
8.5.6 Linear Feedback Shift Register Counters
![Page 70: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/70.jpg)
8.5.6 Linear Feedback Shift Register Counters
![Page 71: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/71.jpg)
8.5.6 Linear Feedback Shift Register Counters
![Page 72: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/72.jpg)
8.5.6 Linear Feedback Shift Register Counters
![Page 73: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/73.jpg)
8.5.7 Shift Register in ABEL and PLDs
![Page 74: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/74.jpg)
8.5.8 Ring Counter in ABEL and PLDs
![Page 75: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/75.jpg)
8.5.8 Ring Counter in ABEL and PLDs
![Page 76: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/76.jpg)
8.5.8 Shift Register in VHDL
![Page 77: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/77.jpg)
8.5.8 Shift Register in VHDL
![Page 78: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/78.jpg)
8.5.8 Shift Register in VHDL
![Page 79: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/79.jpg)
8.5.8 Shift Register in VHDL
![Page 80: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/80.jpg)
8.5.8 Shift Register in VHDL
![Page 81: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/81.jpg)
6. Iterative versus Sequential Circuits
![Page 82: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/82.jpg)
If X = Y, A = 1, EQI = 1, -> then EQO = 1If X ≠ Y, A = 0, EQI = 1, -> then EQO = Ø
![Page 83: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/83.jpg)
![Page 84: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/84.jpg)
RESET_L = Ø EQO = 1, next clock EQI = 1
![Page 85: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/85.jpg)
![Page 86: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/86.jpg)
design goal for the digital systems ⅰ) function as required ⅱ) high reliable & easy maintenance ⅲ) cost effective design factor for the reliable digital systems • clock skew & gating the clock • static , dynamic , function hazards
7. Synchronous Design Methodology
![Page 87: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/87.jpg)
8.7.1 Synchronous System Structure
![Page 88: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/88.jpg)
8.7.1 Synchronous System Structure
![Page 89: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/89.jpg)
▶ design factor for reliable digital systems ⅰ) clock skew ⅱ) gating the clock 1) clock skew difference between arrival times (of a clock at different devices) - for proper operation tffpd(min) + tcomg(min) - thold – tskew(max) > 0 if hold time margin > clock skew, then system → OK
8. Impediments to Synchronous Design
![Page 90: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/90.jpg)
8.8.1 Clock Skew
![Page 91: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/91.jpg)
8.8.1 Clock Skew
![Page 92: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/92.jpg)
8.8.1 Clock Skew
![Page 93: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/93.jpg)
8.8.1 Clock Skew
![Page 94: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/94.jpg)
8.8.2 Gating the Clock
![Page 95: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/95.jpg)
If CLKEN = Ø, GCLK = 1 (not ticking)If CLKEN = 1, GCLK = Clock_L = Clock
8.8.2 Gating the Clock
![Page 96: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/96.jpg)
8.8.3 Asynchronous Inputs
![Page 97: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/97.jpg)
8.8.3 Asynchronous Inputs
![Page 98: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/98.jpg)
8.8.3 Asynchronous Inputs
![Page 99: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/99.jpg)
8.8.3 Asynchronous Inputs
![Page 100: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/100.jpg)
▶ metastable : Set-up & hold time → violation (not meet) ▶ Synchronizer failure - if system → use synchronizer output, while output → metastable output solution ⅰ) min. pulse width , set-up time ⅱ) wait “ long enough” until f/f → come out of metastable ▶ metastability resolution time : tr
tr = tclk – tcomb – tsetup ▶ reliable synchronous design ⅰ) wait “long enough” → slow down ⅱ) for speed up use
9. Synchronizer Failure and Metastability
![Page 101: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/101.jpg)
8.9.1 Synchronizer Failure
![Page 102: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/102.jpg)
8.9.3 Reliable Synchronizer Design
![Page 103: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/103.jpg)
8.9.3 Reliable Synchronizer Design
![Page 104: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/104.jpg)
8.9.5 Better Synchronizers
![Page 105: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/105.jpg)
8.9.5 Better Synchronizers
![Page 106: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/106.jpg)
8.9.6 Other Synchronizer Designs
![Page 107: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/107.jpg)
8.9.6 Other Synchronizer Designs
![Page 108: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/108.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 109: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/109.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 110: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/110.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 111: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/111.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 112: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/112.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 113: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/113.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 114: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/114.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 115: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/115.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 116: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/116.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 117: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/117.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 118: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/118.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 119: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/119.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 120: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/120.jpg)
8.9.7 Synchronizing High-Speed Data Transfers
![Page 121: Ch 8. Sequential logic design practices](https://reader038.vdocuments.us/reader038/viewer/2022102612/568165b5550346895dd8b1b8/html5/thumbnails/121.jpg)
8.9.7 Synchronizing High-Speed Data Transfers