implementation of intelligent data acquisition system for iter fast controllers using rio devices
DESCRIPTION
Implementation of intelligent data acquisition system for ITER fast controllers using RIO devices. M. Ruiz, D.Sanz , R. Castro, J.M. López , J. Vega, E. Barrera Universidad Politécnica de Madrid Asociación Euratom /CIEMAT. Outline. Motivation and objective. - PowerPoint PPT PresentationTRANSCRIPT
Page 17th Workshop on Fusion Data Processing Validation and Analysis
Implementation of intelligent data acquisition system for ITER fastcontrollers using RIO devices
M. Ruiz, D.Sanz, R. Castro, J.M. López, J. Vega, E. Barrera
Universidad Politécnica de MadridAsociación Euratom/CIEMAT
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Outline
• Motivation and objective.• ITER Fast Controllers:
– HW elements.– SW elements.
• Methodology.• Conclusions.
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Motivation and Objective
• Implement “data analysis” as close as possible to the Data Acquisition Hardware-> Intelligent DAQ
• Traditional approach-> To Use host CPU to implement data analysis.
• New approaches-> To use FPGA in the DAQ device– Advantages:
• DAQ functionalities are defined by the user.• Data analysis is implemented in the FPGA, therefore DAQ
provide features of the signals acquired.• Simple control loops can be implemented in the FPGA
Hardware. Therefore, we have deterministic applications.– Disadvantages:
• No floating point available but you can use “fixed point” algorithms.
• You need to program the FPGA with their specific tools. This is difficult in general!!!
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Some interesting points to discuss!!!
• Data analysis applications are infinite and the implementation possibilities too.
– We need some kind of standardization methods. We have developed a methodology based in the use of reconfigurable input/output (RIO) devices .
• There are a lot of hardware platforms available to implement these applications.
– We have selected PCIe based solutions in PXIe form factor.• There are a lot software environment to integrate the
solutions.– We have selected EPICs to provide compliant solutions to
ITER CODAC.
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Plant System Instrumentation and Control model defined by ITER-CODAC
Plant System
Host
Fast Controller
COTSIntelligent
Device
Actuators and Sensors
Mini-CODAC
Fast Controller
Slow Controller
Slow Controller
Plant System I&C
Signal Interface
Remote I/O
Plant Operation Network (PON)
Plant Operation Network (PON)
Remote I/O
Signal Interface
InterlockController
Signal Interface
Central Interlock System
Central Interlock Network (CIN)
Time Communication Network (TCN)
Audio/video Network (AVN)
Synchronous Data Network (SDN)
High Performance Networks (HPN) CODAC Terminal
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Fast controller cubicle
CPU/Network/DisksPXIe chassisPCIe to PXIe link
TCN & Timing card
DAQ device
Connectors
PXI
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Fast Controller Hardware Elements
Ethernet PON
PXIe chassis
PCIe
PICMG 1.3Industrial Computer
PXI6259Multifunction DAQ
RIOFPGA based DAQ- device
NI-PXI6682-1588
TCN
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EPICS software architecture
Plant System
Host
Fast Controller
COTSIntelligent
Device
Actuators and Sensors
Mini-CODACCodac Core
System
Slow Controller
Slow Controller
Plant System I&C
Signal Interface
Remote I/O
Plant Operation Network (PON)
Plant Operation Network (PON)
Signal Interface
InterlockController
Signal Interface
Central Interlock System
Central Interlock Network (CIN)
Time Communication Network (TCN)
Audio/video Network (AVN)
Synchronous Data Network (SDN)
High Performance Networks (HPN) CODAC Terminal
EPICSIOC
Channel Access
The IOC allow to interchange the information between the hardware and the network using a standard protocol
(channel access)“IOCs are created
automatically using ITER CODAC tools”
CODAC CORE SYSTEM
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EPICS IOC
Sequencer
LAN
Asyn Device Support
I /O Hardware
Database
Channel Access
ASYN MODULE
EPICs IOC
PCIe
Standard interface
Process Variables (PVs)
The ASYN software module includes the code supporting a specific hardwareITER is developing “ASYN modules for different hardware elements”
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Intelligent DAQ devices
LAN
I /O Hardware
EPICSIOC
ASYN MODULEPCIe
The ASYN module includes the code supporting a specific
hardware
The FPGA contains a specific application
implementing DAQ and preprocessing
DATA ANALYSIS is implemented in the hardware in this FPGA
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What are the contributions of this work?
• Implementation of the NIRIO EPICS device support to connect the FPGA resources with ITER CODAC CORE SYSTEM applications.
– The implementation of a device support following ASYN methodology in EPICS is not easy. If we are going to implemented multiple solutions in the FPGA, for instance
• data analysis• data processing• spectral estimation.• data reduction• Compression• pattern recognition• Filtering• image processing, etcwe cannot implement specific device support for each application. We need a <<standard>> device support.
– We have created a set of rules to standardize this and we have built this general purpose “device support” for RIO devices.
– The rules must be taken into account in the implementation of the FPGA code.
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What is the contribution of this work?
• Implementation of the FPGA code supporting data acquisition and preprocessing for your specific application
– We have simplified the process using LabVIEW for FPGA• We have created LabVIEW code patterns for
oContinuous data acquisition + processing single sample oriented
oContinuous data acquisition + processing waveform (block) oriented
o Single event data acquisition + processingo Images data acquisition using camera-link interface.oCustomized triggerso IEEE 1588 time-stamping for samples and blocks (using the
PXI-6682)oWaveform (pattern) generation (periodic signals)oDigital input-output.
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What is the contribution of this work?
• Implement the interface for EPICS to integrate your solution in ITER CODAC CORE SYSTEM.
– NIRIO EPICS ASYN Device Support implemented– The device support searches for the resources available in
the FPGA design– The device support automatically connects FPGA resources
and EPICS records.
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FPGA code implementation using “coreDAQ” pattern (block oriented)
SamplingRate0
ADC Ch[0-N]
GroupEnable0
SamplingRate0
DMA PCI/PCIe to CPU
DAQStartStop
FIFO0
DMATtoHOST0
GroupEnable0
DAQStartStop
Controls
HOST (DMA)
InitDone
Hardware Logic
Indicators
NCHperDMATtoHOST
DevQualityStatus
DeviceTemp
DMAsOverflow
Fref
FPGAVIversion
NoOfWFGen
ExpexctedIOModuleID
RIOAdapterCorrect
DATAPROCESSING
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Development cycle using CODAC CORE SYSTEM
SDDPlant System I&C developer
SDD Developer
New data base for RIO in Fast Controllers
CORE DAQ Design Rules
List of the maximumnumbers elements of each RIO device-AI,AO,DI,DO, etc
Scientistrequirements
++ = projectname.lvbitx
projectname.h
SDD Editor
SDD translator
CORE DAQ Design Rules
m-nirioThis package
is installed like an EPICS
Module in CCS
m-myUnit
src
main
epics
IOC unit
resources
nirio
bitfile
headerfile
1
5
2
3
4
List of the maximum numbers elements
of each RIO device-AI,AO,DI,DO, etc
Plant System I&C developer
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Steps for implementing “intelligent data acquisition applications
• Select one RIO device and an adapter module• Develop the FPGA code using LabVIEW for
FPGA – Test the application!!– The output is a bitfile for programming the FPGA
• Download of resource files to the Fast Controller Host
• Create and IOC following ITER Codac Core System Application Manual
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Some results obtained
• Continuous data acquisition moving the data to EPICS:
– Up to 6MS/s using 2 analog input channel (16 bits) in PXI (PCI) modules (24 MB/s)
– Up to 2MS/s using 32 analog input channel (16 bits) in PXIe (PCIe) modules (200MB/s)
• Single triggered data acquisition– Up to 100MS/s using 2 channels.
• Data Analysis and Pattern Recognition– Real Time Plasma Disruptions Detection in JET Implemented
With the ITMS Platform Using FPGA Based IDAQ (IEEE TNS Volume: 58 Issue:4 pp: 1576 - 1581 )
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Conclusions
• The methodology for integrating data analysis applications in RIO devices has been developed.
• The methodology solves the integration of these applications in ITER fast controllers using EPICS and CODAC CORE SYSTEM tools.
• The FPGA processing capabilities are limited (if we compare them with CPUs or GPUs) therefore new methods like “peer to peer comunications” among FPGAs should be explored
Page 197th Workshop on Fusion Data Processing Validation and Analysis
Implementation of intelligent data acquisition system for ITER fastcontrollers using RIO devices
M. Ruiz, D.Sanz, R. Castro, J.M. López, J. Vega, E. Barrera
Universidad Politécnica de MadridAsociación Euratom/CIEMAT