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HDL-Based Digital DesignPart I: Introduction to VHDL (I)

Dr. Yingtao JiangDr. Yingtao Jiang

Department Electrical and Computer EngineeringDepartment Electrical and Computer EngineeringUniversity of Nevada Las VegasUniversity of Nevada Las Vegas

Summer 2005Summer 2005

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What is VHDL?What is VHDL?VHDL: VHSIC Hardware Description Language

VHSIC: Very High Speed Integrated Circuit

Developed originally by DARPADeveloped originally by DARPA for specifying digital systemsfor specifying digital systems

International IEEE standard (IEEE 1076International IEEE standard (IEEE 1076--1993)1993)

Hardware Description, Simulation, SynthesisHardware Description, Simulation, Synthesis

Practical benefits:

a mechanism for digital design and reusable design documentationa mechanism for digital design and reusable design documentation

Model interoperability among vendors

Third party vendor support

Design re-use.

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VHDL vs. C/PascalVHDL vs. C/PascalC/Pascal:

Procedural programming languages

Typically describe procedures for computing a mathsfunction or manipulation of data (e.g., sorting, matrix

computing)

A program is a recipe or a sequence of steps for how to

perform a computation or manipulate data.VHDL:

a language to describe digital systems.

Purposes: simulation and synthesis of digital systems.

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Lets Start SimpleLets Start SimpleSupport different description levelsSupport different description levels

Structural (specifying interconnections of the gates),Structural (specifying interconnections of the gates),

Dataflow (specifying logic equations), andDataflow (specifying logic equations), and

Behavioral (specifying behavior)Behavioral (specifying behavior)

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Domains and Levels ofDomains and Levels of

ModelingModeling

high level of

abstraction

FunctionalStructural

GeometricY-chart due to

Gajski & Kahn

low level of

abstraction

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Domains and Levels ofDomains and Levels of

ModelingModeling FunctionalStructural

GeometricY-chart due to

Gajski & Kahn

Algorithm

(behavioral)

Register-TransferLanguage

Boolean Equation

Differential Equation

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Domains and Levels ofDomains and Levels of

ModelingModeling FunctionalStructural

Geometric Y-chart due toGajski & Kahn

Processor-Memory

Switch

Register-Transfer

Gate

Transistor

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Domains and Levels ofDomains and Levels of

ModelingModeling FunctionalStructural

Geometric Y-chart due toGajski & Kahn

Polygons

Sticks

Standard Cells

FloorPlan

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VHDL Description ofVHDL Description of

Combinational NetworksCombinational Networks

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EntityEntity--Architecture PairArchitecture Pair

entity name port names port mode (direction)

port type

reserved words

punctuation

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VHDL Program StructureVHDL Program Structure

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44--bit Adder (contd)bit Adder (contd)

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Modeling FlipModeling Flip--Flops UsingFlops Using

VHDL ProcessesVHDL Processes

Whenever one of the signals in theWhenever one of the signals in thesensitivity list changes, the sequentialsensitivity list changes, the sequentialstatements are executedstatements are executedin sequence one timein sequence one time

General form of process

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D FlipD Flip--flop Modelflop Model

Bit values are enclosed

in single quotes

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JK FlipJK Flip--Flop ModelFlop Model

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Using Nested IFs andUsing Nested IFs and

ELSEIFsELSEIFs

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VHDL Models for a MUX

Sel represents the integerequivalent of a 2-bit binary

number with bits A and B

If a MUX model is used inside a process,

the MUX can be modeled using a CASE statement

(cannot use a concurrent statement):

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MUX Models (1)MUX Models (1)

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity SELECTOR is

port (A : in std_logic_vector(15 downto 0);

SEL : in std_logic_vector( 3 downto 0);

Y : out std_logic);

end SELECTOR;

architecture RTL1 ofSELECTOR is

begin

p0 : process (A, SEL)

begin

if (SEL = "0000") then Y

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MUX Models (2)MUX Models (2)

architecture RTL3 of SELECTOR is

begin

with SEL select

Y

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MUX Models (3)architecture RTL2 of SELECTOR is

begin

p1 : process (A, SEL)

begin

case SEL is

when "0000" => Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y

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MUX Models (4)

architecture RTL4 of SELECTOR is

begin

Y

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Compilation and

Simulation of VHDL CodeCompiler (Analyzer)Compiler (Analyzer) checks the VHDL source codechecks the VHDL source code does it conforms with VHDL syntax and semantic rulesdoes it conforms with VHDL syntax and semantic rules

are references to libraries correctare references to libraries correct

Intermediate form used by a simulator or by a synthesizerIntermediate form used by a simulator or by a synthesizer

ElaborationElaboration create ports, allocate memory storage, create interconnections, ...create ports, allocate memory storage, create interconnections, ...

establish mechanism for executing of VHDL processesestablish mechanism for executing of VHDL processes

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Timing ModelTiming ModelVHDL uses the following simulation cycle tomodel the stimulus and response nature ofdigital hardware

Delay

Start Simulation

Update Signals Execute Processes

End Simulation

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Delay TypesDelay TypesAll VHDL signal assignment statementsAll VHDL signal assignment statementsprescribe an amount of time that mustprescribe an amount of time that musttranspire before the signal assumes its newtranspire before the signal assumes its newvaluevalue

This prescribed delay can be in one of threeThis prescribed delay can be in one of threeforms:forms:

TransportTransport ---- prescribes propagation delay onlyprescribes propagation delay only

InertialInertial ---- prescribes propagation delay and minimumprescribes propagation delay and minimuminput pulse widthinput pulse width

DeltaDelta ---- the default if no delay time is explicitlythe default if no delay time is explicitlyspecifiedspecified

Input

delayOutput

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Transport Delay

Transport delay must be explicitly specified I.e. keyword TRANSPORT must be used

Signal will assume its new value after specified delay

Input Output

0 5 10 15 20 25 30 35

Input

Output

-- TRANSPORT delay example

Output

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Inertial DelayProvides for specification propagation delay and inputpulse width, i.e. inertia of output:

Inertial delay is default and REJECT is optional:

Input

Output

0 5 10 15 20 25 30 35

Input Output

target

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Inertial Delay (cont.)Example of gate with inertia smaller than propagationdelay

e.g. Inverter with propagation delay of 10ns whichsuppresses pulses shorter than 5ns

Note: the REJECT feature is new to VHDL 1076-1993

Input

utput

0 5 10 15 20 25 30 35

Output

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Delta DelayDefault signal assignment propagation delay if noDefault signal assignment propagation delay if nodelay is explicitly prescribeddelay is explicitly prescribed

VHDL signal assignments do not take place immediatelyVHDL signal assignments do not take place immediately

Delta is an infinitesimal VHDL time unit so that all signalDelta is an infinitesimal VHDL time unit so that all signal

assignments can result in signals assuming their values at aassignments can result in signals assuming their values at a

future timefuture time

E.g.E.g.

Supports a model of concurrent VHDL processSupports a model of concurrent VHDL processexecutionexecution

Order in which processes are executed by simulator does notOrder in which processes are executed by simulator does not

affect simulation outputaffect simulation output

Output

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Simulation Example

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Problem #1Using the labels, list

the order in which the

following signal

assignments are

evaluated if in2

changes from a '0' to a'1'. Assume in1 has

been a '1' and in2 has

been a '0' for a long

time, and then at time

t

in2 changes from a'0' to a '1'.

entity not_another_prob is

port (in1, in2: in bit;

a: out bit);

end not_another_prob;

architecture oh_behave of not_another_prob is

signal b, c, d, e, f: bit;

begin

L1: d

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Problem #2Under what conditions do the two assignments belowUnder what conditions do the two assignments below

result in the same behavior? Different behavior? Drawresult in the same behavior? Different behavior? Draw

waveforms to support your answers.waveforms to support your answers.

out

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Modeling a Sequential

MachineMealy Machine for8421 BCD to 8421 BCD + 3 bit serial converter

How to model this in VHDL?

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Behavioral VHDL ModelBehavioral VHDL Model

Two processes:

the first represents the combinational network;

the second represents the state register

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Simulation of the VHDL

ModelSimulation command file:

Waveforms:

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Dataflow VHDL Model

33

21313213

12

21

''

''''')()(

)(

XQQXZ

QQXQQXQQQtQQtQ

QtQ

!

!

!

!

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Structural Model

Package bit_pack is a part of library

BITLIB

includes gates, flip-flops, counters

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Simulation of the StructuralSimulation of the Structural

ModelModelSimulation command file:

Waveforms:

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Wait Statements... an alternative to a sensitivity list... an alternative to a sensitivity list

Note: a process cannot have both wait statement(s)Note: a process cannot have both wait statement(s)and a sensitivity listand a sensitivity list

Generic form of a process with wait statement(s)Generic form of a process with wait statement(s)

process

begin

sequential-statements

wait statement

sequential-statements

wait-statement

...

end process;

How wait statements work? Execute seq. statement until

a wait statement is encountered.

Wait until the specified condition is satisfied.

Then execute the next

set of sequential statements until

the next wait statement is encountered. ...

When the end of the process is reached start

over again at the beginning.

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Forms of Wait StatementsForms of Wait Statements

Wait on

until one of the signalsin the sensitivity listchanges

Wait for

waits until the timespecified by the timeexpression haselapsed

What is this:wait for 0 ns;

Wait until

the Boolean expression isevaluated whenever oneof the signals in theexpression changes, andthe process continues

execution when t

heexpression evaluates to

TRUE

wait on sensitivity-list;

wait for time-expression;

wait until boolean-expression;

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Using Wait Statements (1)

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Using Wait Statements (2)