fyse420 digital electronics lecture 7users.jyu.fi/~loberg/fyse420slides/fyse420lecture7.pdf ·...

FYSE420 DIGITAL ELECTRONICS

Lecture 7Lecture 7

1

DIGITAL LOGIC

CIRCUIT ANALYSIS

& DESIGNNelson, Nagle, Irvin, Carrol

ISBN 0-13-463894-8

DIGITAL DESIGNMorris Mano

[1]

[2]Morris Mano

Fourth edition

ISBN 0-13-198924-3

Digital DesignPrinciples and Practices

Fourth edition

Wakerly John F.

ISBN 0-13-186389-4

[3]

2

Implementation Strategies for Digital ICs

Introduction

A high complexity of integrated circuits poses an enormous design challenge.

Computer aided design The rate of technology advancement depends on the

absorption bandwidth of the design community

Well-established design

methodologies

The rate of the IC-manufacturing

development

The IC-complexity is growing

faster than the productivity

“Design gap”

3

The correct operation of the

designed circuit.

The productivity of the design teams

©Loberg

108

109

1010

0.1µµµµ

Complexity

Logic transis-

tors per chip

Productivity

Trans./Staff-month

106

107

108

Complexity

Introduction


1981 1985 1989 1993 1997 2001 2005 2009

104

105

106

107

10

0.35µµµµ

1032.5µµµµ

101

102

103

104

105

10

Productivity

Design productivity gap

4©Loberg

Digital Circuit Implementation Approaches

Custom Semicustom

Array basedCell based

Introduction


Standard cells

Compiled cellsMacro cells Prediffused

(Gate arrays)

Pre-wired

(FPGA’s , ..)

Array basedCell based

The preferred approach to mapping a function onto silicon

depends largely upon the function itself.

Pre-wired arrays

5©Loberg

Prewired Arrays

By using the prewired arrays the

IC manufacturing time can be

reduced to zero in

“desk to market” time.

The prewired array of cells is

Introduction

Pre-diffused

Cell based

The logical design of digital system

The manufacturing of IC

Th

e ti

me

fro

m d

esk

to m

arke

t

Unprogrammed

FPGAs from IC

vendor


The prewired array of cells is

called a field-programmable

gate array , FPGA

The implementation can be

performed at the user site

with negligible turnaround

time.Semicustom

Pre-diffused

Th

e ti

me

fro

m d

esk

to m

arke

t

vendor

Pre-wired

FPGA

6©Loberg

Fuse-based FPGA

Fuse based

Antifuse based

The nonvolatile FPGA

EEPROM (Electrically

Erasable Programmable

Read-Only Memory)

The volatile FPGA

RAM-based FPGA

FPGA do not have spe-

(OTP)

Introduction Prewired Arrays


Short-circuited

by default

Open-circuited

by default

Flash memory

FPGA do not have spe-

cial manufacturing pro-

cess requirements (regu-

lar CMOS process).

7©Loberg

Introduction

Fuse-based FPGA

Advantage

Memory cell is very small

Resistance of the short-circuited fuse is low

Fuse based


Prewired Arrays

Resistance of the short-circuited fuse is low

Disadvantage

One-time programmable

Reliable simulation

A new component is required for every

design change

8©Loberg

A thin layer (<10nm) of ONO (oxide-nitride-oxide) dielectric is

deposited between conducting polysilicon and diffusion layers.

The circuit is open by default.

Fuse-based FPGA

Introduction

Antifuse based

Large programming current through it.


Prewired Arrays

ONO dielectricLarge programming current through it.

The current causes the dielectric

to melt

A permanent connection with fixed

resistance (about 300ΩΩΩΩ).

9

Antifuse polysilicon

n+ antifuse diffusion

©Loberg

SiO2

MetalVia

In an amorphous-silicon based FPGA, the two layers of metal

are separated by amorphous silicon, which provides electrical

insulation.

Fuse-based FPGA

Antifuse based

Introduction


Prewired Arrays

Link

Amorphous-silicon

antifuse element

A programming pulse of 10V to 12V across

the via

Conductive link with a resistance

of about 50ΩΩΩΩ.

10©Loberg

Advantage

Once programmed, the logic remains functional and fixed until new

programming round.

Memory retains its value even when the supply voltage is turned off.

The nonvolatile FPGA

Introduction


Prewired Arrays

Disadvantage

Disadvantage of this approach is that nonvolatile memories require

special steps in the

manufacturing process.

High programming/erasure voltage (>10V)

11©Loberg

Ram-Based FPGA

Advantage

FPGA do not have special manufacturing process requirements

(regular CMOS process).

Logic can be modified on the fly.

The volatile FPGA

Introduction


Prewired Arrays

Disadvantage

The reloading of the configuration from an external permanent memory is

necessary every time the part is turned on.

The size of the memory cells with pass transistors is large.

The resistance of the interconnection switch is high (about 1000ΩΩΩΩ).

12©Loberg

Programming bit

Select

The volatile FPGA

Introduction


Prewired Arrays

Ram-Based FPGA

Interconnect switch

SRAM cell

13©Loberg

The volatile FPGA

The six SRAM controlled pass transistors

Introduction


Prewired Arrays

Ram-Based FPGA

SRAM cellN

14

EW

S

©Loberg

Programmable Logic* Array-Based Programmable Logic

* Cell-Based Programmable Logic

A complex circuit implementation

Introduction


Prewired Arrays

Programmable Interconnection* Array-Based Programmable Wiring

* Switch-Box-Based Programmable Wiring

15©Loberg

Array-Based Programmable Logic

I5 I 4 I3 I2 I 1 I0 ProgrammableOR array

Programmable logic array (PLA)

AND and OR planes can be programmed by

selectively enabling connections.

Introduction


Prewired Arrays

O0O1O2O3

Programmable AND array

AND plane Required minterms

OR plane The set of selected minterms

Sum-of-product format (SOP).

16©Loberg

I3 I2 I1 I0 ProgrammableOR array

In PROM architecture the AND plane is fixed

and enumerates all possible minterms.

Spend die area

PROM architecture


Introduction


Prewired Arrays

O0O1O2O3

Fixed AND array

17©Loberg

I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable array logic (PAL)

OR plane is fixed and the AND plane is

programmable.

Note!


Introduction


Prewired Arrays

O0O1O2O3

Programmable AND array

Programmable logic devices PLDs : PLA, PROM, PAL

To realize the complete, sequential subdesigns, the

presence of registers and/or flip-flops is an absolute

requirement.

Note!

18©Loberg

programmable AND array (2 i 3 jk ) k macrocells

j -wide OR array

productterms

D Q

1

2i x jk


Introduction


Prewired Arrays

Partition the array into a number of smaller sections : macrocells

introduce flip-flops and provide a potential feedback from output to the inputs.

j

macrocell

D Q

A

j

B

CLK

OUT

C i i inputs PALA single register in macrocell can be programmed also : D, T, JK,

or clocked SR flip-flop

19©Loberg

The PLA approach has two distinct advantages:

Structure is very regular.

Estimation of the parasitics is quite easy.

Accurate predictions of area, speed, and power dissipation.

Efficient implementation of two-level logic description (functions with large fan-in).

For example finite-state machines used in controllers and sequencers.


Introduction


Prewired Arrays

For example finite-state machines used in controllers and sequencers.

Disadvantages:

High overhead.

Every intermediate node has sizable capacitance (lower performance

and higher power dissipation).

These are true especially when parts of array are underutilized (only some of

the minterms are only used).

20©Loberg

Array-based programmable logicSmall logic block that can be configured to

perform a wide range of logic functions.

Cell-Based Programmable Logic

Introduction


Prewired Arrays

Logic functions with large fan-out. Multilevel logic implementation such as addition and

multiplication.

Fits poorly in the multilevel logic.Fits better in the multilevel logic.

21©Loberg

0A

F

F = AS + BS

Configuration

A B S F=

0 0 0 00 X 1 X

Introduction



Prewired Arrays

The multiplexer as a function generator

1

S

B

F 0 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X + Y1 0 X1 0 Y1 1 1 1

XYXY

XY

22©Loberg

A

B

SA Y

1

1

The logic cell of Actel ACT family of FPGAs

consists of three two-input multiplexers and

two-input NOR gate.

Any two- or three input logic function,

some four-input Boolean functions,

Introduction



Prewired Arrays

C

D

SB

1

S0S1

1

Logic Cell of Actel Fuse-Based FPGA

some four-input Boolean functions,

and a latch.

23©Loberg

Introduction


In Out

Lookup table method


Prewired Arrays

Out

ln1 ln2

Memory

00 0

01 1

10 1

11 0

Lookup table LUT

24©Loberg

4

G4

C1....C4

G3

G2

Logicfunction

ofF1-F4

xx

H1

xxxxxx

xxxx xxxx xxxx

S/Rcontrol

D QSD YQ

xxxx

Xilinx 4000 Series

Introduction



Prewired Arrays

K(clock)

2

G1

F4

F3

F2

F1

F1-F4

Logicfunction

ofxxx

Logicfunction

ofF1-F4

xxxxxxxx

xxx

HP

S/Rcontrol

Multiplexer Controlledby Configuration Program

Y1

1

EC

x

XQ

xxxx

RD

D

EC

QSD

RD

LUT-based logic cell of the XILINX XC4000 series.

25©Loberg

The interconnect network must be flexible and routing bottlenecks must be avoided.

Short interconnection delays.

Requirements

High performance Good question !

Introduction

Programmable Interconnect


Prewired Arrays

High performance

Low power consumption.

Good question !

How to get these features ?

One-time programmable Reprogrammable

Fuse and antifuse SRAM, EEPROM

26©Loberg

Input/output pinProgrammed interconnection

Cell

Array-Based Programmable Wiring

Introduction



Prewired Arrays

tracks

Vertical tracks

Pass transistor

M

27©Loberg

Switch-Box-Based Programmable Wiring

Programmable mesh-

based interconnect

network.

Switch Box

Introduction



Prewired Arrays

Connect Box

Interconnect

Point

28©Loberg

Introduction



Mesh-based interconnec-

tion network is quite

efficient for local connec-

tions, but unefficient for

global interconnections.

Transistor-level schematic diagram.


Prewired Arrays

* Delay

* Large capacitive load

29©Loberg

Wire with

doubled pitch

We can include long wires that

connect every second, 4th, 8th,

or 16th switch matrix (S-box).

Introduction




Prewired Arrays

* Decreased interconnection

resistance.

* Shorter delay.

30©Loberg

Altera QuicklogicActel Xilinx

FPGA:

*Stratix

*Cyclone

*Stratix GX

*APEX II

Reprogrammable

Flash FPGAs:

*ProASICplus

*ProASIC

Antifuse Devices:

FPGA:

*VirtexIIIPro

*VirtexII

*VirtexE

*Virtex

FPGA:

*Eclipse

*Eclipse-II

*pASIC

*pASIC 1

Introduction


Prewired Arrays

*APEX II

*APEX 20K

*Mercury

*FLEX 10K

*ACEX 1K

*FLEX 6000

CPLD:

*MAX 3000A

*MAX 7000

Antifuse Devices:

*Axcelerator

*SX-A / SX

*eX

*MX

*Virtex

*Spartan 3

*SpartanIIE

*SpartanII

*SpartanXL

*Spartan

CPLD:

*CoolRunner

*XC9500 family

*pASIC 1

*pASIC 2

*pASIC 3

*QuickRAM

31©Loberg

The EndThe End

32©Loberg

fyse420 digital electronics lecture 7users.jyu.fi/~loberg/fyse420slides/fyse420lecture7.pdf ·...

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