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Introduction to Sequential Circuits Models of Digital Circuits
©Loberg
Combinational Logic :
Sequential Logic :
Output states of Combinational Logic depends only on the current states of input variables.
Next Output state (n+1) of Sequential Logic depends on the current state of input variables and current output state (n).
We need a Memory element for old (previous) state.
Latch Flip-Flop Delay
If memory element is clocked, then circuit is synchrous, if not, circuit is asynchronous.
Output state
Inputs Current
Next
Clock
Current state
n n+1 n+2
1
Combinational Logic
n input variables m output variables
Introduction to Sequential Circuits
©Loberg
Models of Digital Circuits
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Y1 Y2
Yk
y1
y2
yk
x1 x2
xn
z2
z1
zm
m output variables n input variables
k secondary variables k exitation variables (next state) (present state)
Combinational circuit
Memory
Memory
Memory
Model for sequential logic
Clock
used/not used
depends on applications
Introduction to Sequential Circuits
©Loberg
Models of Digital Circuits
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Synchronous sequential logic Asynchronous sequential logic
The change of internal state occurs in response to the clock pulses.
The change of internal state occurs when there is change in the input variables.
Memory element : clocked, (gated) Memory element : unclocked or time-delay elements.
INPUT
OUT A
OUT B
INPUT
OUT A
OUT B
CLK
Introduction to Sequential Circuits
©Loberg
Models of Digital Circuits
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Synchronous sequential logic Asynchronous sequential logic
Properly designed system
"No timing problems"
The design of asynchronous sequential circuits is difficult
No clocked flip-flops
Timing problems
Feedback bath
Used when speed of operation is important
Fast response to the change of input variable
Redused logic and power dissipation
No clock distribution
Synchronous or asynchronous ?
Introduction to Sequential Circuits
©Loberg 5
To ensure proper operation, circuits must be allowed to attain a stable state before the input is changed to a new value.
Because of delays in the wires and the gate circuits it is "impossible" to say which variable changes its state first when two or more input variables change at "exactly same instant time".
Fundamental mode
Input signals change one at a time and only when the circuit is in the stable state.
Models of Digital Circuits
Wery Important for Asynchronous Sequential Logic.
In this course material we design and analyze only synchronous sequential logic.
Introduction to Sequential Circuits
©Loberg 6
Mealy Type state Machine
Block diagram of Mealy type state machine
Output is a function of both the present state and the input.
Next State Combinational
Logic
Output Combinational
Logic
State Registers
Clock
Outputs Inputs
Exitation equations
Asynchronous outputs
Typically, D flip-flops are used by synthesis tools.
Memory
Introduction to Sequential Circuits
©Loberg 7
Next State Combinational
Logic
Output Combinational
Logic
State Registers
Clock
Outputs
Inputs
000 00 0 001 01 0 010 00 1 011 11 0 100 00 1 101 10 0 110 00 1 111 10 0
ABx AB y t t+1 t
Present states A(t) B(t)
Present input x(t)
Next states A(t+1) B(t+1)
Present output y(t) State table of
Mealy FSM
A(t)B(t) A(t+1)B(t+1)
x(t)/y(t) Present state
Next state
Present input/Present output
State after the clock cycle
x(t)/y(t)
Clock State diagram
x(t+1)/y(t+1)
Introduction to Sequential Circuits
©Loberg
Mealy Type state Machine
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00
11 01
10
0/0 0/1
1/0
1/0 0/1
1/0
1/0
0/1
State diagram of Mealy FSM
000 00 0 001 01 0 010 00 1 011 11 0 100 00 1 101 10 0 110 00 1 111 10 0
ABx AB y t t+1 t
State table of Mealy FSM
A(t)B(t) A(t+1)B(t+1)
x(t)/y(t) Present state Next state
Present input/Present output
State after the clock cycle
x(t)/y(t)
Clock
Example :
A,B input/output
Introduction to Sequential Circuits
©Loberg
Mealy Type state Machine
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Moore Type state Machine
Block diagram of Moore type state machine
Output is only a function of the present state.
Next State Combinational
Logic
Output Combinational
Logic
State Registers
Clock
Outputs Inputs
Exitation equations
Asynchronous outputs
Typically D flip-flops are used by synthesis tools.
Memory
Next States
Present States
Present Outputs
Introduction to Sequential Circuits
©Loberg 10
State table of Moore FSM
000 00 0 001 01 0 010 01 0 011 10 0 100 10 0 101 11 0 110 11 1 111 00 1
ABx AB y t t+1 t
State/Output
x
Clock
Present Input Next state
00/0
11/1
01/0
10/0
x=0
0 0
0
1
1
1
1
State diagram
t
t+1
Example :
Introduction to Sequential Circuits
©Loberg
Moore Type state Machine
AB/y
State
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Latches Storage elements
Storage elements that operate with signal levels are referred to as latches.
SR latch with NAND gates
SR latch with NOR gates
SR latch with control input C
D latch with control input C (Transparent latch)
Introduction to Sequential Circuits
©Loberg 12
SR Latch SR latch with NOR gates
Q
Q
R
S
Allowed input transitions in fundamental mode
0QQ 1n1n == ++
Forbidden
0QQ 1n1n == ++
0QQ 1n1n == ++
00 == nn QQ
Forbidden
Forbidden
1 1
S 0 R 1
S 1 R 0
1 1
1 1
S 0 R 0
1 0
S 0 R 1
S 1 R 0
0 1
S 1 R 1 S 1 R 1
0 0 0 1
S 1 R 1
1 0
Forbidden
Forbidden
Forbidden
Forbidden
1 0
S 0 R 0
0 0
S 1 R 0
S 0 R 1
0 0
S 0 R 0
0 1
1nQ +S R
Function table of SR latch with NOR gates
Forbidden
1nQ +
0 0 1 1
0 1 0 1
0 1 0
nQ1 0 0
nQreset state set state
? = 0 or 1 Depends on previous state
Q QS R
State table
0 0 1 1
0 1 0 1
? 0 1 0
? 1 0 0
"forced" states: reset and set
S
R
Q
Q
Symbol
S
R
Q
Q
Symbol
Introduction to Sequential Circuits
©Loberg
Storage elements
13
SR latch with NAND gates
Q
QR
S? = 0 or 1 Depends on previous state
1nQ +S RForbidden
1nQ +
Function table of SR latch with NAND gates
0 0 1 1
0 1 0 1
1 1 0
nQ
1 0 1
nQ
set state reset state
Q QS R
State table
0 0 1 1
0 1 0 1
1 1 0 ?
1 0 1 ?
"forced" states: reset and set
S
R
Q
Q
Symbol
S
R
Q
Q
Symbol
Introduction to Sequential Circuits
©Loberg
Storage elements SR Latch
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Q
QR
S
0 0 1 1
0 1 0 1
0 1 1
1nQ +
nQS R
Function table of SR latch with NAND gates
Forbidden
1nQ +
1 0 1
nQ
SR latch with NAND gates
In general, the function table of SR latch
? = 0/1 Depend on latch implementation Forbidden
0 0 1 1
0 1 0 1
0 1 ?
1nQ +
nQS R
S
R
Q
Q
Symbol
Introduction to Sequential Circuits
©Loberg
Storage elements SR Latch
15
Set-reset latch timing diagram
With zero-delay model
With non-zero-delay model
Introduction to Sequential Circuits
©Loberg
Storage elements SR Latch
Q
Q
R
S
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SR latch with Control input
Function table of gated SR latch with NAND gates
1nQ +S R 1nQ +C0 0 1 1 X
0 1 0 1 X
0 1 1
nQ1 0 1
nQ1 1 1 1 0 nQ nQ
Forbidden
reset state set state
Q
QR
SC
1nQ +S RForbidden
1nQ +
Function table of SR latch with NAND gates
0 0 1 1
0 1 0 1
1 1 0
nQ
1 0 1
nQ
set state reset state
C=0 Symbol
S
R
Q
QC
Introduction to Sequential Circuits
©Loberg
Storage elements SR Latch
17
D latch with Control input
Function table of gated SR latch with NAND gates
1nQ +S R 1nQ +C0 0 1 1 X
0 1 0 1 X
0 1 1
nQ1 0 1
nQ1 1 1 1 0 nQ nQ
Forbidden
reset state set state
Assumption : SR =
S
Q
Q
DC
R
Symbol
D Q
QC
(Transparent latch)
D Latch
Introduction to Sequential Circuits
©Loberg
Storage elements
18
1nQ +S R 1nQ +C0 1 X
1 0 X
0 1
1 0
1 1 0 nQ nQ
reset state set state
D D
Function table of gated D latch
1nQ +DC0 1 X
0 1
1 1 0 nQ
reset state set state
storage state
"Transparent mode" when C = 1
DQ
C Transparent Storage mode Storage mode
Present state
nQ 1nQ +
Next state
Enable Hold Hold
Introduction to Sequential Circuits
©Loberg
Storage elements D latch with Control input
(Transparent latch)
D Latch
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D Latch Timing Constrains
wt
sut
ht
Minimum pulse width of the gate signal (clock)
Setup Time
Hold Time
DC
Q
wt
sutht
D may not change
sut
ht
Setup time violation
Hold time violation
Introduction to Sequential Circuits
©Loberg
Storage elements D Latch
20
Q
QR
SSW
+5V
1 2
SW in position 1
SW in position 2
S
RQ
Q
1nQ +S RForbidden
1nQ +
Function table of SR latch with NAND gates
0 0 1 1
0 1 0 1
1 1 0
nQ
1 0 1
nQ
set state reset state
A simple application of SR-latch
Introduction to Sequential Circuits
©Loberg
Storage elements Latches
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The End