Fully Industrialised Foundry SPAD

in an Optimised 130nm CMOS

Imaging Technology

Sara Pellegrini

7th February 2019

Agenda

• Introduction to STMicroelectronics Imaging Division

• SPAD pixel

• Diode Details

• Diode Performance inc. Volume Statistics and Reliability Data

• Associated Quench Circuit

• Pixel Performance

• IMG175 Technology Highlights

• SPAD Application Areas

2

Global Presence 3

Front-End

Back-End

Research & Development

Main Sales & Marketing

Among the world’s largest semiconductor companies

Serving over 100,000 customers across the globe

2018 revenues of $9.66B, with year-on-year growth of 15.8%

Listed: NYSE, Euronext Paris and Borsa Italiana, Milan

Signatory of the United Nations Global Compact (UNGC),

Member of the Responsible Business Alliance (RBA)

~46,000 employees worldwide

~ 7,400 people working in R&D

11 manufacturing sites

Over 80 sales & marketing offices

Imaging - Where We Are 4

Grenoble• Product development

• Business & Marketing

• Central functions

Americas• Regional Marketing & Support

Edinburgh• Product development

• Business & Marketing

China + Taiwan +

Korea + Japan• Regional Marketing & Support

• Operations

Paris• Product development

Philippines• Packaging & Test

• OperationsSingapore• Product development

• Regional Marketing & Support

• Operations

Noida• Product development

Additional people located in Agrate, Crolles, Geneva, Rousset, Munich

ST CIS Manufacturing Facilities 5

Crolles

300 mm

Crolles

200 mm

• Area: 40ha

• Buildings' floor surface: 60 000m²

• Cumulated investment > 4 B$

Crolles200

Wafers 200 mm Down to 120 nm

Crolles300

Wafers 300 mm Down to 28 nm

Innovative pixel design

• Rolling & Global shutter

• High Dynamic Range

• High Quantum Efficiency

Imager silicon process

• Front and Back-Side Illumination

• Deep Trench Isolation

• Low optical stack

Large sensors stitching

• 8” and 12’’ wafers

• Ultra large pixels

• High-precision performance

SPAD-based Time-of-Flight

• ST proprietary technology

• Complete integrated solution

• High performance & low power

Low power architecture

• ST proprietary architecture

• Image processing IPs

• 3D stack

Imaging system expertise

• Full optical system know-how

• Image sensors

• Imaging algorithms

6

ST Imaging key assets

Where to find us 7

ImagingSmart Optical Sense & Illumination

Wearable

Appliances

Smart home

Industrial automation

TV/LCD

Medical

Metering

Smartphones

Tablets

Automotive

PC

Robots

20 Years of Imaging solutions at ST 8

500 Millions

ISP shipped

2003 20122009200720051999

Start customers &

applications

diversification

2014 2015

The University of Edinburgh

Starting working in the Sensor

Early paper on CMOS Imaging

Creation of VISION

Start-up from

The University of Edinburgh

1986 1990

STMicroelectronics

acquired VISION

Creation of Imaging Division

Large volume camera

proliferation in Nokia camera

phones

Time-of-flight

Ranging sensor

ramp-up

FlightSense™

pervasion in

smartphones

1M camera module &

ISP shipped for mobile

2002 2017

ST Depth Sensing

600Mu+ shipped in

100+ smartphones

SPAD Pixel

An Introduction to SPADs

• SPADs are at the core of our FlightSense® devices

• SPADs are diodes reverse biased beyond their breakdown voltage

• They are said to operate in Geiger mode

• A single electron/hole pair is required to start avalanche event

• We hope this pair is generated by an incident photon

• Additional pixel circuitry required to stop avalanche process (quench)

and recharge diode ready for next event

• Each avalanche event results in a voltage pulse

• This voltage pulse has a very fast leading edge and can be used to accurately

capture the photon arrival time

10

dSiPM capability provenSPADnet program

ST SPAD technology 11

Optimised & reliable supply chain High volumes & yields

Single Photon Avalanche DiodeUltra fast time resolution

Processed in ST CMOS Imaging process

12 years R&DInitiated with EU FP6 project

Partnership with University of Edinburgh

Over 200 Million

SPAD products shipped

12

Full standard CMOS process. High

voltage process (40V) not needed

8µm circular diode

Quench and recharge logic provided

Low level of Dark Count Rate

Ultra-fast photo response with short

dead-time

Sub 0.1% cross-talk and afterpulsing

operation

Optimized imaging specific BE stack

Mass production and industrialization

proven

IMG

175 f

or

SP

AD

H9A

130nm

IMG140B

65nm-BE

IMG140F

65nm-BE

IMG220

130nm

H8S

180nm

IMG175

90nm-BESPAD

SPAD Diode 13

Metric IMG175SPAD Value (@ 60°C)

[SPIE Photon Counting Conference]

VHV0 13.8V

DCR Median ~1k cps

PDP 3.1% (850nm)

SPAD Fill Factor 6%

Max Count Rate 37Mcps

Jitter 120ps FWHM, 870ps FW1%M

Charge per Pulse 0.08pC

After-Pulsing <0.1%

Cross-Talk <0.01% (isolated SPAD)

Quench and recharge logic

• Used to detect onset of avalanche breakdown in SPAD diode, halt current flow and return

diode to reverse bias Geiger mode state

• The onset and subsequent quench and recharge of a breakdown event is accompanied by

an output pulse at the circuit output with logic levels compatible with standard GO2

transistors

• The falling edge of this output pulse is highly correlated to the photon arrival time at the

diode

14

SPAD_Out

VSPADOFFVHV

Anode

En En

En

VDDPIX

En

VQUENCH

Quench and recharge logic 15

Parameter Value

Mean Pulse Width ~22ns

Charge per pulse 0.08pC per pulse

VDDPIX Range 0.8 – 3.3V

Vquench Range 0.8 – 3.3V

VSPADoff Range 0.8 – 3.3V

Subsequent pixel performance values assume use with this diode

SPAD_Out

VSPADOFFVHV

Anode

En En

En

VDDPIX

En

VQUENCH

Key SPAD Metrics

Diode Reverse Bias Breakdown Voltage

29/03/2016

7/35

OCI_15_140_HTOL_EFR_v1

PS

RP168h

RP500h

RP1000h

170mV widePS RP168h RP500h RP1000h

Median

VHV0 (V) 13.82 13.82 13.82 13.82

Min

VHV0 (V)13.73 13.77 13.73 13.73

Max

VHV0 (V)13.89 13.9 13.89 13.89

• VHV0 = Minimum reverse diode voltage required to produce pixel output pulse

• Diode Reverse Bias Breakdown Voltage + Inverter Threshold Voltage

• High temperature lifetime testing used to evaluate device stability and reliability

over lifetime

• PS = Pre-Screen Baseline Data

• RP168h,500h and 1000h = Measurements made after 168, 500 and 1000

hours of high temperature operation

• No drift in diode bias voltage observed

Dark Count Rate (DCR) 18

• DCR median @ 60°C = 1kcps

• Data collected from 5 lots

• Measurement made @ 60°C

• 90% of SPAD have DCR rate

< 20kcps

HTOL results / Q539109

DCR (cps) @VHV0+0.6V

29/03/2016

14/21

I175 SPAD gen2 MAT30 results for SPAD device

• No SPAD with DCR >=500kcps post HTOL

• Only few outliers with a DCR drift higher than the remaining of the population

DCR (cps) @PS

DC

R (

cps)

@R

P168h

DC

R (

cps)

@R

P500h

DC

R (

cps)

@R

P1000h

500kcps

5kcps

Photon Detection Probability• For a photon to be detected it must be absorbed by the detector and

then generate a electron-hole pair which triggers an avalanche.

• The efficiency of detection increases with excess bias voltage (VEB) due to the higher field increasing the triggering possibility.

20

PPLUSPWELL_NISO SPAD PDE vs VEB (low, med, high)

0

5

10

15

20

25

30

300 400 500 600 700 800 900 1000 1100

Wavelength (nm)

PD

E (

%)

VEB high

VEB low

• An example of a SPAD PDP characteristic at three different level of excess bias is shown.

Wavelength PDP

650nm 16.1%

850nm 3.1%

940nm 1.4%

Pulse width

• Pulse width determines dead time and max CR

• We measure pulse width and we look at its distribution

• Typical is 10 ± 20% ns

21

VHV=VBD+VEB

VOUT

VQCH

SPAD Schematic

photon

Example from early SPAD development

Median = 7 ns

StdDev = 0.9 ns

Light Sweep – Vddpix & Vquench sweep 22

Maximum Count Rate = 37Mcps

Jitter vs excess bias

• Jitter reduces with excess bias on SPAD

23

1.0E-03

1.0E-02

1.0E-01

1.0E+00

2.3E-09 2.8E-09 3.3E-09

No

rmal

ized

co

un

ts

Time / s

Timing JitterSPADDEVELA, pppw_ni_epipoly_circ_8um

Veb = 1.2V Veb = 1.8V Veb = 2.4V Veb = 3.0V

1.2 1.40E-10

1.8 1.20E-10

2.4 1.00E-10

3 1.00E-10

Veb / V FWHM / s

WLC

(wafer level statistics)

Data not available

SPADEVELA

(only a few samples)

SPAD Diode 24

Metric IMG175SPAD Value (@ 60°C)

[SPIE Photon Counting

Conference]

40nm SPAD (@60°C)

[IEDM 2017 Conference]

VHV0 13.8V 15.5V

DCR Median ~1k cps 700 cps

PDP 3.1% (850nm) 5% (850nm)

SPAD Fill Factor 6% >70%

Max Count Rate 37Mcps 150Mcps

Jitter 120ps FWHM, 870ps FW1%M 140ps FWHM, 1.3ns FW1%M

Charge per Pulse 0.08pC 0.06pC

After-Pulsing <0.1% <0.1%

Cross-Talk <0.01% (isolated SPAD) <2% (Shared well)

Digital gate density 80% higher than 130nm CMOS

Power consumption 85% lower than 130nm CMOS

IMG175 / C40 Technology Highlights

IMG175 C40

CMOS process 130nm front-end, 90nm

back-end

40 nm

Reduced height 4 metal

layer back-end stack for

optimised optical

performance

Full 7 metal layers with

Copper metal & Ultra

Low K dielectric

Thick oxide transistor

voltage

2.5V to 3.3V

Thin oxide transistor

voltage

1.3V 1.1V

High-speed and low-leakage thin-oxide devices available

Auto-generated RAM cells

25

Application Areas

FlightSense™ Limitless Applications 27

Automotive

Communication & Consumer

Industrial

Home AppliancesAuto-focus assist, proximity sensing, gesture…

Infotainment system control Proximity detection, door control, robotics…

Robot cleaners, light control, toys…

Measuring true distance independently of target size and reflectance

Distance measured as the time

light takes to hit an object and

then return to the sensor

FlightSense™

Time of Flight Principle

Measured

distance=

Speed of

light x

Photon travel

time / 2

distance

Target

Emitter

Sensor

photon

G4 Beat

VL6180 AF Assist Hall of Fame

G3 & G3 Dual G3 Cat6 G3 Beat G Vista G3A AKA G Flex 2G4 & G4 Dual

Vibe Shot

ZenFone 2 LaserZE500KG

ZenFone SelfieZD551KL

ZenFone 2 LaserZE550KL & ZE500KL

ZenFone ZoomZX551ML

R7+ One+ 2 MX5

Updated MV 30 November 2016 (38)

PRO5

M9+ Aurora Edition

Nexus 6PNexus 5X

ZenFone 2 LaserZE600KL & ZE601KL

V10 G4 Stylus

Blade 7

ZenFone MaxZX550KL & ZC550KL

R7S+ Elfie S8

imoo M1000

NOA H9

P9000

Desire 10 Pro

Zero 4

SPAD Development with Academic Partners

• UoE are exploring CMOS Spad applications in various fields using

testchips developed in ST IMG175 SPAD process

29

• Megaframe 32x32

• MF FP6 (European

Collaborative

Research Project)

• Target Biomedical

• TDC per Pixel

• Ranging Imager• PhD project on Depth

Map imaging

• Array 128 x 9620s exposure showing

mannequin at 1m

Bissacate pollen grain,

12s, 300kframes

• High Fill Factor SPADNET (FP7) Sensor PET/MRI

• SPADNET chips to be arranged in tiles within the circular scanner.

• Each SPADNET ‘pixel’ has 12x15 spads connected as a SiPM

which return information on both Energy and Timestamping.

30

• Energy

histogram

for 511kEv

scintillation

SPADNET1 Sensor

SPAD Development with Academic Partners

Analog Single Photon Counting Pixel 31

Neale Dutton, The University of Edinburgh, International

Image Sensor Workshop (IISW) June 2013

nmos

logic

• One approach being investigated by UoE is to create an NMOS Only

Time to Analog Converter (TAC) in PWELL regions between SPADs.

psub

NMOS

Logic

nw pw

niso

nw pw

• Results from the test chip demonstrate counting of individual photons

• Column Output Voltage Histogram

shows a Discretised Poisson Curve -

matching quantum theory of photons

• Pixel Pitch 9.8um, Read Noise < 0.3e-

VHV

VOUT

photon

VQCH

SPAD Analog TAC

VG

rstSF

Cread

Acknowledgements

• TR&D team in ST Crolles

• Pixel Design Team in ST Edinburgh

• EOCS team in ST Crolles and Edinburgh

• CEA LETI in Grenoble

• Robert Henderson – University of Edinburgh

32

Thank you! 33