full adder design using ledit

ASSIGNMENT 1

SUBMITTED TO:Dr. SUDHANSHU CHAUDHARYAsst. ProfessorSUBMITTED BY:

DHAN RAJ SHEHRAWAT

R.N. 3136511

M.TECH. EMBEDDED SYSTEM

SCHOOL OF VLSI DESIGN & EMBEDDED SYSTEM

N.I.T. KURUKSHETRA

One bit Full Adder

The purpose of this assignment is to introduce an essential component to binary computation - a full adder. For simplification the single bit full adder will be considered (from which the device can be scaled to multiple bits).Input-to-Sum and Carry-in to Carry-out timing restrictions are also factored into this sizing consideration.

The (non-optimized) full adder's functionality using MUX is summarized in Figure below.

Truth Table of one bit Full Adder

The behavioral description focuses on block behavior. Figure 7 shows how two instances of the same building block, the half adder, can be used to implement a full adder using a structural approach.

What Is A One-Bit Full Adder

A one-bit full adder is a device with three single bit binary inputs (A, B, Cin) and two single bit binary outputs (Sum, C-out). Having both carry in and carry out capabilities, the full adder is highly scalable and found in many cascaded circuit implementations. The basic logic functions of the full adder can be summarized in the truth table (right). From the truth table it can be seen that the full adder can be trivially constructed with two half adders. The full adder can also be decomposed into the following logical relationships:

1-Bit Full Adder logic function:

Using K-Map Technique:

Sum = A XOR B XOR C

= ABC + ABC + ABC + ABCCarry_out = AB + AC + BC Exercise: Show that the sum function can be written as shown at left

Sum = ABC + (A + B + C) Carry_out

This alternate representation of the sum function allows the 1-bit full adder to be implemented in complex CMOS with 28 transistors, as shown at left below.

Carry_out internal node is used as an input to the adder complex CMOS gate

Exercise: Show that the two P-trees in the complex CMOS gates of the carry_out and sum are optimizations of the proper dual derivations from the two N-tree networks.How the Sum = ABC + (A+B+C).Carry_out is derived

SUM = [(ABC + ABC + ABC + ABC)]

= [AAB + AAC + ABC + ABB + ABC + BBC + ABC +ACC + BCC + ABC]

=[(AB + AC + BBC + BCC).(A+B+C) + ABC]

=[(AB + AC + BC + BC).(A+B+C) + ABC]

=[(AB + AC + BC).(A+B+C) + ABC]

=[(B + C).(A + BC).(A+B+C) + ABC]

=[(B + C).(A + (B+C)).(A+B+C) + ABC]

=[{(BC)}.{A. (B+C)}.(A+B+C) + ABC]

=[(BC) + {A(B+C)}.(A+B+C) + ABC]

=[(AB+BC+AB).(A+B+C) + ABC]

SUM=(AB+BC+AB).(A+B+C) + ABCFinally, Fig. above shows the circuit diagram of a CMOS one-bit full adder. The circuit has three inputs, and two outputs, sum and carry_out. All input and output signals have been arranged in vertical polysilicon columns. Notice that both the sum-circuit and the carry-circuit have been realized using one uninterrupted active area each.

Layout Technique using Euler Graph Method

Layout Technique using Stick Diagram

Layout Technique using L-edit

File Extracted From Layout

* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ; * TDB File: C:\Tanner Tools v13.0\L-Edit and LVS\Tech\Mosis\FA_1bit.tdb* Cell: Cell0Version 1.02 * Extract Definition File: mamin08.ext * Extract Date and Time: 09/18/2013 - 21:37.include mamin08.md

* Warning: Layers with Unassigned AREA Capacitance.*

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* Warning: Layers with Unassigned FRINGE Capacitance.

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* NODE NAME ALIASES

* 1 = SUM (253 , -10.5)

* 11 = Cin (-22.5 , -18.5)

* 12 = Cout (-22 , -10.5)

* 13 = Ain (-22.5 , 3)

* 14 = Bin (-22.5 , -3.5)

* 16 = VDD (-19.5 , 39.5)

* 17 = GND (-20 , -53.5)

Cpar1 1 0 C=8.744f

Cpar2 6 0 C=17.488f

Cpar3 7 0 C=7.168f

Cpar4 8 0 C=27.048f

* Warning: Node 11 has zero nodal parasitic capacitance.

Cpar5 12 0 C=8.744f



Cpar6 15 0 C=10.288f

Cpar7 16 0 C=34.776f

Cpar8 17 0 C=16.64f

Cpar9 18 0 C=20.608f



M28 1 6 16 21 PMOS L=1u W=4u AD=20p PD=18u AS=20p PS=18u $ (238 6 240 14)

M27 6 13 5 21 PMOS L=1u W=4u AD=20p PD=18u AS=7p PS=7.5u $ (213 6 215 14)

M26 4 11 5 21 PMOS L=1u W=4u AD=7p PD=7.5u AS=7p PS=7.5u $ (204 6 206 14)

M25 4 14 8 21 PMOS L=1u W=4u AD=7p PD=7.5u AS=20p PS=18u $ (195 6 197 14)

M24 1 6 17 20 NMOS L=1u W=2u AD=18p PD=18u AS=18p PS=18u $ (238 -35 240 -31)

M23 17 13 3 20 NMOS L=1u W=2u AD=18p PD=18u AS=3.5p PS=5.5u $ (213 -35 215 -31)

M22 2 11 3 20 NMOS L=1u W=2u AD=3.5p PD=5.5u AS=3.5p PS=5.5u $ (204 -35 206 -31)

M21 2 14 6 20 NMOS L=1u W=2u AD=3.5p PD=5.5u AS=18p PS=18u $ (195 -35 197 -31)





















* Total Nodes: 21

* Total Elements: 37

* Total Number of Shorted Elements not written to the SPICE file: 0

* Output Generation Elapsed Time: 0.000 sec

* Total Extract Elapsed Time: 2.371 sec

.ENDFile Created for T-SPICE Simulation

* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;

* TDB File: C:\Tanner Tools v13.0\L-Edit and LVS\Tech\Mosis\FA_1bit.tdb

* Cell: Cell0Version 1.02

* Extract Definition File: mamin08.ext

* Extract Date and Time: 09/18/2013 - 21:37

.include "C:\Tanner EDA\Demo\T-Spice\models\ml2_125.md"

* NODE NAME ALIASES

* 1 = SUM (253 , -10.5)

* 11 = Cin (-22.5 , -18.5)

* 12 = Cout (-22 , -10.5)

* 13 = Ain (-22.5 , 3)

* 14 = Bin (-22.5 , -3.5)

* 16 = VDD (-19.5 , 39.5)

* 17 = GND (-20 , -53.5)VDD 16 0 5

VGND 17 0 0

VAin 13 0 PULSE (0 5 0 1ns 1ns 30ns 60ns)

VBin 14 0 PULSE (0 5 0 1ns 1ns 60ns 120ns)

VCin 11 0 PULSE (0 5 0 1ns 1ns 15ns 30ns)

.print tran v(1,0) v(12,0) v(13,0) v(14,0) v(11,0)

.tran 2ns 200ns start=2ns

Cpar1 1 0 C=8.744f

Cpar2 6 0 C=17.488f

Cpar3 7 0 C=7.168f

Cpar4 8 0 C=27.048f


Cpar5 12 0 C=8.744f



Cpar6 15 0 C=10.288f

Cpar7 16 0 C=34.776f

Cpar8 17 0 C=16.64f

Cpar9 18 0 C=20.608f





M26 4 11 5 21 PMOS L=1u W=4u AD=7p PD=7.5u AS=7p PS=7.5u $ (204 6 206 14)




M22 2 11 3 20 NMOS L=1u W=2u AD=3.5p PD=5.5u AS=3.5p PS=5.5u $ (204 -35 206 -31)






















* Total Nodes: 21

* Total Elements: 37

* Total Number of Shorted Elements not written to the SPICE file: 0

* Output Generation Elapsed Time: 0.000 sec

* Total Extract Elapsed Time: 2.371 sec

.ENDWave Created by W-Edit Simulation Tool

Output Generated by T-SPICE after Simulation* T-Spice 13.00 SimulationWed Sep 18 21:47:29 2013C:\Users\DhanRajShehrawat\Pictures\FA_1bit.spc

* Command line: tspice -o C:\Users\DhanRajShehrawat\Pictures\FA_1bit.out C:\Users\DhanRajShehrawat\Pictures\FA_1bit.spc

* T-Spice Win32 13.00.20080321.01:01:33

*SEDIT: Alter blocks = 0* Accuracy and Convergence options:

* numndset|dchold = 100

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* Timestep and Integration options:

* relq|relchgtol = 0.0005

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* Model Evaluation options:

* dcap = 2 defnrb = 0 [sq] defnrd = 0 [sq]

* defnrs = 0 [sq] tnom = 25 [deg C]

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* General options:

* temp = 25 [deg C] threads = 1

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* Output options:

* acout = 1 ingold = 0

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* Device and node counts:

* MOSFETs - 28 MOSFET geometries - 32

* BJTs - 0 JFETs - 0

* MESFETs - 0 Diodes - 0

* Capacitors - 9 Resistors - 0

* Inductors - 0 Mutual inductors - 0

* Transmission lines - 0 Coupled transmission lines - 0

* Voltage sources - 5 Current sources - 0

* VCVS - 0 VCCS - 0

* CCVS - 0 CCCS - 0

* V-control switch - 0 I-control switch - 0

* Macro devices - 0 External C model instances - 0

* HDL devices - 0

* Subcircuits - 0 Subcircuit instances - 0

* Independent nodes - 16 Boundary nodes - 6

* Total nodes - 22 *SEDIT: Alter=0

*SEDIT: Analysis types DCOP 0 ACMODEL 0 AC 0 TRANSIENT 1 TRANSFER 0 NOISE 0

*WEDIT: .tran 2e-009 2e-007 START= 2e-009

TRANSIENT ANALYSIS

Time v(1,0) v(12,0) v(13,0) v(14,0) v(11,0)

2.000000e-009 4.6632e+000 4.9957e+000 5.0000e+000 5.0000e+000 5.0000e+000

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------SO ON* Parsing 0.02 seconds

* Setup 0.09 seconds

* DC operating point 0.06 seconds

* Transient Analysis 0.79 seconds

* Overhead 1.47 seconds

* -----------------------------------------

* Total 2.43 seconds* Simulation completed

* End of T-Spice output file

full adder design using ledit

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