Full Adder

Section 4.5Spring, 2014

J.Ou

Schedule

6 2/3 Monday Binary addition: full adder 7 2/5 Wednesday Binary addition: full adder/four-bit adder

L 2/6 Thursday Lab canceled8 2/10 Monday Class canceled9 2/12 Wednesday Four bit subtractor, effects of gate delay,

binary multiplicationL 2/13 Thursday Binary adder: full adder 10 2/17 Monday Decoder 11 2/19 Wednesday Encoder

L 2/20 Thursday Decoder Experiment12 2/24 Monday MUX/Three state13 2/26 Wednesday Review

L 2/27 Thursday Random number generator14 3/3 Monday Test 1

Outline

• Review of a Half Adder• Full Adder– Explanation– Step-By-Step Module Writing

• Four Bit Adder

Derivation of ∑

Question: What primitive best implements ∑? • Inputs: A, B• Outputs: ∑=

B A ∑

0 0 0

1 0 1

0 1 1

1 1 0

Derivation of Carry Out

Question: What primitive best implements Co? • Inputs: A, B• Outputs: Co =A∙B

B A Co

0 0 0

1 0 0

0 1 0

1 1 1

Implementation of a Half-Adder

Limitation of a Half Adder

A half-adder does not account for carry-in.

Truth Table for a Full Adder

carry-in

Karnaugh Map For the Sum Bit

= = =

Karnaugh Map For the Carry-Out Bit

C=𝑥 ′ 𝑦𝑧+𝑥 𝑦 ′ 𝑧+𝑥𝑦=𝑧 (𝑥⊕𝑦 )+𝑥𝑦

Implementation of a Full Adder

𝐶=𝑧 (𝑥⊕𝑦 )+𝑥𝑦𝑆=𝑧⊕(𝑥⊕𝑦 )

(carry-in)

Build a Full-Adder Circuit

w1

w2 w3

M1 M2

Module Templatemodule module_name ( , , )

endmodule

Input, outputwiresreg

Program Body

Module Declaration

w1

w2 w3

M1 M2

x,y, and z are the input portss,c are the output ports

wires:x, y,z, s, cwires w1, w2, w3

Module Templatemodule module_name ( , , )

endmodule

Input, outputwiresreg

Program Body

Program Body

w1

w2 w3

M1 M2

• Use existing half adder cells• Two instances: M1 and M2• Need an OR gate:

• I can use either primitive gates• Use assign statement

Module Test Bench Template//`timescale 1 ms /1 usmodule module_tb_name ( , , )

endmodule

Input, outputwiresreg

Define the test bench

Call on the module

Modify half_adder_tb.v

1. Change `include line2. Change module name

Module Test Bench Template//`timescale 1 ms /1 usmodule module_tb_name ( , , )

endmodule

Input, outputwiresreg

Define the test bench

Call on the module

Change input/output, wire/regs

To do list:1. Increase X,Y to X,Y,Z

a. outputb. t_X,t_Y, t_Z

Question:Why do we have to usereg X,Y, but not wire X, Y?

After Modifying the Module Declaration

Module Test Bench Template//`timescale 1 ms /1 usmodule module_tb_name ( , , )

endmodule

Input, outputwiresreg

Define the test bench

Call on the module

To-Do List

1. Change output file name2. Add Z to $fmonitor line3. Read from three bit files4. Update Z from t_Z 5. Change how the moduleis invoke.

Implement the To-Do List

Error!

Erroneous Output

Program Body

w1

w2 w3

M1 M2

Output

Four-Bit Adder

C4 is calculated last because it takes C0 8 gates to reach C4.Each FA uses 2 XOR, 2 AND and 1 OR gate.A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.

G0G1G2G3

Outputtime=230 A0=1 A1=0 A2=0 A3=1 B0=1 B1=0 B2=0 B3=1 C0=0 S0=0 S1=1 S2=0 S3=0 C4=1time=240 A0=0 A1=1 A2=0 A3=0 B0=0 B1=0 B2=1 B3=0 C0=1 S0=1 S1=1 S2=1 S3=0 C4=0time=250 A0=0 A1=0 A2=0 A3=1 B0=1 B1=0 B2=0 B3=0 C0=0 S0=1 S1=0 S2=0 S3=1 C4=0time=260 A0=0 A1=1 A2=1 A3=1 B0=1 B1=1 B2=1 B3=0 C0=0 S0=1 S1=0 S2=1 S3=0 C4=1time=270 A0=0 A1=0 A2=1 A3=0 B0=0 B1=1 B2=0 B3=0 C0=1 S0=1 S1=1 S2=1 S3=0 C4=0time=280 A0=1 A1=0 A2=0 A3=0 B0=0 B1=0 B2=0 B3=1 C0=1 S0=0 S1=1 S2=0 S3=1 C4=0time=290 A0=0 A1=0 A2=0 A3=0 B0=0 B1=0 B2=0 B3=0 C0=1 S0=1 S1=0 S2=0 S3=0 C4=0time=310 A0=0 A1=0 A2=0 A3=1 B0=1 B1=0 B2=0 B3=0 C0=0 S0=1 S1=0 S2=0 S3=1 C4=0time=320 A0=1 A1=1 A2=1 A3=0 B0=0 B1=1 B2=1 B3=1 C0=1 S0=0 S1=1 S2=1 S3=0 C4=1time=330 A0=0 A1=1 A2=0 A3=0 B0=0 B1=0 B2=1 B3=0 C0=1 S0=1 S1=1 S2=1 S3=0 C4=0time=340 A0=1 A1=1 A2=0 A3=1 B0=1 B1=0 B2=1 B3=1 C0=0 S0=0 S1=0 S2=0 S3=1 C4=1time=350 A0=0 A1=1 A2=0 A3=1 B0=1 B1=0 B2=1 B3=0 C0=0 S0=1 S1=1 S2=1 S3=1 C4=0time=360 A0=0 A1=0 A2=0 A3=0 B0=0 B1=0 B2=0 B3=0 C0=1 S0=1 S1=0 S2=0 S3=0 C4=0

Things to Sort Through before writing the module

• four_bit_adder.v–What should be declared as inputs?–What should be declared as outputs?– How do I connect the ports of

four_bit_add.v module to ports of full_adder.v module?

–What should be declared as wires–What verilog modules should I include?– How should the instance be invoked?

Things to Sort Through Before Writing the Module

• four_bit_adder_tb.v–What test bench should I use as a

template?–What should be the output?–What wires should I have?–What should I replace t_X,t_Y, t_Z with?– How should the four_bit_adder.v be

invoked?– How should the output be printed?

What Will Be provided?

• Bit files (9 files in all, downloadable from the course website)

• half_adder.v• What you need to implement:– full_adder.v– full_adder_tb.v– four_bit_adder.v– four_bit_adder_tb.v

• Due date: Next Wed (2/12) in Class.