final logic families

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DIGITAL LOGIC FAMILIES

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Digital Logic Families

ICs are also classified based on their specific circuit technology, known asdigital logic family.

Each family has its own basic electronic components (NAND, NOR, andNOT gates), used to build complex digital circuits.

Various digital logic families have been introduced and used over theyears.

(in chronological order) RTL: Resistor-Transistor Logic DTL: Diode-Transistor Logic TTL: Transistor-Transistor Logic ECL: Emitter-coupled Logic

MOS: Metal-Oxide Semiconductor CMOS: Complementary MOS Low power dissipation, currently the MOST DOMINANT

BiCMOS: Bipolar CMOS CMOS and TTL for additional current/speed

GaAs: Gallium-Arsenide

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Defining Characteristics ofDigital Logic Families

Fan-in: # of gate inputs.

Fan-out: # of standard loads a gates output can drive.

Noise margin: max external noise tolerated.

Power dissipation: power consumed by the gate (dissipated asheat).

Propagation delay: time required for an input signal change to beobserved at an output line.

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PropagationDelayOne of the most important design parameters (if not THE most

important!)The maximum propagation delay (tpd) determines the circuits speed.tPHL: high-to-low propagation timetPLH: low-to-high propagation timetpd = max(tPHL, tPLH)


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The Power dissipation of a logic gate is the product of thedirect current (dc) voltage supply (VCC) and the averagesupply current (ICC). The average ICC is determined basedon a 50% duty cycle, i.e. the state is LOW 50% of the timeand HIGH 50% of the time.

The fan-out of a gate is the maximum number of inputs ofthe same IC family series that the gate can drive whilemaintaining the its output levels within specified limits. Inshort, it specifies the maximum load that a given gate can

handle. If this limit is exceeded that the operation of thegate degrades and become unpredictable.

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Figure of merit

A Figure of merit is a quantity used to characterize the

performance of a device relative to other devices of thesame type. It is often used as a marketing tool to convinceconsumers to choose a particular brand. Power - DelayProduct:

Another Important Parameter = (Average Power

Diss)x(Propagation Delay)

Fan-in

The number of standard loads drawn by an input toensure reliable operation. Most inputs have a fan-in of 1.

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Logic Threshold Voltage Levels

VCC: The voltage applied to the power pin(s). In mostcases the voltage the device needs to operate at.

VIH:[Voltage Input High] The minimum positivevoltage applied to the input which will be accepted by thedevice as a logic high.

VIL:[Voltage Input Low] The maximum positivevoltage applied to the input which will be accepted by thedevice as a logic low.

VOL:[Voltage Output Low] The maximum positivevoltage from an output which the device considers will be

accepted as the maximum positive low level.VOH:[Voltage Output High] The maximum positive

voltage from an output which the device considers will beaccepted as the minimum positive high level.

VT:[Threshold Voltage] The voltage applied to a device

which is "transition-Operated", which cause the device toswitch. Ma also be listed as a '+' or '-' value.

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NoiseMargin

Logic Noise Margin is the difference between what the

driver IC outputs as a valid logic voltage and what thereceiver IC expects to see as a valid logic voltage. Thereare two different types of noise margin, one for a logichigh value [1] and one for a logic low value [0]. For avalid logic low, the worst case noise margin for thecircuit is the maximum low level voltage which may be

output from the driver; minus, the maximum low levelvoltage which may be seen at the receiver IC

Noise Margin Output high = VOH [driving device] - VIH[receiving device]

Noise Margin Output low = VIL [receiving device] -VOL [driving device]

The higher the numbers the better, with negative numbersindicating in-operability. Use Minimum numbers foroutput High, and maximum numbers for Output Low.

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Diode LogicDiode Logic makes use of the fact that the electronic device

known as a diode will conduct an electrical current in one

direction, but not in the other. In this manner, the diode acts asan electronic switch.

To the left you see a basic Diode Logic OR gate. We'll assumethat a logic 1 is represented by +5 volts, and a logic 0 isrepresented by ground, or zero volts. In this figure, if bothinputs are left unconnected or are both at logic 0, output Z willalso be held at zero volts by the resistor, and will thus be a logic

0 as well. However, if either input is raised to +5 volts, its diodewill become forward biased and will therefore conduct. This inITM,Gurgaon


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To the right is the equivalent AND gate. We use the same

logic levels, but the diodes are reversed and the resistor isset to pull the output voltage up to a logic 1 state. For thisexample, +V = +5 volts, although other voltages can justas easily be used. Now, if both inputs are unconnected orif they are both at logic 1, output Z will be at logic 1. Ifeither input is grounded (logic 0), that diode will conduct

and will pull the output down to logic 0 as well. Bothinputs must be logic 1 in order for the output to be logic1, so this circuit performs the logical AND function.

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Resistor-Transistor Logic

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Resistor-Transistor Logic . Consider the most basictransistor circuit, such as the one shown to the left. We willonly be applying one of two voltages to the input I: 0 volts(logic 0) or +V volts (logic 1). We'll assume an ordinary

NPN transistor here, with a reasonable dc current gain, an

emitter-base forward voltage of 0.65 volt, and a collector-emitter saturation voltage no higher than 0.3 volt. Instandard RTL ICs, the base resistor is 470 and the collectorresistor is 640.


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When the input voltage is zero volts (actually, anything under0.5 volt), there is no forward bias to the emitter-base junction,and the transistor does not conduct. Therefore no currentflows through the collector resistor, and the output voltage is+V volts. Hence, a logic 0 input results in a logic 1 output


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Diode-Transistor Logic:

Diode-Transistor Logic


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The gate to the right is a DL OR gate followed by aninverter such as the one we looked at in the page onresistor-transistor logic. The OR function is still

performed by the diodes. However, regardless of thenumber of logic 1 inputs, there is certain to be a highenough input voltage to drive the transistor intosaturation.

The advantage of this circuit over its RTL equivalent isthat the OR logic is performed by the diodes, not byresistors. A disadvantage of this circuit is the inputresistor to the transistor. Its presence tends to slow thecircuit down, thus limiting the speed at which thetransistor is able to switch states.
http://www.play-hookey.com/digital/electronics/rtl_gates.htmlhttp://www.play-hookey.com/digital/electronics/rtl_gates.html


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The designers of commercial TTL IC gates reduced thatproblem by modifying the output circuit. The result was the"totem pole" output circuit used in most of the 7400/5400 seriesTTL ICs. The final circuit used in most standard commercialTTL ICs is shown to the right. The number of inputs may vary

a commercial IC package might have six inverters, four 2-input gates, three 3-input gates, or two 4-input gates. An 8-inputgate in one package is also available. But in each case, thecircuit structure remains the same.


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In the TTL NAND gate of Figure 1, applying a logic '1'

input voltage to both emitter inputs of T1 reverse-biases bothbase-emitter junctions, causing current to flow through R1into the base of T2, which is driven into saturation. When T2starts conducting, the stored base charge of T3 dissipatesthrough the T2 collector, driving T3 into cut-off. On theother hand, current flows into the base of T4, causing it tosaturate and pull down the output voltage Vo to logic '0', ornear ground. Also, since T3 is in cut-off, no current willflow from Vcc to the output, keeping it at logic '0'. Note that

T2 always provides complementary inputs to the bases of T3and T4, such that T3 and T4 always operate in oppositeregions, except during momentary transition betweenregions.


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CMOS Logic

CMOS Logic: CMOS logic is a newer technology, basedon the use of complementary MOS transistors to performlogic functions with almost no current required. Thismakes these gates very useful in battery-poweredapplications. The fact that they will work with supplyvoltages as low as 3 volts and as high as 15 volts is alsovery helpful.

CMOS gates are all based on the fundamental inverter

circuit shown to the left. Note that both transistors areenhancement-mode MOSFETs; one N-channel with itssource grounded, and one P-channel with its sourceconnected to +V. Their gates are connected together toform the input, and their drains are connected together to

form the output.


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When input A is grounded (logic 0), the N-channelMOSFET is unbiased, and therefore has no channelenhanced within itself. It is an open circuit, and thereforeleaves the output line disconnected from ground. At thesame time, the P-channel MOSFET is forward biased, soit has a channel enhanced within itself. This channel hasa resistance of about 200 , connecting the output line tothe +V supply. This pulls the output up to +V (logic 1).

When input A is at +V (logic 1), the P-channel MOSFETis off and the N-channel MOSFET is on, thus pulling theoutput down to ground (logic 0). Thus, this circuitcorrectly performs logic inversion, and at the same time

provides active pull-up and pull-down, according to theoutput state.


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This concept can be expanded into NOR and NAND

structures by combining inverters in a partially series,partially parallel structure. The circuit to the right is apractical example of a CMOS 2-input NOR gate.

In this circuit, if both inputs are low, both P-channelMOSFETs will be turned on, thus providing a connectionto +V. Both N-channel MOSFETs will be off, so therewill be no ground connection. However, if either inputgoes high, that P-channel MOSFET will turn off anddisconnect the output from +V, while that N-channel

MOSFET will turn on thus grounding the output

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