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Digital Logic Families

TTL: Transistor-Transistor Logic

ECL: Emitter-coupled Logic

MOS: Metal-Oxide Semiconductor

CMOS: Complementary MOS Low power dissipation, currently the MOST DOMINANT

high-speed operation

widely used

compact

Ref: Digital Design: Moris Mano PHI

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Fan-out: # of standard loads a gates output can drive.

Noise margin: max external noise tolerated.

Power dissipation: power consumed by the gate

(dissipated as heat).

Propagation delay: time required for an input signal

change to be observed at an output line.

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TTL Series name Prefix

Standard 74

Low-power 74LHigh-speed 74H

Schottky 74S

Low-power Schottky 74LS

Advanced Schottky 74AS

Advanced Low power- Schottky 74ALS

Fast 74F

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Base-Emitter voltage less than 0.6V ; IB = 0

Cut-Off region

Base-Emitter voltage more than 0.6V,

transistor starts conducting

active region IC

= IB

Maximum collector current IC = VCC/RC

BJT Characteristics

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In the cut-off region VBE < 0.6V, VCE opencircuit, IC, IB negligible

In the active region VBE about 0.7 VCE widerange and IC = IBIn the saturation region VBE hardly changes,VCE= 0.2V

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Three Types of TTL gates

- Open - collector output

- Totem- pole output

- Three- state output

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Open Collector gates are used

-Driving relays and lamps

-Wire ANDing

-Construction of common bus system

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Output impedance of a gate is resistive plusCapacitive load ( typical C = 15 pF)

For output low to high transition C charges exponentially

through RC

R is RL ( external) in open collector

For a typical value of C = 15pF, RL = 4k propagationdelay for turn off is 35nS.

With active pull-up delay can be reduced

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Wired Logic not allowed in Totem pole gates

excessive current drawn by one gate can

damage it

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Reduction in storage timereduction in

propagation delay

Schottky diode- metal semiconductor junction

Schottky transistor- Schottky diode between

base and collector

Schottky TTL

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Y = (A(D+E) + BC)

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F = AB + AC + ABC