EBB1143: Digital Electronics II “IC Logic Families”Fawnizu Azmadi Hussin
TTL – Transistor-Transistor Logic
Diode representation of a TTL transistor.
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TTL NAND Gate
The basic TTL logic circuit. The simplest form in the family.
Let’s analyze. LOW OUTPUT
Note:
Q: What happens to the output if D1 is removed?
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TTL in Action : Current-Sinking
Figure 8-9(a) shows conditions for the driving gate in the low state.
Transistor Q3 is an open circuit, while Q4 provides a very low resistance for the current flowing out of the driven gate’s input.
The input circuit is actually a forward biased diode and several mA of sink current flows.
Current flow in the base-emitter (diode) causes collector current to flow in Q1.
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TTL in Action : Current-Sourcing
Figure 8-9(b) shows conditions for the driving gate in the high state.
Transistor Q4 is an open circuit, while Q3 provides a low resistance for the current flowing into the driven gate’s input.
The input circuit is now a reverse biased diode, and A of source current flows.
The source current is simply the reverse biased diode’s leakage current. Transistor Q1 is turned off
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TTL circuits have a similar structure
The input will be the cathode of a PN junction
A HIGH input will turn OFF the junction and only a leakage current is generated.
A LOW input turns ON the junction and a relatively large current is generated
Most TTL circuits have some type of totem-pole output configuration
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54 series operates over a wider temperature range
Same numbering system, prefix indicates manufacturer
SN – Texas Instruments
DM – National Semiconductor
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Two types of propagation delay:
tPLH, delay time in output going from logical 0 to 1
tPHL, delay time in output going from logical 1 to 0
due to the change in input(s)
Propagation delay
Noise Immunity / Margin
Voltage levels are not constant. Stray electric and magnetic fields can cause spikes and cause input voltage to rise above VIL (max) or decrease below VIH(min).
We must make allowances for those variations, as shown by VNL and VNH.
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Noise Immunity (cont.)
VNH = VOH (min) – VIH (min)
The low state noise margin VNL is defined as
VNL = VIL (max) – VOL (max)
*
Example 8-1
The I/O voltage specification for the standard TTL family are listed in the following table. Use these values to determine the following
The maximum amplitude noise spike that can be tolerated when a HIGH output is driving an input
The maximum amplitude noise spike that can be tolerated when a LOW output is driving an input
Parameter
Maximum amplitude noise spike is equivalent to the noise margins.
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IC Terminology
Power Requirements
Every IC requires electrical power to operate. The supply comes from VCC (TTL), or VDD (CMOS).
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IC Terminology
Speed-Power Product
We would like to have the fastest IC with the least power consumption.
A common means for measuring and comparing the overall performance of an IC family is the speed-power product.
Suppose an IC family has:
Average power dissipation, PD(avg) = 5 mW.
Average propagation delay, tP(avg) = 10 ns.
Speed-power product is
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Standard TTL, 74 series
Schottky TTL, 74S series
Advanced Schottky TTL, 74AS series (AS-TTL)
Advanced low power Schottky TTL, 74ALS series
74F fast TTL
Refer to Table 8-6 for a comparison between the series characteristics
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3ns 20 mW 60 pJ
1.7ns 8 mW 13.6 pJ
4 ns 1.2 mW 4.8 pJ
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8-5 TTL Loading and Fan Out
Fan out refers to the load drive capability of an IC output
A TTL output has a limit on how much current it can sink in the LOW state
A TTL output has a limit on how much current it can source in the HIGH state.
Exceeding these currents will result in output voltage levels outside specified ranges
We will study Noise Margins later
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Determining fan out
Add the IIH for all inputs connected to an output. The sum must be less than the output IOH specification.
Add the IIL for all inputs connected to an output. The sum must be less than the output IOL specification.
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Example (Fan-out)
A standard TTL gate can deliver a maximum output current of 0.4 mA (400 A) in the high state.
Each driven gate input requires a current of 40A when the driving gate output is high.
Choose the correct answer:
Calculate the fan-out.
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Current transients
When a totem pole TTL output goes from LOW to HIGH, a high amplitude current spike is drawn from the VCC supply
Ceramic disk capacitors (.01 or .1 F) are used to short these high frequency spikes to ground.
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Example 2 (Fan-out)
When X is at HIGH logic?
When X is at LOW logic?
Assume all logic gates are from Schottky
family with the following characteristics
IIH = 20 A
IIL = 0.4 mA
on both HIGH and LOW states.
How can we further reduce the load current?
*
• You could reduce the load on gate 1 by connecting the extra input (the lower one) on gate 2 through a pull-up resistor to +5V.
• You could reduce the load on gate 1 by connecting the extra inputs (the lower two) on gate 4 to ground. You must not allow inputs to float.
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Self reading