PUBLIC

DOLPHIN ABESSOLO-BIDZO

EMC-ESD IN DE PRAKTIJK

NOVEMBER 9TH, 2016

ESD LAYOUT CHECK TOOL:

APPLICATION TO RF IC DESIGNS

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OutlineOutline

• Introduction

• IC Level ESD

• HBM layout Simulations

• Predictive CDM Simulations

• Conclusions

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IntroductionIntroduction

• Context:

−Rapidly increasing RF Complexity of RF BiCMOS IC designs

−Key Mobile, Internet Everywhere and Car Radio applications

• Extreme RF performance vs. NXP IC’s ESD reliability requirements:

−Big challenge to achieve first time right silicon for both

−ESD layout check tools are essential to verify proper layout implementation

• ESD Layout Check tools are applied to RF IC designs in NXP propriety

RF BiCMOS technology

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IC Level ESDIC Level ESD

Courtesy of Theo Smedes

• IC’s can be exposed to ESD during assembly

• ESD on-chip protection is used to protect IC during manufacturing

• Qualification of IC by (JEDEC) standards:

−Human Body Model (HBM)

−Charged Device Model (CDM)

• Stresses are applied to all the pins of the IC

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IC Level ESD: Human Body Model (HBM)IC Level ESD: Human Body Model (HBM)

• HBM: Where a charged human gets discharged by making contact to

exposed IC pins

HBM Characteristics

Qualification Level 2kV

Pulse Width ~150ns

Rise Time 2-10ns

Peak Current 1.33A

ESD Association

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IC Level ESD: Charged Device Model (CDM)IC Level ESD: Charged Device Model (CDM)

• CDM: IC packages that acquire charge can discharge to ground

through their pins

CDM Characteristics

Qualification Level 500V

Pulse Width ~1.5ns

Rise Time 100-300ps

Peak Current* 1-15A

ESD Association

* IC package dependent

HBM LAYOUT SIMULATIONS

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LNA Design LNA Design

• An integrated 800µm x 800µm low

noise amplifier (LNA) and switch

• Processed in an NXP proprietary

BiCMOS technology

• Integrated circuit used in RF modules

for mobile applicationsESD CLAMP

Backend view

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SEM view of the ESD diode

HBM Failure MechanismHBM Failure Mechanism

• During HBM zap, a high clamping voltage is built up across the ESD

diode

• Leading to observed HBM failure: breakdown of the ESD diode

Pin A

GND

IO circuit

500 Ohm

200 Ohm

Secondary ESD Protection

VDD

ES

D C

LA

MP

VCC ZAP

REF

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HBM Simulations: Input DataHBM Simulations: Input Data

e.g. ESD Diode

• ESD Device (measured data)

• Design data (layout database)

• Technology Data (process layer map,

ESD rule file)

• Execution Setup (description of the ESD

tests of interest)

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HBM Simulations: ESD Violations (1)HBM Simulations: ESD Violations (1)

• High current density crowding is observed in the ESD diodes area

ESD diodes

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HBM Simulations: ESD Violations (2)HBM Simulations: ESD Violations (2)

• High ESD current density (488 % Stress !) reported in the ESD diodes

area by the HBM simulations

• The observed HBM failure mechanism is identified by HBM

simulations successfully !

• A redesign metal fix was implemented and the HBM simulations

reported NO violation (0 % Stress !)

• This was further confirmed with silicon results with HBM qualification

pass.

HBM Sim. Zap name Vclamp (V) Ipeak (A) Reff (Ω) Stress,%

Fail VCC vs. PinA 11.7 1.3 8.4 488%

Pass VCC vs. PinA 8.6 1.3 4.2 0%

PREDICTIVE CDM SIMULATIONS

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CDM Tester ModelCDM Tester Model

Model has been calibrated on Standard ESDA verification modules

Simulated waveforms agreed with measured current discharges

100MΩ

VCDM

RARC

LPOGO

RPOGO 1Ω

RGND

CGND

RTESTER

LTESTER

LPIN

CPACKAGE CDIE-ATTACH

LBONDWIRE

CDM CHARGING

PLATE

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High

Low

CDM Simulations: Substrate ModelingCDM Simulations: Substrate Modeling

A 3.5mm x 3.3mm Silicon Tuner IC processed in an NXP proprietary

BiCMOS technology

The substrate coupling of the die is extracted with a 3D high frequency

electromagnetic solver @ 1.1GHz

VS

S1

VSS5

VS

S4

VSS3VSS2

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CDM Simulations: IC Package ModelCDM Simulations: IC Package Model

• IC package influences the CDM discharge significantly

• Accurate Spice simulation model required

• Based on Time Domain Reflectometry (TDR) measurements

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CDM Discharge SimulationsCDM Discharge Simulations

Good agreement simulation and measurement

RARC= 30Ω arc impedance (used as fitting parameter for Ipeak)

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

0 1 2 3 4 5

Ipe

ak

(A

)

Time (ns)

PUT Measurement

PUT Simulation

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Cross-Domain CDM FailCross-Domain CDM Fail

Failure mode: passed 400V but failed -500V

Gate-source defect in an NMOST cross-domain circuit VDD4-VSS1

Antenna diode does not prevent CDM failure

Note: The central ESD clamp is not shown

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Cross-Domain Voltage SimulationCross-Domain Voltage Simulation

Simulation explains

−Failure mode (Gate oxide breakdown)

−No CDM X-domain failure in VDD4-VSS3

-3

-1

1

3

5

7

9

11

13

15

17

0 1 2 3 4 5X-d

om

ain

Vo

lta

ge

(V

)

Time (ns)

differential VDD4-VSS1

differential VDD4-VSS3

BVox

The failure mode was fixed

A local CDM clamp was added

in parallel to the antenna diode

CONCLUSIONS

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ConclusionsConclusions

• The HBM simulations have been silicon calibrated successfully and are

useful:

− to verify ESD design guidelines are met

− to highlight weak areas of IC designs

− to report current density violations and high resistance paths

This predictive CDM simulation method is efficient to:

−understand the CDM discharge mechanism in IC’s

− improve the predictability of CDM robustness of the IC’s

• ESD Layout Check Tools are applied, implemented and used for RF IC

designs before tape-out within NXP Semiconductors