System-level ESD protection of high-voltage tolerant IC pins – A case study

Mirko Scholz 1, Steven Thijs, Shih-Hung Chen 2, Alessio Griffoni, Dimitri Linten, Masanori Sawada 3, Gerd Vandersteen 1, Guido Groeseneken 2

imec, Kapeldreef 75, 3001 Leuven, Belgium (1) also at: Vrije Universiteit Brussels, Dept. ELEC, Brussels, Belgium;

(2) also at: Katholieke Universiteit Leuven, Dept. ESAT, Leuven, Belgium; (3) HANWA Electronics Ltd., Wakayama, Japan

email: mirko.scholz@imec.be

Zusammenfassung – Mit und ohne anliegende Versorgungsspannung wurde eine Systemebene-ESD Schutzlösung für HVT IC-Pins untersucht. Die transiente Wechselwirkung des untersuchten SCRs mit den Komponenten auf Systemebene muss sorgfältig geprüft werden, um einen thermischen Ausfall des SCR zu verhindern, wenn keine Versorgungsspannung angelegt ist und Latchup, wenn der SCR eingeschaltet ist.

Abstract – A system-level ESD protection solution for HVT IC pins is studied without and with applied supply voltage. The transient interaction of the studied SCR with the off-chip components needs to be studied carefully to prevent a thermal failure of the SCR when no VDD is applied and latchup when the SCR is powered up.

1 Introduction Integrating high-voltage (HVT) circuitry into a standard low-voltage CMOS process is one of the challenging tasks when System-on-chip (SOC) solutions like line drivers, USB interfaces, display drivers etc are implemented. These HV-tolerant (HVT) IC pins operate at higher supply voltages (VDD) then the used low-voltage technology. Due to the higher VDD the classical ESD protection solutions of the used low-voltage process often do not work. Moreover additional challenges can occur. For example, due to the higher VDD there is a higher risk for latch up when the circuit is powered up.

In this paper, we demonstrate a system-level ESD protection methodology for HVT IC pins using a test board and board-level components together with an on-chip protection device on-wafer. With measurements and simulations the interaction between on-chip and off-chip devices is analyzed. The presented methodology enables the study of on-chip ESD protection devices under system-level ESD stress conditions and their interaction with board-level components even before IC packaging.

First, we present the test structure and measurement setup. In the following section the protection methodology for the non-powered state is demonstrated. Next we show how to protect the

selected test structure for the case that a supply voltage is applied to it, followed by some conclusions.

2 Test structure, test board and measurement setup

To study the system-level ESD robustness of HVT IC pins a standard Silicon-Controlled Rectifier (SCR), manufactured in a 130 nm CMOS technology, has been selected. The nominal supply voltages in this technology are 1.2 V and 3.3 V. Due to its high trigger voltage (~ 15.5 V) during ESD stress and the absence of a gate oxide it can be safely used as an ESD protection for HVT circuitry. Due to their known latchup sensitivity SCRs are usually not used as a standalone power clamp. In this study we use the SCR as a “latchup monitor” and thereby working as a replacement for a latchup sensitive circuit in a real application.

The SCR used is measured on-wafer. The probe needles and probe holder parasitic are extracted beforehand [1] and included in the analysis to determine the influence of the needle parasitic in the setup during ESD stress. Off-chip components are added to the SCR by connecting a dedicated double layer test board (Figure 1) to the on-wafer setup. The test board has been manufactured using an industrial PCB process and FR4 as board

material. The top layer contains the PCB traces and the footprints for required board components like capacitors, resistors and TVS diodes. The bottom layer works as ground plane connected with plated via to the top layer.

Figure 1: Photo of test board for systemexperiments; TVSx : TVS diode, Cxcapacitor, Rx: serial components (ESD resistor, ferrite bead), VDDx: optional supply voltage input, ESD_IN: input for ESD stress and supply voltage (optional), OUTx: output to wafer prober (SMA)

The used ESD stress sources are a TransmissionLine Pulse (TLP) and very fast (vf) TLPHANWA T-5000 for extracting the IV curves of the devices used. The system-level ESD stress source is a Human Metal Model (HMM) testerHANWA HED-W5000M. Next to current probes, a high impedance passive voltage probe is connected to the SCR in a KELVIN configuration to capture the transient behavior of the SCR during different stress conditions and with different off-chip configurations.

3 Power-off protection

3.1 Applying the SEED methodoIn white paper 3 [2] the Industry Council on ESD target levels proposed the so called Systemefficient ESD design (SEED) methodology for the design of off-chip ESD protections meeting system-level ESD specifications. suitable off-chip protection the TLP IV curves of the on- and off-chip ESD protection devices are captured and compared. If required additional offchip devices can be added to obtain the desired system-level protection level.

Figure 2 shows the 100 ns of the SCR and a selected off-chip ESD protection deviceapplications. The selected TVS diode turnsaround 6.2 V. It has a junction capacitance of 80 pF and a HMM/IEC61000-4-2 robustness of ±30 kV.

the PCB traces and the footprints for required board components like capacitors, resistors and TVS diodes. The bottom layer works as ground plane and is

via to the top layer.

: Photo of test board for system-level ESD

: TVS diode, Cx: decoupling : serial components (ESD resistor,

: optional supply voltage input, ESD_IN: input for ESD stress and supply voltage

output to wafer prober (SMA)

The used ESD stress sources are a Transmission-and very fast (vf) TLP tester

5000 for extracting the IV curves of level ESD stress

Human Metal Model (HMM) tester W5000M. Next to current probes,

a high impedance passive voltage probe is a KELVIN configuration

to capture the transient behavior of the SCR during different stress conditions and with

odology In white paper 3 [2] the Industry Council on ESD target levels proposed the so called System-efficient ESD design (SEED) methodology for the

chip ESD protections meeting To select a

chip protection the TLP IV curves of protection devices are

captured and compared. If required additional off-chip devices can be added to obtain the desired

shows the 100 ns of the SCR and a chip ESD protection device for 5 V

d TVS diode turns-on s a junction capacitance of

2 robustness of

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Figure 2: 100ns TLP and 5 ns vfTLPSCR and TVS diode(On-Semi ESD5Z5.0T1)

Because the TVS diode trigger voltage is much lower than the Vthe TVS diode should shunt the systemstress current until 5.4 A without triggering the SCR. At higher current leveland goes into snapback TVS diode. At the moment of snapbackcurrent through the SCR is much higher than theTLP failing current and thermal will occur.

However, HMM measurements on thedevice with the TVS diode in parallel show different results. Already at low stress level the SCR turns on. Figure 3 shows the current through the SCR device at a HMM with the TVS diode in parallel(region A) of the HMM current is conducted mainly by the TVS diode.

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Figure 3: Measured HMM stress current and current through SCR at SCR region A: 1st pulse, region B: 2

At low stress level the TVS diode turnsthe 2nd pulse (region B) flows mainly through However at higher stress level the shared between the SCR and TVS diodeindicating a turn-off of the TVS diodeduration of the HMM current.

10 15 20

SCRTVS

Voltage [V]

VT1 SCR

and 5 ns vfTLP IV curves of Semi ESD5Z5.0T1)

Because the TVS diode trigger voltage VT1 (6.2 V) VT1 of the SCR (15.5 V)

the TVS diode should shunt the system-level ESD A without triggering the

At higher current level the SCR will trigger snapback thereby turning off the

At the moment of snapback the current through the SCR is much higher than the

thermal failure of the SCR

measurements on the SCR device with the TVS diode in parallel show

. Already at low stress level the shows the current through

HMM stress level of 500 V TVS diode in parallel. The 1st pulse

HMM current is conducted

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: Measured HMM stress current and current through SCR at SCR trigger level (0.5 kV);

pulse, region B: 2nd pulse

the TVS diode turns-off before (region B) rises and the 2nd pulse

the SCR (Figure 4). However at higher stress level the 2nd pulse is shared between the SCR and TVS diode

of the TVS diode after the duration of the HMM current.

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Figure 4: Currents at 30 ns: measured HMM stress current and current through SCR; calculated current through TVS diode

The triggering of the SCR already at low HMM stress level cannot be explained using only the SEED methodology. Transient information like for example the voltage overshoot of the TVS diode is required in addition to the TLP IV data. Figure 5 shows the vfTLP IV data of the standalone TVS diode extracted with two different averaging windows.

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Figure 5: vfTLP IV testing (pulse width: 2 ns; rise time: 200 ps) of standalone TVS diode: definition of averaging windows (a) and extracted vfTLP IV curves (b); averaging window I (0.3 ns to 0.6 ns) and II (1.7 ns to 1.9 ns)

Averaging window I is defined at the beginning of the vfTLP pulse. Voltage and current have a more transient character. Averaging window II is

defined at the end of the vfTLP pulse where voltage and current are more quasi-static.

The vfTLP IV curve extracted with averaging window I reaches already at low vfTLP stress level (1.6 A) the VT1 of the SCR. This agrees well with the measured HMM peak current (1.65 A) at the SCR trigger level. By adding this transient information the SEED methodology can be extended with data which is required to fully understand the interaction between on-chip and ESD off-chip protection device.

The SCR triggering already at low stress level impacts the system-level ESD robustness of the device when the TVS diode is placed in parallel. The expected failure level from the SEED methodology and by using the relation established in [3] would be 2.9 kV. However the real failure level with added TVS diode is only 2.1 kV (Table 1).

Table 1: Failure level of standalone SCR and SCR with TVS diode in parallel (no VDD applied)

HMM [kV] SCR standalone (measured) 1.4 SCR with TVS (measured.) 2.1

SCR with TVS (predicted by SEED)

2.9

Most of the 2nd pulse current goes through the SCR and only a smaller part is conducted by the TVS diode. At a HMM stress level of 2.1 kV, the residual current through the SCR causes thermal breakdown (Figure 6).

Figure 6: Current through SCR with and without TVS diode in parallel; stress level: failure level

Similar to the triggering of the SCR at low stress level the sharing of the 2nd pulse current at higher stress level between SCR and TVS diode cannot be explained by the SEED methodology. HMM simulations are required which are demonstrated in the following section.

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3.2 Transient analysis with SPICE simulations

3.2.1 Simulation setup To study the transient behavior of on- and off-chip protection devices SPICE simulations are carried out with LTSPICE (Figure 7).

HMM

tester

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probe

needles

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ITVS ISCR

Figure 7: Simulation setup for transient analysis; IHMM – HMM current, ITVS – current through TVS diode, ISCR – current through SCR

The HMM tester is modeled according to [4]. The TVS diode is modeled with a standard SPICE model based on the datasheet and TLP data. To approximate and model the overshoot of the TVS diode an inductance is added in series and its value matched to measurement data obtained from the standalone TVS diode mounted in the test board. This simplification is used because the TVS diode consists of only one physical diode and it is used in reverse mode.

Figure 8 shows the voltage across the TVS diode during simulated and measured HMM stress. Similar current and voltage waveforms are obtained with the simulated TVS model.

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Figure 8: Current through (a) and voltage (b) across the TVS diode, comparison measurements and simulations; stress level: 1 kV

The SCR is modeled by modifying a SPICE model of a commercial discrete SCR. This behavioral model contains information like the trigger behavior, on-resistance and holding current and gives a good approximation of the real device behavior in the transient domain.

Figure 9 shows the simulated and measured voltage across the SCR. Measurement and simulation data include the parasitic of the probe needle and probe needle holder. A good agreement for the voltage after snapback is obtained. The overshoot before device snapback in the simulation is significant higher. This is attributed to bandwidth limitations of the voltage probe used during the measurement.

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Figure 9: Voltage across standalone SCR; comparison simulation and measurement; stress level: 0.5 kV

To verify the accuracy of the simulation setup, first the SCR triggering is simulated with the TVS diode in parallel. In Figure 10a the current through the SCR is shown for the stress level when the SCR turn on. In Figure 10b the current through the SCR at a higher stress level is plotted. For both stress level a good agreement between simulation and measurement is obtained.

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Figure 10: Current through SCR with TVS diode in parallel: a) stress level: 0.5 kV, b) stress level: 1.5 kV; comparison between measurement and simulation; no VDD

3.2.2 Transient analysis For the transient analysis different pre-charge voltages are simulated and the voltages and currents at different locations in the schematic are extracted. Figure 11 shows the voltage across the TVS diode and across the SCR for two pre-charge voltages. The TVS turns-off at low stress level (Figure 11a). The low holding voltage of the SCR and the voltage across the probe holder and probe needle parasitic are not high enough to keep the TVS diode on. More voltage drops at a higher stress level keeping the TVS diode also on during the duration of the 2nd pulse of the HMM current (Figure 11b).

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(b)

Figure 11: Simulated voltages across TVS diode and SCR: (a) stress level: 0.5 kV, (b) stress level: 1.5 kV

The current distribution between the SCR and TVS during HMM stress is directly influenced by this device behavior. Figure 12a shows the current through TVS diode and SCR when the TVS diode turns off during the duration of the HMM pulse. Only the 1st pulse of the HMM current is conducted by the TVS diode. The 2nd pulse is fully conducted by the SCR.

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Figure 12: Simulated currents through TVS diode and SCR: (a) stress level: 0.5 kV, (b) stress level: 1.5 kV

Figure 12b shows the current distribution when the TVS diode stays on during the 2nd pulse. The 1st pulse and the 2nd pulse are shared between SCR and TVS diode.

The obtained results clearly show why the SEED methodology cannot be used. Depending on the

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applied HMM stress the TVS diode can be turned off by the SCR snapback or stays on during the duration of the HMM stress. HMM simulations or measurements are required to fully explain this device behavior.

3.3 Designing the system-level ESD protection

An additional current limiting resistor is required to limit the residual current through the SCR to a safe value. The methodology in [5] is used to calculate the required resistance value for the peak current of 8 kV HMM. The safe current level is taken at 2 A for the SCR. With this data, the on-resistance of TVS diode and SCR and by applying Kirchhoff’s current laws a resistor value of about 7.3 Ω is obtained. The closest available value in the lab was 8.2 Ω. With the added isolation resistor the residual current through the SCR stays at a safe level even at 8 kV HMM stress (Figure 13).

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Figure 13: Current through standalone SCR (failing waveform) and with added TVS diode and ESD resistor

4 Power-on protection To study the behavior of the protected SCR under powered conditions a typical decoupling capacitor (SMD1206, thick film, 1 µF) and a VDD source (Agilent E3136A) with an additional 75 V discrete zener diode as blocking device are added to the setup (Figure 14). For all power-on testing the VDD is set to 5 V and the VDD compliance to 100 mA.

Figure 14: Setup for power-on testing [6]

At a HMM stress level of 800 V the SCR triggers and goes into latchup (Figure 15 a). This is indicated by a sudden drop of the supply voltage and a strong increase of the supply current. The fast rise time of the HMM current together with the intrinsic inductance of the capacitor used cause a voltage overshoot which is not suppressed fully by the TVS diode.

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Figure 15: Measured voltage across (a) and current (b) through SCR before and during latchup

After turn-on the SCR snaps back to its holding voltage. Due to the low on-resistance after snapback the SCR conducts part of the HMM current and an additional current which is discharged from the decoupling capacitor (Figure 15 b). Due to its low holding current of 25 mA the additional discharge current keeps the SCR in the latched state even when the HMM current is fully decayed. Over a longer time scale the SCR continues staying in the latched state due to a permanent current flow from the power supply to the board which is sourced by the power supply to restore the programmed supply voltage.

4.1 SPICE simulation setup for transient analysis

To analyze the interaction of the on-chip and off-chip components under powered conditions, SPICE simulations are carried out. The setup in section 3.2 is extended with the components which are required for the powered ESD testing (Figure 16).

Figure 16: Schematic of power-on simulation setup in SPICE

The zener diode is modeled with the same breakdown voltage (75 V) like during measurements. The decoupling capacitor is modeled with its equivalent model which consists of the intrinsic inductance, the parasitic resistance and the capacitance value.

To verify the power-on simulation setup the latchup situation is simulated. Figure 17 shows the simulated voltage across and the current through the SCR before and during latchup. In the simulation the SCR latches at the same HMM stress level like in the measurements proving the accuracy of the simulation.

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Figure 17: Simulated voltage across SCR before and during latchup; VDD = 5 V

With the simulation setup the current distribution between the off-chip components is extracted. Below the latchup trigger level (Figure 18a) most of the HMM current is conducted by the decoupling capacitor. Only a small part of the 1st pulse is conducted by the TVS diode. During latchup (Figure 18b) the SCR triggers. When reaching its holding voltage the SCR and decoupling capacitor share first the HMM current. After the decay of the HMM current the discharge current from the decoupling capacitor keeps the SCR on. The negative current in Figure 18 b indicates this current which flows from the capacitor through the latched SCR.

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Figure 18: Simulated currents before and during latchup: HMM current, current through decoupling capacitor and TVS diode

4.2 Designing the system-level ESD protection for the power-on state

Going into latchup during ESD stress is not allowed for ESD power clamps. Therefore the design target for the power-on state is to prevent triggering and subsequent latching of the SCR at a HMM stress level of 8 kV. The SCR in this case study is used as a latchup monitor. Therefore the latchup protection will be demonstrated with board level components only.

By using the presented SPICE simulation setup a protection solution preventing SCR triggering is designed. The proposed solution (Figure 19) consists of a ferrite bead which is added between the TVS diode and one decoupling capacitor.

Figure 19: Protection solution with ferrite bead and RC filter; RISO: 8.2 Ω; Cdecoup: 1 µF; ferrite bead: Tyco Electronics BMB1-J0070-B08

Ferrite beads are passive components which block high frequency noise in supply lines. The use of ferrite beads for preventing latchup has been

proposed before [7]. However, a design methodology was not given.

The isolation resistor together with a second decoupling capacitor works as a RC filter. It directs most of the HMM current through the first decoupling capacitor leaving only a small residual current for the TVS diode, ferrite bead and second decoupling capacitor (Figure 20). When simulating the presented design no latchup occurs at a stress level of 8 kV HMM.

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Figure 20: Simulated voltage across SCR and current through first decoupling capacitor (C1) when SCR is protected with presented protection solution and powered-up to 5 V; stress level: 8 kV

Figure 21 shows the experimental verification of the protection solution. At a HMM stress level of 8 kV and a supply voltage of 5 V no latch up in the SCR occurs.

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Figure 21: Measured voltage across SCR when protected with presented protection solution and powered-up to 5 V, HMM stress level: 8 kV

All components of the proposed protection solution are typically used to decouple and stabilize the voltage in supply lines and do not add any additional devices to the bill of material of a application board.

5 Conclusions A system-level ESD protection solution for HVT IC pins has been studied without and with applied supply voltage. It has been found, that the

transient interaction of the studied SCR with the off-chip components needs to be carefully studied to prevent any low failure level of the SCR when no VDD is applied and moreover to prevent latch up when the device is powered up. It was demonstrated that the SEED methodology needs transient information in addition to the TLP IV data to ensure a protection design which takes also into account the transient interaction of on-chip and off-chip ESD protection with other board-level components.

By using a SPICE simulator together with suitable models for all on-chip and off-chip components an ESD protection solution for the power-on state during system-level ESD stress has been designed and experimental verified.

Literature [1] M. Scholz et al., “Calibrated wafer-level

HBM measurements for quasi-static and transient device analysis”, in Proc. EOS/ESD Symposium, 2007, pp. 89–94

[2] “White Paper 3 - System Level ESD, Part I”, Industry Council on ESD Target Levels, 2011

[3] G. Notermans et al, “HMM and TLP Correlation”, IEW, 2011

[4] M. Scholz et al, “On-wafer Human Metal Model measurements for systemlevelESD analysis”, Proc. EOS/ESD Symposium, 2009, pp. 405–413

[5] S. Marum et al, “Protecting circuits from the transient voltage suppressor's residual pulse during IEC 61000-4-2 stress”, Proc. EOS/ESD Symposium, 2009, pp. 377-386

[6] M. Ker et al, “Component-Level Measurement for TLU under system-level ESD considerations”, IEEE Trans. on Device and Materials Reliability, 2006, Vol. 6, No. 3, pp. 461-472

[7] Hsu et al, “Study of board-level noise filters to prevent transient-induced latch-up in CMOS integrated circuits during EMC/ESD test”, in Proc. International Zurich Symposium on EMC, 2006, pp. 533-536