analog ic layout 1 1385
TRANSCRIPT
Workshop on Fully Layout Technology 2002 / 03 / 23
林正松 / 矽拓科技有限公司
主講㆟:林正松主講㆟:林正松主講㆟:林正松主講㆟:林正松
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THE ART OF ANALOG LAYOUT
Workshop on Fully Layout Technology 2002 / 03 / 23
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前言前言前言前言
• 瞭解Analog佈局元件• 熟悉analog matching guide• 適當技巧性的放置• Design 與 layout 的共識
Workshop on Fully Layout Technology 2002 / 03 / 23
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ANALOG LAYOUT
• CMOS ANALOG LAYOUT
• BIPOLAR ANALOG LAYOUT
• BICMOS ANALOG LAYOUT
Workshop on Fully Layout Technology 2002 / 03 / 23
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CMOS ANALOG LAYOUT• CMOS Component Layout Guide
• CMOS Layout Application• Transistor• Capacitor• Resistor• Bipolar• Mos power transistor
• CMOS Layout Case Study
Workshop on Fully Layout Technology 2002 / 03 / 23
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s G D S G D
CMOS LAYOUT STRUCTURE
LV NMOS:(poly)&(active)&(nplus)&(psub)
LV PMOS:(poly)&(active)&(pplus)&(nwell)
Workshop on Fully Layout Technology 2002 / 03 / 23
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Asymmetric HV12V Device LayoutCMOS LAYOUT STRUCTURE
NMOS PMOS
N+
HV
POLYN+N++DIFF
DRAIN GATESOURCE DRAIN GATE SOURCE
CONTACT
NWELLP+POLY
PDD
HV
P+
MT1
DIFF
Workshop on Fully Layout Technology 2002 / 03 / 23
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Asymmetric HVP30V Device LayoutCMOS LAYOUT STRUCTURE
PMOS NMOS
DRAIN GATE SOURCE
DIFF
POLYHPF+BL
P+
HV
CO
NWELL+BLNWELL+HPF
POLYN+
HV
DIFFDRAIN GATE SOURCE
LL
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CMOS-RESISTOR LAYOUT STRUCTURE
>>Diff Resistor
>>Poly register >>Nwell ResistorCONTACT
DIFF
POLY1
NWELL
Ndiff
DUMMY DUMMY
NWELL
P+
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1、P1-P2 LAYOUT STRUCTURE
2、MOS LAYOUT STRUCTURE
poly1
M1
CO
POLY2M2
poly1
P+CO
N+
DIFF
CMOS-CAPACITOR LAYOUT STRUCTURE
Workshop on Fully Layout Technology 2002 / 03 / 23
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CMOS-CAPACITOR LAYOUT STRUCTURE3、MIN TOPMETAL 與 TOPMETAL-1之間加-MINLAYER
4、METAL POLY STRUCTURE
M5M4
VIA4
MIM
NWELLCONTACT
TOP=M1+M3BOTTOM=POLY1+M2
Workshop on Fully Layout Technology 2002 / 03 / 23
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CMOS-PNP LAYOUT STRUCTURE
NWELL
CONTACT
DIFFM1
P+
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CMOS-FUSE LAYOUT STRUCTURE
STYLE -3STYLE-1 STYLE-2
METAL FUSE POLY1 FUSE POLY1 FUSEM1
POLY1CONTACT
PASS
CONTACT
M1
POLY1
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CMOS LAYOUT APPLICATION -TRANSISTOR
>>MOS Matching Mirror M2
VIA
M1
CONTACT
P+
DIFFPOLY
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CMOS LAYOUT APPLICATION -TRANSISTOR>>交叉對稱(1)
OUT P
OUT N
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>>交叉對稱(2)
CMOS LAYOUT APPLICATION -TRANSISTOR
DUMMY POLY
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CMOS LAYOUT APPLICATION-CAPACITOR
DUMMY
>>Unit Capacitor
DUMMY
Well contact
poly
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CMOS LAYOUT APPLICATION-CAPACITOR
>>Unit Capacitor –Input Stage Matching
POLY1
POLY2
M1
WELL CONTACT
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CMOS LAYOUT APPLICATION-RESISTOR
>> Normal Resistor-兩端拉出即可兩端拉出即可兩端拉出即可兩端拉出即可
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CMOS LAYOUT APPLICATION-RESISTOR
>>Crocess ResistorM2 VIA WELLCONTACT
CONTACT
POLY
M1
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CMOS LAYOUT APPLICATION -RESISTOR>>交叉對稱
DUMMYDUMMY
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CMOS LAYOUT APPLICATION –PNP X 10
NWELLP+N+
P+
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CMOS LAYOUT APPLICATION –PNP X 9
NWELL
P+
P+
N+
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CMOS LAYOUT APPLICATION-Power MOS Transistor(1)
ESD PROTECTION 佈局方式不影響面積 面積效益是最好ESD PROTECTION 能力差㆒點
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CMOS LAYOUT APPLICATION –Power MOS Transistor(2)
阻抗考量,正方面型最好N+ DIFF NWELL
P+ DIFF
POLY
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CMOS LAYOUT APPLICATION- Power MOS Transistor((((3))))
N+DIFFP+DIFF
NDIFF
POLY
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CMOS LAYOUT APPLICATION –Power MOS Transistor((((4))))
>>M2 Finger Structure
M2
M1
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CMOS LAYOUT CASE STUDY >>OP1
NWODP+
N+P1P2
COM1
VIAM2
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CMOS LAYOUT CASE STUDY>>OP2
6 5
5 6
44 24 3
3 41
7 78 8
IP
IN
NWODP+N+P1P2COM1
VIAM2
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CMOS LAYOUT CASE STUDY-CIRCUIT
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BIPOLAR ANALOG LAYOUT
• BIPOLAR Component Layout Guide
• BIPOLAR Layout Application
• BIPOLAR Layout Case Study
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BLDCSPSNCOM1
VIAM2TOCAPIR
BIPOLAR LAYOUT STRUCTURE-VNPN
STYLE-1 STYLE-2
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BLDCSPSNCOM1
VIAM2TOCAPIR
BIPOLAR LAYOUT STRUCTURE-LPNP
STYLE-1 STYLE-2 STYLE-3
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BIPOLAR –CAPACITOR LAYOUT STRUCTURE
MT1
BIPOLAR-RISISTOR LAYOUT STRUCTURE
IR SP
>>Sn-cap type
cap
BL
SN
TO
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BIPOLAR LAYOUT APPLICATION-VNPN
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BIPOLAR LAYOUT APPLICATION-LPNP
STYLE-1 STYLE-2
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BIPOLAR LAYOUT APPLICATION-LPNP
STYLE-3
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BIPOLAR LAYOUT APPLICATION-Power Transistor
EMIT 面積效應最大 電流平均分散 讓熱不會集㆗
矩型 工字型
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BIPOLAR LAYOUT APPLICATION-VNPN增加EMIT的周長,提昇趨動能力
梯型
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BIPOLAR LAYOUT CASE STUDY
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BIPOLAR LAYOUT CASE STUDY -CIRCUIT
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BIPOLAR LAYOUT CASE STUDY
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BICMOS ANALOG LAYOUT
• BICMOS Component Layout Guide
• BICMOS Layout Application
• BICMOS Layout Case Study
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BICMOS LAYOUT STURCTURE
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BICMOS LAYOUT STURCTURE-VPNP
DIFF PW
P+
CONTACT
NWELL
N+
>>Double Base
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BICMOS LAYOUT STURCTURE-LPNP
PDIFF
NDIFF
NWELL
N+BL
POLY
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BICMOS LAYOUT STURCTURE-VNPN
>>Double Base-降低Base 阻抗
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BICMOS LAYOUT STURCTURE-RESISTOR
>>Base Resistor >>P2 resistor>>P1 resistor
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BICMOS LAYOUT STURCTURE
>>SNK Capasistor >>P1-P2 Capasistor
N+BLNWELLN+INP
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BICMOS LAYOUT APPLICATION-VNPN
>>交叉對稱
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BICMOS LAYOUT APPLICATION-VNPN增加Driver 趨動能力,節省面積
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BICMOS LAYOUT CASE STUDY-CASE 1>>OP1
R2R2
R2R2
R2 R2 R2 R2
M5 M5
M1
M3
M3
M4
M4
M2
R1 R1 R1 R1 R1
DU
MM
Y
DU
MM
Y
Q2 Q1
Q2Q1
INIP
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BICMOS CASE STUDY –OP CIRCUIT
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BICMOS LAYOUT CASE STUDY-CASE 2AMP
G1
DU
MM
YD
UM
MY
DU
MM
YD
UM
MY
DU
MM
Y
DU
MM
YD
UM
MY
DU
MM
YD
UM
MY
DU
MM
Y
DU
MM
YD
UM
MY
DU
MM
YD
UM
MY
COLLECT
IN
M7
Q2 Q1Q3
R1 R1
R1 R1 R1 R2 R3
R1 R1 R1 R1 R1 R1 R1 R2
R1 R1 R1 R1 R2 R2 R2 R2
R4 R3 R4 R3
R3 R4 R3 R4
R3
M6M6
M4M5
M1M1
M1M1
M5M4
M6M6
M3M2
M2M3
M2M3
M3M2
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BICMOS CASE STUDY –AMP CIRCUIT