em microelectronic offers alp018 for mpw service through cmp · 2019-02-13 · 21 cpnw18...
TRANSCRIPT
V20140310-01
EM MICROELECTRONIC offers
ALP018 for MPW service through CMP
Christian Terrier
ALP018 : Analog Low Power
180nm process, optimized for
Analog and Low Voltage Designs
CMP Seminar Paris - Feb 7th 2019
V20140310-01
Creating integrated Circuits since
CMP Seminar Paris - Feb 7th 2019
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ProductsSensor Fusion & Sensor Interface
Power Management
Microcontrollers
Supervisory
Wireless / RF
Timing
RF Identification & Security
Display & Touch
Know-HowASICS
Capacitive Tactile
Electronic Modules
IC Production
RF Communication
Ultra-Low Power
Low Voltage
Non-Volatile
Memory
Display Technology
Sensor Interfaces
ApplicationsAutomotive
Displays
Healthcare & Sports
Identification
Industrial
Mobile Communication
Tablet & PC Peripherals
Watchmaking
CMP Seminar Paris - Feb 7th 2019
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Colorado Springs, USA
Prague, Czech Republic
Marin, Switzerland
Bangkok, Thailand
CMP Seminar Paris - Feb 7th 2019
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– Down to 110nm in production
– 180 nm is the actual main stream technology.
– Low cost 2-3um/Pwell CMOS still running after 30 years !
– Tailored components for analog in all processes.
– NVM (EE or Flash) in all processes (trimming, storage)
– EKV accurate models for near/sub Vth operations
– Characterized libraries for low voltage.
CMP Seminar Paris - Feb 7th 2019
V20140310-01
Let’s start with ALP018 Logic process (the easiest to use),
– A process developed and optimized “in house for” :
• Low current (nA bias), Low voltage operations (down to 0.4V)
• Analog Designs (low leakage, low noise, pairing)
• Mixed Signal (100kGates/mm2)
– EKV models with parameters for near/sub Vth operations
– Analog components (MOS, Bip, R, C, diodes) with models.
– Digital cell library optimized for Low Power/Low Voltage
– I/O pads library with low leakage ESD protections.
– Design Kit built around the Cadence Framework
– Use of Synopsys for Digital flow (100kGates/mm2)
CMP Seminar Paris - Feb 7th 2019
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• Cadence Virtuoso Version 6.1.7_ISR20 ( Open Access )
• ADE Explorer & Assembler
• Virtuoso Schematic Composer & Virtuoso Layout Editor
• Spectre & APS Simulators Version 16.10.ISR4
• Incisive Version 15.20.026
• Physical Verification : PVS Version 16.12
• Parasitic extractions : QRC Version 17.21
• Synopsys : CustomSim XA, Design + Power + DFT Compilers
• Cadence Innovus
• Synopsys PrimeTime
CMP Seminar Paris - Feb 7th 2019
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APL018 : a 180nm process optimized and dedicated to :
- Analog and Mixed Signal designs
- Low Power and Low Voltage
- Accurate models for near for Threshold operations
- OK for small digital parts (100kGates/mm2)
- Developed and Manufactured in Europe
- Development teams are “under the same roof” :
- Process, Models, Design kit, Designers
CMP Seminar Paris - Feb 7th 2019
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Thank you for your attention
Happy to have you as future users
Any question ?
CMP Seminar Paris - Feb 7th 2019
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1 N18 N mos 1.8V
2 N33 N mos 3.3V
3 NLVT18 Low Vt Nmos
4 NAT18 Native 1.8V
5 NAT33 Native 3.3V
6 P18 Pmos 1.8V
7 P33 Pmos 3.3V
8 PLVT18 Low Vt pmos
9 N18_OCT Octagonal N mos 1.8V
10 NLVT18_OCT Octagonal Low Vt Nmos
11 P18_OCT Octagonal Pmos 1.8V
12 PLVT18_OCT Octagonal Low Vt Pmos
N33_ESD ESD Nmos 3.3V
BIP Vertical PNP
CMP Seminar Paris - Feb 7th 2019
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10 RHRPO HR poly resistor
11 RNND Ndiff resistor
12 RNNPO N+ poly resistor
13 RNPD Pdiff resistor
14 RNPD33 Pdiff resistor
15 RNPPO P+ Poly resistor
16 RSPPO Sallicied poly
17 RNW18 Nwell resistor 1.8V
18 RNW33 Nwell resistor 3.3V
19 RM1/2/3/4/5/6 Metal resistors
OTHER
PROBE Probe point
CMP Seminar Paris - Feb 7th 2019
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20 CN18 Mos cap
21 CPNW18 Poly/Nwell 1.8V
22 CPNW33 Poly/Nwell 3.3V
22 CMIM_1F5 MIM Cap
23 CCOMB Double poly
25 DIONW Nwell diode
26 DN18 N+/sub 1.8V
27 DN33 N+/sub 3.3V
28 DP18 P+/sub
29 MVNWSY MV Nwell Schottky
CMP Seminar Paris - Feb 7th 2019