school of microelectronic engineering emt362: microelectronic fabrication thin gate oxide – growth...

School of Microelectronic Engineering

EMT362: Microelectronic FabricationThin Gate Oxide – Growth &

Reliability

Ramzan Mat AyubSchool of Microelectronic Engineering


Lecture Objectives

• Understand the importance and requirement of thin gate oxide

• Able to describe the tecnique to grow high quality thin oxides

• Understand the nature of Mode-A,B &C of breakdown failure

• Able to calculate the oxide strength, τBD and QBD


Gate Oxide

GATE

Gate Oxide

L

n+ n+ID

P-well

)(2

VthVgsL

WCI oxnD

oxox

t

AC


Gate Oxide Requirements

• Possible to grow thin oxide precisely and uniformly across the wafer

• Adequate reliability characteristics under operating conditions in terms of strength (Breakdown Voltage), Reliability of operation over specified time (τBD, QBD) and resistance to hot-carrier degradation)


Desired Gate Oxide Characteristics

• The thickness closely match the specification in MOSFET design

• Uniform across the wafer, from wafer to wafer, run to run.

• Small interface charge

• High dielectric strength

• Long lifetime under normal operating conditions

• High resistance to hot-carrier damage


Technology of Thin Oxide Growth

1. Oxidation furnace

Vertical furnace is more favourable compared to horizontal.3 reasons

• Wafer/wafer holders make no contact with oxidation tube during loading, growth and unloading (fewer particles generated).• Lighter boat material can be used, as a result, better heat and gas distributions (result in better oxide uniformity).• Precise control of wafer to wafer spacing.



2. Control of Growth Rates• Slow growth rates required to reproducibly grow thin oxides with precise thickness.

• Grow in dry O2 at atmospheric pressure at lower temperatures (800-900C).• Growth at reduced total pressure, or reduced O2 partial pressure



Typical Thin Gate Oxide Process

1. Carried out in vertical furnace2. Prior to oxide growth;

1. Grow and strip sacrificial oxide (to remove defect in silicon layer)2. Cleaning procedure (normally generic of RCA cleaning)

3. Loaded by robotic wafer handling at specific insertion rates ~ 15 cm per minute for 150mm wafer, 10cm per minute for 200mm wafer. Furnace temperature ~ 650 – 700C.4. Furnace temperature is ramped up to the growth temperature. During temperature ramp up, N2 or Ar is purged to prevent unwanted growth.5. Temperature stabilization around 5 min before O2 is released.



Typical Gate Oxide Process

6. Dry oxidation at atmospheric pressure at temperature ~ 800-900C. Some companies use dry/wet/dry to control the thermal budget. Others use HCl, TCA , DCE as chlorine source. 7. Wafers subjected to Post Oxidation Annealing (POA) in N2 at + ~100C. The purpose is to minimize the interface trap density by neutralizing the dangling bond of Si with H atoms. This will improve the τBD and QBD.8. Furnace temperature is ramped down, and wafer is unloaded at certain rate.


Gate Oxide Characterizations

1. Gate oxide Strengtha) Breakdown voltage, then calculate the breakdown electric field.

2. Gate Oxide Reliabilitya) τBD – time to breakdownb) QBD – charge to breakdown


Gate Oxide Strength

Definition – The maximum electric field strength that can be applied to the oxide before it breaks down. Unit MV/cm.

Test procedure – Ramped Voltage Test using MOS capacitor


GATE

Gate Oxide

substrate

T1

T2

• Ramp voltage between T1 and T2, measure current• Take the voltage at the voltage drop as the breakdown voltage (VBD)• Calculate the oxide strength by VBD / oxide thickness

V

t

Ig

VVBD


Example

Thin oxide of 500A is stressed under voltage ramp test until it breaks at 8 V. Calculate the oxide strength.

Oxide strength = Breakdown voltage / oxide thickness

= 8 V / 500e-8 cm

= 1.6e6 V/cm

= 1.6 MV / cm


Mode of Breakdown FailureA histogram is usually used to plot the results of the ramped-voltage tests(oxide strength) of a group of oxide samples (normally up to 1000 capacitortested to characterized certain oxidation process recipe)

Breakdown Field, MV/cm

BreakdownFrequency

5 10

Mode-A (<1 MV/cm)

Mode-B (2-6 MV/cm)

Mode-C (8-12 MV/cm)


Mode-A

• Fail instantly upon the application of a small gate bias.• Its believed that this oxide may experienced a gross defect such as pinholes and may already be shorted before the application of low strength field.


Mode-B

• Fail at electric field of intermediate strength (2-6 MV/cm)• Contain weak spots that do not produce instant shorting, but may give rise to early failures of ICs under normal operating conditions.• Majority of oxide breakdown failure in sub-micron CMOS fall under this category. Mostly due to the defects exist in the oxide. • Defects include;

• Sodium contamination – originated from W furnace filamen, chemicals• Metal contamination – from substrate, other processes• Surface roughness at Si-SiO2 interface from etching or cleaning procedures – promote localize weak spot• Non-uniformity of oxide growth• Crystalline defect – defect originated during crystal growth


Mode-C

• Can withstand the highest electric fields (8-12 MV/cm)• Failure mechanism always referred as intrinsic failure.• Generally assumed as defect-free oxide.• Several models proposed to explain the intrinsic breakdown

• Holes generation and trapping model.Electrons are injected into the conduction band of oxide by FN tunneling. In the oxide, these electrons are accelerated towardsthe gate, and generate electron-hole pair in the oxide. These generated holes are trapped at the localized areas and in return trappositive oxide charge. This will increase the positive charge atcertain point in the oxide, causing the tunneling current densityto increase there up to critical point where the breakdown occurs.

• Wolters Electron Lattice-Damage Model


Gate Oxide Reliability

Gate oxide strength is not directly relevant to the normal device operation, since what is really needed is how long the thin oxide willsurvive at lower field strength.

The measurement of oxide performance at lower electric field iscalled Time-Dependent Dielectric Breakdown (TDDB).

• Time to Breakdown under Constant-Voltage Stressing (τBD)• Time to Breakdown under Constant-Current Stressing (τBD)• Charge to Breakdown (QBD)


Time to Breakdown under Constant-Voltage Stressing

Electric field in the oxide is held constant (voltage is held constant)during the stress test. The length of time, τBD elapsed until breakdownoccurs is then measured.


Time to Breakdown under Constant-Current Stressing

Current is injected into the oxide by Fowler- Nordheim tunneling, andthis value Iinj is held constant. Voltage and time are recorded untilbreakdown occurs.


Charge to Breakdown

In a constant current test;

QBD = Jinj . τBD

In a constant voltage test;

BD

injBD dtJQ

0

.


Emperical Model to Estimate Oxide Reliability

Applicable to Mode-B and Mode-C Failures

1. QBD for intrinsic oxide is approximately constant for small FN tunneling current.2. Qp (hole charge to breakdown) also constant. Qp = JgατBD

]/)([)( exp0 oxBD TGT Where at 300C 1110 e sec G=350 MV/cm

)](/)()/(350exp[(sec)111)300( cmVcmtcmMVeK oxoxBD


Example

Calculate the time-to-breakdown, τBD at 300K of 8nm defect free gate oxide, use in CMOS technology with Vcc 5.0V.

τBD (300K)= 1e-11 (sec) exp 350e6 . Tox / Vox

= 1e-11 . exp 350e6 . 8e-7 / 5.0

= 2 e 13 sec


Example

Calculate the minimum thickness of a defect free oxide that could be used in a MOSFET that is to operate at 5.5V for 10 years at 150 C (425K) w/out suffering oxide breakdown. Given G(425K)= 283 MV/cm andΤ0 (425K)=0.75e-11 sec.

τBD for 10 years ~ 3e8 sec

tox min = 88 Å

school of microelectronic engineering emt362: microelectronic fabrication thin gate oxide – growth...

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