EE457 Instructor: G. Puvvada

Homework #7 (Virtual Memory) Due: Please check on the BB

Part Ia, Part Ib, and Part Ic are based on the textbook questions/figures. These are detailed inthe first five pages. The rest of the parts are from the previous ee457 midterm/final exams. These questionsare attached after the Part I questions.

Part II Question 3 from Spring 1994 Final exam

Part III Question 5 from Fall 1995 Final exam

Part IV Question 5 from Spring 1999 Midterm exam

Part Ia Exercises from the third edition of the textbook. Problems 7.39(7.32), 7.40(7.33) reproduced below for your convenience. Note: The exercise numbers in parentheses are the corresponding second edition exercise numbers.

7.39 Consider a virtual memory system with the following properties:

- 40-bit virtual byte address- 16 KB pages- 36-bit physical byte address

What is the total size of the page table for each process on this processor, assuming that the valid, protection, dirty, and use bits take a total of 4 bits and that all the virtual pages are in use?(Assume that disk addresses are not stored in the page table.).

Note for EE457 students: Show your answer in this rectangle together with your calculations/explanation. If the page table entry is a little less than 32 bits, allocate 32-bit word for the entryas it would be difficult to deal with say 29-bit wide table. Also assume that it is a single level table.

EE457 Homework #7 Page 1 / 12C Copyright 2004 Gandhi Puvvada

7.40

Assume that the virtual memory system of Exercise 7.39 is implemented with a two-way set-associativeTLB with a total of 256 TLB entries. Show the virtual-to-physical mapping with a figure like Figure 7.24on page 525. Make sure to label the width of all fields and signals.

Note to EE457 students: It is best to show an arrangement similar to the figure on page 7-55 of theclassnotes.For this exercise 7.40(7.33), while you could use either the figure 7.25 on page 593 of the second editionor figure 7.24 on page 525 of the third edition (which are later reproduced in part Ic of this homework),we prefer that you refer to the figure on Intel i860 TLB arrangement 7-45 of the classnotes mainly becausethe TLB uses set associative mapping. Also look at page 7-12 of the classnotes to arrive at how manyRAMs of what size are need to build the TLB. Show what portion of the virtual address is used to indexthese RAMs. Show comparators in a fashion similar to page 7-55 of the class notes. Answer in the rectan-gle below.

Virtual Address VA[39:0]

VA39 VA0

PA35 PA0

Physical address PA[35:0]

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EE457 Homework #7 Page 3 / 12

Part Ib - Relation between Cache, TLB and the Page Table

Reproduced below is the Figure 7.26 on page 527 from the 3rd edition of your textbook (figure 7.27 on page 595 of the 2nd edition).

Ib.1 Based on the bottom three rows of the above table, we can say that if the page is ______________________ (present/

absent) in the main memory, then there ________________ (will be / can’t be) a _____________ (hit / miss) in

________________________________ (TLB / Cache / either TLB or Cache / neither TLB nor Cache).

Ib.2 By increasing the main memory, we can be sure to increase the HIT rate of ___________________ (Cache / TLB / PT).

Ib.3 Please refer to the first row of the above table.

While a __________________ (hit / miss) in TLB guarantees a _________________ (hit / miss) in the Page Table, we note

that a __________________ (hit / miss) in TLB ______________ (does / does not) necessarily imply _________________

_____________________________________ (either a hit or a miss / neither a hit nor a miss) in the page table.

Ib.4 Before a page in the main memory is removed (and perhaps copied back to the secondary storage), any blocks of the

page in the _____________ (cache / TLB) are to be flushed to the main memory and the corresponding translation entry in TLB

shall be ___________________________ (validated / invalidated).

Ib.5 Replacement of an entry in TLB is __________________________________ (possible even though / impossible if) no

pages are altered in the main memory (i.e. no new page is brought into the main memory or no existing page has been removed

from the main memory).

Replacement of a block in cache is _________________________________ (possible even though / impossible if) no pages

are altered in the main memory (i.e. no new page is brought into the main memory or no existing page has been removed from

the main memory).

Ib.6 The block in cache that is being replaced or removed _____________________________________________________

____________________________________________________________________________________________________

(is never written back to the main memory / is always written back to the main memory / written back to the main memory if

write-back policy is used and the block is modified during its residency in the cache).

PTPage Table

C Copyright 2004 Gandhi Puvvada

Part Ic: Let’s take a closer look at Fig.7.25 from the 2nd edi-tion textbook and Fig.7.24 from the 3rd edition textbook repro-duced on the side and answer the following questions.

Ic.1 From these 2 figures we can tell that the TLB uses ____________________________________ (fully associative mapping / set-associative map-ping/ direct mapping) because __________________________________________________________________________________________________________________________________________________________________________________

Ic.2 From these 2 figures we can tell that the cache uses _______________ (fully asso-ciative mapping / set-associative mapping/ direct mapping) be-cause __________________________________________________________________________________________________________________________________________________________________________________

Ic.3 The page size is _________ ________ (the same / different) in these two cases. The page size in the case of the fig. 7.24 of the 3rd edition is _______ KB and it can be inferred from _____________ __________________________________________________________ (which field).

Ic.4 To search for an entry in the TLB we need ________________________________________________________________________________________ (one comparator / two comparators / as many com-parators as there are entries in the TLB) each of ___________ bits wide.

Fig. 7.24 from the third edition textbook

Valid Tag Data

Page offset

Page offset

Virtual page number

Virtual address

Physical page numberValid

1220

20

16 14

Cache index

32

Cache

DataCache hit

2

Byte�offset

Dirty Tag

TLB hit

Physical page number

Physical address tag

TLB

�

Physical address

31 30 29 15 14 13 12 11 10 9 8 3 2 1 0

Fig 7.25 from the second edition of the textbook

Fig 7.24 from the third edition of the textbook

2012

20

18 8 4 2

32

20 12

20

16 14 2

32

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Ic.5 In both cases (in both figures) you use ________________________________________________________________ (Physical address tag / Cache index / Block offset / Byte offset / a concatenations of .......) to index the tag RAM in cache.In Fig.7.25 (from the 2nd edition) you use ________________________________________________________________ (Physical address tag / Cache index / Block offset / Byte offset / a concatenations of .......) to index the cache data RAM.In Fig.7.24 (from 3rd edition) you use ___________________________________________________________________ (Physical address tag / Cache index / Block offset / Byte offset / a concatenations of .......) to index the cache data RAM.

Ic.6 In Fig.7.25 (from the 2nd edition) the shaded area in the cache data RAM is ___________________________________ (an entire cache block / a part of a cache block). In Fig.7.24 (from 3rd edition) the shaded area in the cache data RAM is _________________________________________ (an entire cache block / a part of a cache block). Cache blocks in the two figures are ______________________ (of the same size/different in sizes). The cache block size in the case of fig. 7.24 of the 3rd edition is _____________Bytes. This information is obtained from looking at the size of ______________________________________________________ (state the name of the field(s)).

Ic.7 In both figures we ______________________________ (have to / don’t have to) wait until the translation from virtual address to physical address is done to access the cache. This architecture is called ____________________________________ ___________________ (physically indexed physically tagged (PIPT) / virtually indexed physically tagged (VIPT)) cache.

To convert the current scheme to the other (PIPT to VIPT or VIPT to PIPT as the case may be), in the case of Fig.7.25 (from 2nd edition), we can perhaps (i) consider ___________________________ (increasing / decreasing) the page size to ____________ KBytes from the current size of ____________ KBytes or (ii) consider ____________________________ (increasing / decreasing) the cache size to ____________ KBytes from the current size of ____________ KBytes.

To convert the current scheme to the other (PIPT to VIPT or VIPT to PIPT as the case may be), in the case of Fig.7.24 (from 3rd edition), we can perhaps (i) consider ___________________________ (increasing / decreasing) the page size to ____________ KBytes from the current size of ____________ KBytes or (ii) consider ____________________________ (increasing / decreasing) the cache size to ____________ KBytes from the current size of ____________ KBytes.

Ic.8 Usually TAG RAM is different from Data RAM in cache. For example, on page 7-12 of the classnotes, we have two TAGRAMs each of 4x4 and two Data RAMs of 32x8.

However, in some cases the TAG RAM and the Data RAM can be combined into one wide RAM if the ____________(depth / width) is same for the TAG RAM and the Data RAM.

Ic.9 Consider how the page 7-12 would look like if we change the block size from 8 words (= 8 bytes) to 1 word (= 1 byte).Then there will be 64 block-frames in the 64 location cache and 256 blocks in the main memory. The 64 block-frames in cachewill be organized as 32 sets (since a set contains 2 blocks). Then the set filed is 5 bits, there is no word filed, and the TAG fieldis 3 bits as shown below.

For this case, there will be ______ (1 / 2 / 4 / 32 ) TAG RAMs each of size ___________________ and there will be ______ (1 / 2 / 4 / 32 ) Data RAMs each of size ___________________ . Note that the number of TAG RAMs (similarly thenumber of Data RAMs) depends upon the degree of set associativity (= number of blocks per set (= 2 here)).

SETTAGV

EE457 Homework #7 Page 5 / 12C Copyright 2004 Gandhi Puvvada