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EE241 - Spring 2013Advanced Digital Integrated Circuits

Lecture 15: Latches and Flip-FLops

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Announcements

Homework 3 due next week

Quiz #3 on Monday

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Outline

Last lectureStatistical timing

Intro to latches

This lectureLatches and flip-flops

4. Design for performance

C. Latches and flip-flops

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Latch Pair vs. Flip-Flop

Performance metrics

Delay metricsDelay penalty

Clock skew penalty

Inclusion of logic

Inherent race immunity

Power/Energy MetricsPower/energy

PDP, EDP

Design robustness

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Latches

D

Clk

Clk

Q

Clk

D

Clk

Q

Transmission-Gate Latch C2MOS Latch

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Latches

Courtesy of IEEE Press, New York. 2000

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Latch Pair as a Flip-Flop

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Requirements for the Flip-Flop Design

• High speed of operation:• Small Clk-Output delay• Small setup time• Small hold timeInherent race immunity

• Low power• Small clock load• High driving capability• Integration of logic into flip-flop• Multiplexed or clock scan• Robustness

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Sources of Noise

Courtesy of IEEE Press, New York. 2000

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Types of Flip-Flops

Latch Pair(Master-Slave)

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

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Flip-Flop Delay

Sum of setup time and Clk-output delay is the true measure of the performance with respect to the system speed

T = TClk-Q + TLogic + Tsetup (ignoring skew)

D Q

Clk

D Q

Clk

Logic

N

TLogicTClk-Q TSetup

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Delay vs. Setup/Hold Times

0

50

100

150

200

250

300

350

-200 -150 -100 -50 0 50 100 150 200

Data-Clk [ps]

Clk

-Ou

tpu

t [p

s]

Setup Hold

Minimum Data-Output

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Master-Slave Latch Pairs

Case 1: PowerPC 603 (Gerosa, JSSC 12/94)

Vdd Vdd

Clk

QClk Clkb

Clkb

D

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Master-Slave Latches

Case 2: C2MOS

VddVdd Vdd

Vdd

Vdd Vdd

Vdd

VddClk Ck

Ck

Ck

Ck

CkCkb

Ckb

Ckb

Ckb

QD

Feedback added for static operationLocally generated clockPoor driving capability

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Pulse-Triggered Latches

•First stage is a pulse generator• generates a pulse (glitch) on a rising edge of the clock

•Second stage is a latch• captures the pulse generated in the first stage

•Pulse generation results in a negative setup time•Frequently exhibit a soft edge property

•Note: power is always consumed in the pulse generator

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Pulsed Latch

Kozu, ISSCC’96

Simple pulsed latch

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Intel/HP Itanium 2

Naffziger, ISSCC’02

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Pulse-Triggered Latches

Hybrid Latch Flip-Flop, AMD K-6Partovi, ISSCC’96

Vdd

D

Clk

Q

Q

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HLFF Operation

1-0 and 0-1 transitions at the input with 0ps setup time

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Hybrid Latch Flip-Flop

Partovi et al, ISSCC’96

Skew absorption

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Pulse-Triggered Latches

AMD K-7

Courtesy of IEEE Press, New York. 2000

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Pulse-Triggered Latches

Semi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass, VLSI Circuits’98

Clk

D

Vdd Vdd

Q

Q

Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transitionLatch has one transistor less in stack - faster than HLFF, but 1-1 glitch existsSmall penalty for adding logic

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Pulse-Triggered Latches

Partovi, VLSI’12

Used in a synthesized flow

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Pulse-Triggered Latches

7474, from mid-1960’s

Clk

D

Q

Q

S

R

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Pulse-Triggered Latches

First stage is a sense amplifier, precharged to high, when Clk = 0After rising edge of the clock sense amplifier generates the pulse on S or RThe pulse is captured in S-R latchCross-coupled NAND has different propagation delays of rising and falling edges

Sense-amplifier-based flip-flop, Matsui 1992.DEC Alpha 21264, StrongARM 110

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Sense Amplifier-Based Flip-Flop

Courtesy of IEEE Press, New York. 2000

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Sampling Window Comparison

Naffziger, JSSC 11/02

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Some Interesting Questions

How to compare delays analytically?Similar to LE

Analytical setup time

How to evaluate robustness analytically?

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Next Lecture

Power-performance tradeoffs