ee241 - spring 2001bwrcs.eecs.berkeley.edu/classes/icdesign/ee241_s01/... · 2001-01-18 · ee241 1...

EE241

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UC Berkeley EE241 B. Nikolić

EE241 - Spring 2001Advanced Digital Integrated Circuits

Tu-Th 12:30 – 2:00pm203 McLaughlin


Practical Information� Instructor: Borivoje Nikolić

570 Cory Hall , 3-9297, [email protected] hours: TuTh 2-3pm

� TA: Engling Yeo, yeo@eecs

� Admin: Lea Barker558 Cory Hall, 3-6683, leab@eecs

� Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s01

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Class Organization� +/- 5 assignments� 1 term-long design project

» Phase 1: Proposal (by week 3)» Phase 2: Study (report by week 7)» Phase 3: Design (presentation and report

by final week)» Report and presentations last week of

classes� Final exam


Class Material

� Textbook: “Design of High-Performance Microprocessor Circuits,” by A.Chandrakasan, W. Bowhill, F. Fox

� Must be familiar with “Digital Integrated Circuits - A Design Perspective”, by J. M.Rabaey

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Other Books� Other reference books:

» “High-Speed CMOS Design Styles, by K. Bernstein, et al.

» “Digital Systems Engineering” by W. Dally» “High-Performance System Design: Circuits and

Logic,” by V.G. Oklobdžija» “Low-Power CMOS Design,” by Chandrakasan

and Brodersen» “High-Speed Digital System Design,” by S.H. Hall,

G.W. Hall, J. A. McCall» “Logical Effort: Designing Fast CMOS Circuits,” by

I. Sutherland, B. Sproull, D. Harris


Class Material� List of background material available on

web-site� Selected papers will be made available

on web-site» Protected area, or linked from Inspec

� Papers on http://www.melvyl.ucop.edu� Class-notes on web-site

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Sources� IEEE Journal of Solid-State Circuits

(JSSC)� IEEE International Solid-State Circuits

Conference (ISSCC)� Symposium on VLSI Circuits (VLSI)� Other conferences and journals


Lectures online� The class is webcasted:

» http://bmrc.berkeley.edu/bibs/� It is also videotaped� So use the microphones when you ask

questions

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Class Topics� This course aims to convey a knowledge of advanced concepts of

circuit design for digital LSI and VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, optimization, and layout of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.

� SPECIAL FOCUS in SPRING 2001:» high-performance low-power logic (as needed for digital radio)» interconnect» timing» arithmetic circuits» memory


Class Topics

� Fundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks)

� Design for deep-submicron CMOS - HIGH SPEED (3 weeks)» Static CMOS, transistor sizing, buffer design, high-speed CMOS design styles,

dynamic logic � Design techniques for LOW POWER (2 weeks)

» analysis of power consumption sources » power minimization at the technology, circuit, and architecture level

� Arithmetic circuits – adders, multipliers (2 weeks) � Driving interconnect, high-speed signaling (2 weeks) � Timing (2 weeks)

» Timing analysis, flip-flop/latch design, clock skew, clocking strategies, self-timed design, clock generation and distribution, phase-locked loops

� Memory design (2 week)� Design for test (0.5 weeks)

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Project Topics� High-performance low-power logic � Leakage suppression� Low voltage design� Interconnect in deep-submicron� Arithmetic circuits� High-speed communication� Timing of gigascale circuits� Flip-flops/latches� Memory circuits� Other important circuit topics


Suggested Reading� Chapter 1 – Impact of physical technology on architecture (J.H.

Edmondson),� Chapter 2 – CMOS scaling and issues in sub-0.25µm systems

(Y. Taur)� Technology roadmap (http://public.itrs.net) - and try find some

contradictions� Selected papers from the web:

» S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.

» J. Meindl, “Low Power Microelectronics: Retrospect and Prospect”, Proceedings of the IEEE, April 1995.

» B. Davari et al., “CMOS Scaling for High Performance and Low Power - The Next Ten Years,” Proceedings of the IEEE, April 1995.

» A. Masaki, “Deep-Submicron warms up to High Speed Logic,” IEEECicuits and Devices Magazine, November 1992.

� This lecture is based on IC seminar by S. Borkar, October 2000.

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Tools� HSPICE

» You need an account on cory.eecs� 0.25µm CMOS device models

(TSMC/MOSIS)� Other tools, schematic or layout editors

are optional� Cadence, Synopsys, available on

mingus.eecs


Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months

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Moore’s Law16151413121110

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LOG

2 OF

THE

NUM

BER

OF

CO

MPO

NEN

TS P

ER IN

TEG

RATE

D F

UNCT

ION

Electronics, April 19, 1965.


Transistor Count

1,000,000

100,000

10,000

1,000

10

100

11975 1980 1985 1990 1995 2000 2005 2010

808680286

i386i486

Pentium®Pentium® Pro

K 1 Billion 1 Billion TransistorsTransistors

Source: IntelSource: Intel

ProjectedProjected

Pentium® IIPentium® III

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Technology Evolution (1997 data)

International Technology Roadmap for Semiconductors

17000100006000350021001250750Max frequency [MHz],Local

1831751701601309070Max µµµµP power [W]

1098-97-876-76Metal layers

0.40.5-0.60.6-0.90.9-

1.21.2-1.5

1.5-1.8

1.8-2.5Supply [V]

25355070100140200Channel length [nm]

2014201120082005200219991997Year of Introduction

http://www.sematech.org, or http://public.itrs.net


Technology Evolution (2000 data)International Technology Roadmap for Semiconductors

18617717116013010690Max µµµµP power [W]1.4

1.2

6-7

1.5-1.8

180

1999

1.7

1.6-1.4

6-7

1.5-1.8

2000

14.9-3.611-37.1-2.53.5-22.1-1.6Max frequency

[GHz],Local-Global

2.52.32.12.42.0Bat. power [W]

109-10987Wiring levels

0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V]

30406090130Technology node [nm]

20142011200820042001Year of Introduction

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

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ITRS Technology Roadmap Acceleration Continues


Some Other Scares

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Technology Scaling� Goals of scaling the dimensions by 30%:

» Reduce gate delay by 30% (increase operating frequency by 43%)

» Double transistor density» Reduce energy per transition by 65% (50% power

savings @ 43% increase in frequency� Technology generation spans 2-3 years, but

µP speed doubles every generation (not increased only by 43%)

S. Borkar, IEEE Micro, July 1999.


Moore’s law in Microprocessors

400480088080

8085 8086286

386486 Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

S. Borkar

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Moore’s Law - Logic Density

�Shrinks and compactions meet density goals�New micro-architectures drop density

�Shrinks and compactions meet density goals�New micro-architectures drop density

Sour

ce: I

ntelPentium (R)

Pentium Pro (R) 486386

i860

1

10

100

1000

1.5µ

1.5µ

1.5µ

1.5µ

1.0µ

1.0µ

1.0µ

1.0µ

0.8µ

0.8µ

0.8µ

0.8µ

0.6µ

0.6µ

0.6µ

0.6µ

0.35

µ0.

35µ

0.35

µ0.

35µ

0.25

µ0.

25µ

0.25

µ0.

25µ

0.18

µ0.

18µ

0.18

µ0.

18µ

0.13

µ0.

13µ

0.13

µ0.

13µ

Logi

c D

ensi

ty

2x trend

Logi

c Tr

ansi

stor

s/m

m2

Pentium II (R)


Die Size Growth

40048008

80808085

8086 286386

486Pentium ® procP6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

S. Borkar

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Frequency

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

S. Borkar


Processor Frequency Trend

386486

Pentium(R)

Pentium Pro(R)

Pentium(R) IIMPC750

604+604

601, 603

21264S

2126421164A

2116421064A

21066

10

100

1,000

10,000

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

Mhz

1

10

100

Gat

e D

elay

s/ C

lock

IntelIBM Power PCDECGate delays/clock

Processor freq scales by 2X per

generation

� Frequency doubles each generation� Number of gates/clock reduce by 25%

V.De, S. BorkarISLPED’99

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Power

P6Pentium ® proc

486386

2868086

808580808008

4004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Pow

er (W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

S. Borkar


Obeying Moore’s Law…

400480088080

8085 8086286

386486Pentium ® proc

P6

0.001

0.01

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

900M

1.8B

425M200M

200M--1.8B transistors on the Lead Microprocessor200M--1.8B transistors on the Lead Microprocessor

S. Borkar

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If die size increases

P6Pentium ® proc486386

28680868085

8080

80084004

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

41363228

Die size will have to grow to 30 - 40mmDie size will have to grow to 30 - 40mm

S. Borkar


Frequency will increase

P6Pentium ® proc486

38628680868085

8080800840040.1

1

10

100

1000

10000

100000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

30GHz14GHz

6.5GHz3 Ghz

3 - 30Ghz Frequency3 - 30Ghz Frequency

S. Borkar

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Supply voltage will continue to reduce

0.10

1.00

10.00

1970 1980 1990 2000 2010Year

Supp

ly V

olta

ge (V

)

Only 15% Vcc reduction to meet frequency demandOnly 15% Vcc reduction to meet frequency demand

S. Borkar


Processor Power

386 386

486 486

Pentium(R) Pentium(R) MMX

Pentium Pro (R)

Pentium II (R)

1

10

100

1.5µ1.5µ1.5µ1.5µ 1µ1µ1µ1µ 0.8µ0.8µ0.8µ0.8µ 0.6µ0.6µ0.6µ0.6µ 0.35µ0.35µ0.35µ0.35µ 0.25µ0.25µ0.25µ0.25µ 0.18µ0.18µ0.18µ0.18µ 0.13µ0.13µ0.13µ0.13µ

Max

Pow

er (W

atts

) ?

� Lead processor power increases every generation� Compactions provide higher performance at lower power

Sour

ce: I

ntel

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Active power scaling1

3.1)7.0

1()7.0()14.17.0

1(fCVPower

),7.0

(Freqand,7.0VccIf.1

222 ====××××××××××××========

========

8.1)2()7.0()14.17.0

1(fCVPower

,2Freqand,7.0VccIf.2222 ====××××××××××××========

========

7.2)2()85.0()14.17.0

1(fCVPower

,2Freqand,85.0VccIf.3222 ====××××××××××××========

========


Leakage power increases

10

100

1,000

10,000

100,000

30 40 50 60 70 80 90 100

Temp (C)

Ioff

(na/

u)

0.18u 0.13u 0.1u0.07u 0.05u

8KW

1.7KW

400W 88W

12W

0%

10%

20%

30%

40%

50%

2000 2002 2004 2006 2008Year

Dra

in L

eaka

ge P

ower

Drain leakage will have to increase to meet freq demandResults in excessive leakage power

Drain leakage will have to increase to meet freq demandResults in excessive leakage power

S. Borkar

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Power will be a problem

5KW 18KW

1.5KW 500W

4004800880808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

S. Borkar


A closer look at the power

18KW

5KW

1.5KW

500W 623W375W

225W135W

100

1,000

10,000

100,000

2002 2004 2006 2008Year

Pow

er (W

atts

)

Will be...

Should be...

S. Borkar

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Power density will increase

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

S. Borkar


Power delivery challenges

P6Pentium® proc

486386286

8086

80858080

800840040.01

0.10

1.00

10.00

100.00

1,000.00

1970 1980 1990 2000 2010Year

Icc

(am

p)

P6Pentium® proc

486386

286

8086

80858080

80084004

1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07

1970 1980 1990 2000 2010Year

L(di

/dt)/

Vdd

High supply currents at low voltage:Challenges: IR drop and L(di/dt) noiseHigh supply currents at low voltage:

Challenges: IR drop and L(di/dt) noise

S. Borkar

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Moore’s law challenge

� Double transistors every two years» (Obey Moore’s Law)

� Stay within the expected power trend� Still deliver the expected performance


Expected power trend

500W

1.5KW

5KW

18KW

135W225W

375W623W

100

1,000

10,000

100,000

2002 2004 2006 2008Year

Pow

er (W

atts

)

Will be...

Should be... Pow

er (W

atts

)

P6P5486

386286

80868085

80808008

4004

500W 1.5KW

18KW 5KW

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Goal: Restrict power to the expected trendGoal: Restrict power to the expected trend

S. Borkar

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Restrict transistor leakage

7 GHz5.5 GHz

4 GHz2.5 Ghz

P6Pentium® proc

48638610

100

1000

10000

1985 1990 1995 2000 2005 2010Year

Freq

uenc

y (M

hz)

Reduce leakage �� Frequency will not double every 2 yearsReduce leakage �� Frequency will not double every 2 years

S. Borkar


Do not increase the die size

05

1015202530354045

2000 2002 2004 2006 2008Year

Die

Siz

e (m

m)

Will be...

Reduce die size

Restrict die size to ~ 20 mmRestrict die size to ~ 20 mm

S. Borkar

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Memory has lower power density

1

10

100

1,000

0.25µ0.25µ0.25µ0.25µ 0.18µ0.18µ0.18µ0.18µ 0.13µ0.13µ0.13µ0.13µ 0.1µ0.1µ0.1µ0.1µ 0.07µ0.07µ0.07µ0.07µ 0.05µ0.05µ0.05µ0.05µ

Pow

er D

ensi

ty (W

atts

/cm2 ) Logic

Memory

Exploit memory !Exploit memory !

S. Borkar


Increase memory area

57%55%54%

41%

29%

0%

10%

20%

30%

40%

50%

60%

70%

2000 2002 2004 2006 2008Year

Mem

ory

Are

a %

of t

otal

Use > 50% die area in memoryUse > 50% die area in memory

S. Borkar

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Total memory meets trend

2.5M

5.5M

12M

24M

16168

0

1M

1

10

100

1000

10000

100000

1980 1990 2000 2010Year

Mem

ory

(KB

)

S. Borkar


Power density is reduced

400480088080

8085

8086

286 386486

Pentium ® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Full chip power density is reducedBut local power density will be highFull chip power density is reducedBut local power density will be high

S. Borkar

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Still obey Moore’s Law!

Year

10

100

1,000

10,000

2000 2002 2004 2006 2008

Tran

sist

ors

(MT) Moore's Law.

Actual

Total transistors meet Moore’s LawTotal transistors meet Moore’s Law

S. Borkar


Too good to be true...� Reduced transistor leakage� Reduced frequency� Decreased die size� Increased memory, but reduced logic� Does it deliver expected performance?

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Reduced die size causes “Performance gap”

0%

35%

47%53%

59%

0%

10%

20%

30%

40%

50%

60%

70%

2000 2002 2004 2006 2008Year

Perf

orm

ance

Gap

30-60% performance loss even after meeting Moore’s Law30-60% performance loss even after meeting Moore’s Law

S. Borkar


0

200

400

600

800

Pentiumproc

PentiumPro Proc

PentiumIII proc

Inst

ruct

ion

Cos

t External Mem Latency

Large caches could improve performance

1

10

100

1000

L0 L1 L2 External Mem

Cac

he L

aten

cy (C

lock

s)

0

1

10

100

L0 L1 L2

Rel

ativ

e B

andw

idth

Source: Glenn Hinton, 99

Large on die caches provide:1. Increased Data Bandwidth2. Reduced Latency

External Mem

Future Processors

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Cache size trendCore Logic

Cache

Core Logic

Cache

Core Logic

Cache

0.18µµµµ

0.13µµµµ

0.10µµµµ

Pentium III

Pentium IIIPentium IIPentium

ProPentium

0%

20%

40%

60%

80%

100%

0.7µ0.7µ0.7µ0.7µ 0.5µ0.5µ0.5µ0.5µ 0.35µ0.35µ0.35µ0.35µ 0.25µ0.25µ0.25µ0.25µ 0.18µ0.18µ0.18µ0.18µ 0.13µ0.13µ0.13µ0.13µ 0.10µ0.10µ0.10µ0.10µ

Cache % offull chiparea ?

Cache memory area will dominateCache memory area will dominate


Other design challenges

P6Pentium® proc486386

28680868085

8080800840040.001

0.010.1

110

1001000

10000

1970 1980 1990 2000 2010Year

Logi

c Tr

ansi

stor

s (M

T)

0

5

10

15

20

25

2000 2002 2004 2006 2008Year

Die

Siz

e (m

m) But core will reduce even further...

Die size will reduce...

� Modest increase in Logic transistors

� “Logic Core” size will decrease

� Tools/methodology for memories

� Interconnect RC may not be that big an issue

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Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Tr./ChipTr./Staff Month.

xxxxxx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

Chi

p(M

)

0.01

0.1

1

10

100

1,000

10,000

100,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-Mo.

Source: Sematech

Complexity outpaces design productivity

Com

plex

ity


Summary� Moore’s Law will be obeyed� Barrier: Power delivery, dissipation, and

density� Exploit lower power density of memory--

creates performance gap� Huge on die caches will help maintain

performance trend� Design challenges are different--not

what we think they are!

ee241 - spring 2001bwrcs.eecs.berkeley.edu/classes/icdesign/ee241_s01/... · 2001-01-18 · ee241 1...

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