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EE241 - Spring 2012Advanced Digital Integrated Circuits

MW 2-3:30pm293 Cory

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Practical Information

Instructor:

Borivoje Nikolić550B Cory Hall , 3-9297, bora@eecs

Office hours: MW 3:30pm-4:30pm

GSI: Matthew Weinermgweiner@eecs

Admin: Lea BarkerJust for graded work pickup

Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s12

Class Discussionhttp://piazza.com/class#winter2012/ee241/

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Class Topics

This course aims to convey a knowledge of advanced concepts of circuit design for digital VLSI components in state-of-the-art MOS technologies.

Emphasis is on the circuit design, and optimization for both high performance, and low power for use in applications such as microprocessors, signal and multimedia processors, communications, memory and periphery. Special attention will be devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, variability, power dissipation and timing.

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EECS141 vs. EECS241

EECS 141:Basic transistor and circuit modelsBasic circuit design stylesFirst experiences with design – creating a solution given a set of specifications

EECS 241:Transistor models of varying accuracyDesign under constraints: power-constrained, flexible, robust,…Learning more advanced techniques Study the challenges facing design in the coming yearsCreating new solutions to challenging design problems

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EECS141 vs. EECS241

EECS1410.25m and 90nm CMOS

Unified transistor model

Basic circuit design techniques

Well defined design project

Cadence/Hspice

Focus on principles

EECS241Mostly 45nm CMOS

Different models

Advanced circuit techniques

Open design/research project

Any tool that does the job

Focus on principles

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Special Focus in Spring 2012

Current technology issues

Process variations

Robust design

SRAM

Power and performance optimization

Timing

Clocking and power distribution

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Class TopicsFundamentals - Technology and modeling – Scaling and its limits (2.5 wks)

Introduction to variability (2.5 weeks)Sources of variability, modeling, impact on logic

SRAM in scaled technologies

Timing and variability-aware design (1 week)

Power-performance tradeoffs in design (1 week)

Low power design (3 weeks)

Dynamic and leakage power reduction

High-performance design (2 weeks)Datapaths

Clock and power distribution (1 week)

Project presentations, final exam (1 week)

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Class Organization

4 (+/-) assignments (20%)

4 quizzes (10%)

1 term-long design project (40%)Phase 1: Proposal (Feb 20, week of ISSCC)

Phase 2: Study (report by week 8)

Phase 3: Design (presentation and report by final week)

Report and presentations, April 30

Final exam (30%) (Wednesday, April 25, in-class)

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Class Material

Text: J. Rabaey, “Low Power Design Essentials,” Springer 2009.Available at www.springerlink.com

Baseline: “Digital Integrated Circuits - A Design Perspective”, 2nd

ed. by J. M. Rabaey, A. Chandrakasan, B. NikolićOther reference books:

“Design of High-Performance Microprocessor Circuits,” edited by A. Chandrakasan, W. Bowhill, F. Fox (available at Wiley-IEEE)“CMOS VLSI Design,” 3rd ed, N.Weste, D. Harris

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Class Material

List of background material available on website

Selected papers will be made available on websiteLinked from IEEE Xplore and other resources

Need to be on campus to access, or use library proxy, library VPN (check http://library.berkeley.edu)

Class-notes on websiteNo printed handouts in class!

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Sources

IEEE Journal of Solid-State Circuits (JSSC)

IEEE International Solid-State Circuits Conference (ISSCC)

Symposium on VLSI Circuits (VLSI)

Other conferences and journals

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Project Topics

Focus this semester: Adaptive systems for energy efficiencyDesign components that e.g. operate in a wide range of supply voltages and are resilient to variations and disturbances:

Logic, SRAM, DSP, uP building blocksSupply, clock distributionMeasurement circuits

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Tools

HSPICEYou need an instructional (or research) account

Predictive sub-100nm models (former BPTM)http://www.eas.asu.edu/~ptm/

0.18 /0.13/0.09 m CMOS device models on the class web site

Other tools, schematic or layout editors are optional

Cadence, Synopsys, available on instructional servers

More information on the web site.

EE241 - Spring 2012Advanced Digital Integrated Circuits

Lecture 1: IntroductionTrends and Challenges in

Digital Integrated Circuit Design

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Suggested ReadingInternational Technology Roadmap (http://www.itrs.net) Rabaey, LPDE, Ch 1 (Introduction)Baseline: Rabaey et al, DIC Chapter 3.Chandrakasan, Bowhill, Fox, Chapter 1 – Impact of physical technology on architecture (J.H. Edmondson),Chandrakasan, Bowhill, Fox, Chapter 2 – CMOS scaling and issues in sub-0.25m systems (Y. Taur)Selected papers from the web:

G.E. Moore, No exponential is forever: but "Forever" can be delayed! Proc. ISSCC’03, Feb 2003.

T.-C. Chen, Where CMOS is going: trendy hype vs. real technology. Proc. ISSCC’06, Feb 2006.

S. Chou, Innovation and Integration in the Nanoelectronics Era, Proc. ISSCC’05, Feb. 2005.

S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.

The contributions to this lecture by a number of people (J. Rabaey, S. Borkar, etc) are greatly appreciated.

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Semiconductor Industry Revenues

M. Chang, “Foundry Future: Challenges in the 21st Century,” ISSCC’2007

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Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 12 months. He made a prediction that semiconductor technology will double its effectiveness every 12 months

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”Gordon Moore, Cramming more Components onto Integrated Circuits, (1965).

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Moore’s Law - 1965

“Reduced cost is one of the big attractions of integrated electronics, and the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate.”Electronics, Volume 38, Number 8, April 19, 1965

1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010

TransistorsPer Die

108

107

106

105

104

103

102

101

100

109

1010

Source: Intel

1965 Data (Moore)

Graph from S.Chou, ISSCC’2005

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Moore’s Law - 2005

4004

8080 808680286

386™ Processor486™ Processor

Pentium® ProcessorPentium® II Processor

Pentium® III ProcessorPentium® 4 Processor

Itanium™ Processor

TransistorsPer Die

108

107

106

105

104

103

102

101

100

109

1010

8008

Itanium™ 2 Processor

1K4K

64K256K

1M

16M4M

64M

256M512M

1G 2G

128M

16K

1965 Data (Moore)

Microprocessor

Memory

1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010

Source: IntelGraph from S.Chou, ISSCC’2005

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Moore’s law and cost

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Molecular Electronics

Progress in Nano-Technology

Carbon Nanotubes

Silicon Nanowires

Nanomechanics

Spintronic Storage

Millipede

Spintronic device

T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06

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Technology Strategy / Roadmap 2000 2005 2010 2015 2020 2025 2030

Plan B: Subsytem Integration

R D

Plan C: Post Si CMOS Options

R R&D

Plan Q:

R D

Quantum Computing

Plan A: Extending Si CMOS

R D

T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06

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Technology Evolution

International Technology Roadmap for Semiconductors - 2003 data

Year 2004 2007 2010 2013 2016

Dram ½ pitch [nm] 90 65 45 32 22

MPU transistors/chip 550M 1100M 2200M 4400M 8800M

Wiring levels 10-14 11-15 12-16 12-16 14-18

High-perf. physical gate [nm] 37 25 18 13 9

High-perf. VDD [V] 1.2 1.1 1.0 0.9 0.8

Local clock [GHz] 4.2 9.3 15 23 40

High-perf. power [W] 160 190 220 250 288

Cost-perf. power [W] 84 104 120 138 158

Low-power VDD [V] 0.9 0.8 0.7 0.6 0.5

‘Low-power’ power [W] 2.2 2.5 2.8 3.0 3.0

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Acceleration in the Past

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Printed vs. Physical Gate

Source: Intel, IEDM presentations

m

10000

1000

100

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10

1

0.1

0.01

nm130nm90nm

70nm50nm

Gate Length 65nm

35nm

1970 1980 1990 2000 2010 2020

45nm32nm

22nm

~30nm

0.7X every 2 years

Nominal feature size

180nm250nm

Physical gate length > nominal feature size after 22nm?

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Current Production

32nm (and 28nm): Various flavors - Intel

C.-H. Jan, IEDM’09, P. VanDerVoorn, VLSI Tech’10

Lg = 30/34nm Lg = 46nm Lg > 140nm

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Some Recent Research Devices

Intel’s 30nm transistor, circa 2002

Ion = 570m/mIoff = 60nA/ m

B. Doyle, Intel

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More Recent Research Devices

Intel’s 20nm transistor, circa 2002

B. Doyle, Intel

@0.75V

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Even More Recent Research Devices

L = 10 nmg

10nm device (Intel)

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Almost in Stores - 22nm

FinFET (Tri-gate) – major change in transistor topology

www.intel.com

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Sub-5nm FinFET

Lee, VLSI Technology, 2006

BOX Si fin - Body!

DrainSource

Gate

Gate

Silicon Fin

X. Huang, et al, IEDM’1999.

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More Recent Devices

SOI: Silicon-on-Insulator

Thin-Body SOI MOSFET

Cheng, IEDM’09

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Major Roadblocks

1. Managing complexityHow to design a 10 billion (100 billion) transistor chip?And what to use all these transistors for?

2. Cost of integrated circuits is increasingIt takes >>$10M to design a chipMask costs are many $M in 28nm technology

3. The end of frequency scaling - Power as a limiting factor

Dealing with power, leakages

4. Robustness issuesVariations, SRAM, memory, soft errors, signal integrity

5. The interconnect problem

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Next Lecture

Impact of technology scaling

Characteristics of sub-100nm technologies